TW201143009A - Semiconductor device with substrate-side exposed device-side electrode and method of fabrication - Google Patents

Semiconductor device with substrate-side exposed device-side electrode and method of fabrication Download PDF

Info

Publication number
TW201143009A
TW201143009A TW100118378A TW100118378A TW201143009A TW 201143009 A TW201143009 A TW 201143009A TW 100118378 A TW100118378 A TW 100118378A TW 100118378 A TW100118378 A TW 100118378A TW 201143009 A TW201143009 A TW 201143009A
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor
electrode
exposed
semiconductor device
Prior art date
Application number
TW100118378A
Other languages
English (en)
Other versions
TWI447884B (zh
Inventor
Tao Feng
Anup Bhalla
Original Assignee
Alpha & Omega Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW201143009A publication Critical patent/TW201143009A/zh
Application granted granted Critical
Publication of TWI447884B publication Critical patent/TWI447884B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/781—Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29006—Layer connector larger than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Description

201143009 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明主要涉及半導體裝置結構領域。更確切地說，本 發明是關於製備簡化了晶圓後處理的功率半導體裝置的 裝置結構和製備方法，例如功率金屬-氧化物-半導體場 效應管（MOSFET)以及絕緣栅雙極電晶體（igbt) » [先前技術] [0002] 對於功率MOSFET裝置的系統級封裝而言，有時需要底部 ^ 源極功率MOSFET來優化晶片佈局和/或降低與封裝相關的 寄生互聯阻抗。美國申請11/830951就提出了一個這樣 的例子，其中提出了一種用於DC-DC增強轉換器的多晶片 半導體封裝，具有一個帶有接地的晶片墊的引線框；位 於晶片墊上方的垂直底部源極N-通道m〇SFET ;以及一個 陽極-襯底肖特基二極體，其陽極連接到垂直M〇SFET的漏 極上。肖特基二極體晶片以及垂直M〇SFET晶片以堆疊的 方式共同封裝在單獨的晶片墊上方，肖特基二極體晶片 Q 位於垂直M0SFET晶片上方，使垂直MOSFET的源極電感最 小，並且便於散熱。然而，由於源極和栅極通常形成在 晶片上方，报難連接到柵極墊上，因此要簡單地倒裝 MOSFET晶片十分困難。 由於體型裝置（Bulk Device)電阻低帶來許多好處， 因此半導體工業中十分需要體型裝置，在熱阻低的同時 還能保持小體積，以及用功率半導體裝置很小的襯底厚 度製備薄晶片的能力等。 第1A圖表示於2009年6月3〇日授權的Hebert等人發明的 題為《底部源極LDM0SFET結構及其方法》的美 100118378 表單編號A0101 筮卩百/从π右 1003229267-0 201143009 75541 54中所述的底部-源極橫向擴散m〇S (BS-LDMOS) 裝置的剖面圖。通過植入很深的沉降區115，來製備底部 -源極裝置結構。BSLDM0S裝置位於P +襯底1〇5上，P +襯 底105作為底部源極電極。p—外延層no位於襯底1〇5上 方。在裝置的有源單元區下方，用P +摻雜離子摻雜很深 的沉降區115 ’形成在外延層的深處，並且橫向延伸至漏 極漂移區125的底部，以補償某些積蓄在電晶體中的N—摻 雜物’從而調整N-漂移區125的摻雜水準，使柵極-漏極 電容最小化的同時’維持很低的漏源電阻R. sub. dS0n。 深沉降區115還向下垂直延伸到底部？+襯底105，向上垂 直延伸到本體區150，在柵極氧化物135下方的頂面上構 成一個通道。沉降區11 5既作為一個組合通道，也作為一 個埋入的源極本體接頭，用於連接到形成在頂面附近的 P +本體接觸區155，作為一個頂部溝槽，被源極金屬 170-S覆蓋，N+摻雜源極區160包圍著源極金屬。 被柵極隔片165包圍著的平臺形狀的柵極14〇，被栅極遮 罩材料170-G覆蓋，沉積在栅極氧化層135上方，栅極氧 化層135形成在源極區16〇和漏極漂移區125之間的頂面 上。因此，通過柵極140下方的本體區15〇形成的通道， 栅極140控制源極區160和漏極漂移區丨25之間的電流， 100118378 起一個橫向M0S裝置的作用。漏極區125沉積在場氧化物 130下方，被BPSG層180覆蓋，也可選用鈍化層185覆蓋 。穿過鈍化層185和肿讥層180，刻蝕漏極接頭開口使 頂部漏極金屬199通過接頭Ν +摻雜區19〇接觸漏極區125 ，降低接觸電阻。如圖所示，在平臺柵極140下方的平臺 形狀的氧化物130和135可以通過不同的方法形成。這些 表單編號Α0101 第6頁/共45頁 一 1003229267-0 201143009 方法包括生長或沉積氧化物，從通道區或利用氧化物沉 積工藝的L0C0S類型刻蝕。平臺形狀的柵極14〇具有一個 較長的栅極長度，而且不增加晶胞間距在漏極延伸物上 方進行場電鍍。平臺栅極140為電流在通道和柵極氧化物 135和場氧化物130下方的漏極之間的流動’提供必要的 連接，降低柵漏電容。然而，相應的單元間距與這種結 構和方法密切相關。也就是說，由於沉降區115佔據了太 夕的空間，因此所獲得的單元間距可以相當的大。
隨著原有技術（例如第圖所示）的直通襯底通孔（TSV )技術的出現，如今底部源極功率M〇SFET裝置也可以提 供倒裝晶片法製備，使它的裝置端向下，通過一個獨立 的導電通孔，將其裝置端柵極金屬（底部），重新定向 到其襯底端栅極金屬（頂部）。否則，基本上就沒有電 荷流至裝置結構的其他部分，及其前端製備過程。作為 不例，獨立的導電通孔的結構可以是佈滿氧化物的金屬 填充物。儘管具有上述優點，但是TSV的獨立性，以及在 減薄晶圓的背面上相關的製備步驟，都仍然會帶來不必 要的工藝上的繁瑣與花費。因此，仍然需要進一步簡化 裝置結構和製備工藝。 本申請涉及以下專利申請： 美國專利_請號為1 1/830951，由Francois Hebert等 人於2007年7月31日提交的題為《帶有高效封裝的多晶片 DC-DC增強功率轉換器》的專利，在下文中稱為美國申請 11/830951 。 美國專利申請號為12/749696，由Tao Feng等人於2010 年3月30曰提交的題為《真實無襯底的複合功率半導體裝 100118378 表單編號A0101 第7頁/共45頁 1003229267-0 201143009 置及其方法》的專利，在下文中稱為美國申請 12/749696 。 特此弓『用上述專利内容，作為用於任何及全部意圖的參 考。 【發明内容】 [0003] 提出了帶有襯底端裸露的裝置端電極（SEDE)。該半導 體裝置具有： 一個半導體襯底（SCS)，具有裝置端、裝置端對面的襯 底端以及位於裝置端的半導體裝置區（SDR)。 多個裝置端電極（DSE)，形成在裝置端上方，並與半導 體裝置區相接觸，用於半導體裝置的運行。 至少一個直通襯底溝槽（TST)，穿過半導體襯底延伸， 觸及裝置端電極，從而將它變成裸露在襯底端的裝置端 電極。 為了封裝半導體裝置，可以通過導電連接線（或稱之為 導電内部導線），穿過直通槻底溝槽互聯裸露在襯底端 的裝置端電極。導電内部導線（Conductive interconnector ) 可以是 一個接合引線 、接合 夾片或 焊料凸 塊焊盤。 在一個較典型的實施例中，半導體裝置包括一個與襯底 端相接觸的襯底端電極（SSE)，以及一個SSE上方帶視 窗的襯底端鈍化物（SSPV) °SSPV定義了 SSE的裸露區 ，用於在晶圓後處理封裝時在該處塗抹焊錫材料。半導 體裝置可以是一種垂直半導體裝置（Vertical semiconductor device) ， 其主電流從裝置頂部流至底部 ，或反之亦然。 表單編號A0101 100118378 第8頁/共45頁 1003229267-0 201143009
在一個較佳實施例中，半導體裝置包括一個裝置端鈍化 物（DSPV) ’覆蓋在裸露在襯底端的裝置端電極的裝置 端。對應至少一個裸露在襯底端的裝置端電極，裝置端 電極中的一個非裸露在襯底端的裝置端電極帶有一個延 伸的支撐架’堆積在（裸露在襯底端的裝置端電極）下 方同時通過裝置端鈍化物與這一個裸露在襯底端的裝置 端電極分開’以便在晶圓後處理封裝時給這一個裸露在 襯底端的裝置端電極結構上的支撐。此外，該延伸的支 撐架投射在主半導體襯底平面上的尺寸，基本上包住了 裸露在襯底端的裝置端電極相應的的投射尺寸，即支撐 架投射在主半導體襯底平面上的尺寸大致上大於或等於 夤 ϋ 裝置端電極相應投射在主半導體襯底平面上的尺寸。 在另一個較佳的實施例中，直通槻底溝槽沿主半導體襯 底平面的寬度為TSTW，垂直於主半導體襯底平面的深度 為TSTD，較佳的縱橫比TSTW/TSTD約為0. 2至20。 在一個較典型的實施例中，該半導體裝置是一種底部源 極金屬氧化物半導體場效應管（MOSFET)，具有與半導 體襯底相接觸的襯底端漏極電極（SSDE)，並且相應地 半導體裝置區具有一個源極區、一個栅極區以及一個本 體區。 裝置端電極具有： 一個接觸源極區和本體區的源極電極，並且帶有延伸的 支撐架。 一個接觸柵極區的裸露在襯底端的裝置端電極。 在一個擴展的實施例中，在其裝置端上，該半導體裝置 100118378 表單編號Α0101 第9頁/共45頁 1003229267-0 201143009 還包括’通過絕緣仲介接合層（ILBL)的接合裝置端載 體（裝置端載體）。其中： 半導體襯底具有一個襯底近乎消失的厚度TSCS，該厚度 可以和半導體裝置區的厚度TSDR相比擬。 裝置端載體具有帶圖案的背面載體金屬，接觸裝置端電 極’該裝置端電極不是裸露在襯底端的裝置端電極，一 個帶圖案的正面載體金屬墊和多個直通載體導電通孔分 別將背面載體金屬連接到正面載體金屬墊上。 裳置端載體的厚度TDSC足夠大，可以為半導體裝置提供 充足的結構剛性’襯底近乎消失的厚度TSCS使接觸的裝 置端電極產生很低的背部襯底電阻，直鸿載體導電通孔 使接觸的裝置端電極產生很低的正面接觸電阻。 提出了 一種用於製備帶有至少一個襯底端裸露的裝置端 電極（SEDE)的方法，以便與外部環境互聯。該方法包 括： a)在半導體襯底（SCS)的裝置端中製備一個半導體裝置 區（SDR)。 b) 在裝置端上，製備多個裝置端電極（DSE)和裝置端鈍 化物（DSPV)，並與半導體裝置區相接觸，用於半導體 裝置的運行，裝置端鈍化物使裝置端電極相互絕緣。 c) 製備至少一個直通襯底溝槽（TST)，延伸穿過半導體 襯底，觸及預製的裝置端電極，從而將它變成裸露在襯 底端的裝置端電極。 包括： 棋的圖案 在一個較典型的實施例中，製備直通概底溝槽 在半導體襯底上，使用並形成帶視窗的溝槽掩 ’掩膜視窗相當於直通襯底溝槽的尺寸。 100118378 表單編號A0101 第10頁/共45頁 1003229267-0 201143009 定向刻姓穿過在掩膜視窗内的那部分半導體槻底和半導 體裝置區，並終止在半導體裝置區-裸露在襯底端的裝置 端電極的交界面和半導體裝置區—裝置端鈍化物的交界面 截止，從而製成直通襯底溝槽。 除去帶窗口的溝槽掩膜。
在一個附加的實施例中，在上述步驟b)和C)之間，還 在裝置端鈍化物上方延伸一個帶有橫向延伸支撐架的裝 置端電極，直到它基本上蓋住在裝置端鈍化物下裸露在 襯底端的裝置端電極的裝置端表面◊該裝置端電極不是 所述的預定的裝置端電極。可以通過利用帶視窗的掩臈 ，在所選的裝置端電極的裝置端表面上方電鍍金屬，直 到形成延伸的支撐架為止。 在另一個典型實施例中，提出了一種用於製備薄厚度為
TMOSFET的底部源極MOSFET的方法。該底部源極mosFET 具有一個襯底端裸露的裝置端栅極電極（襯底端裸露的 裝置端柵極電極），便於在晶圓後工藝封裝時互聯到外 部壞境。該方法包括：
a)製備一個厚度為TISS > TMOSFET的臨時半導體襯底 OSS) ，TISS足夠大，可以與傳統的半導體晶圓工藝相
容。 b)在臨時半導體上方利用傳統的半導體晶圓工藝，連續 製備M0SFET裝置區（FETDR)加裝置端源極電極（DSSE )’裝置端栅極電極（DSGE)以及在裝置區上方的裝置 端鈍化物（DSPV)，其中： 裝置端柵極電極位於裝置端源極電極附近β 裝置純化物使裝置端柵極電極和裝置端源極電極相互 100118378 表單編號A0101 第Π頁/共45頁 1003229267-0 201143009 絕緣。 裝置端鈍化物還覆蓋了裝置端柵極電極的裝置端表面。 C)在臨時半導體的背面，在所需厚度為了奶〜 TM0SFET的半導體襯底中，減薄臨時半導體，並在它上面 製備一個襯底端漏極電極（SSDE)。 d)製備—個直通襯底溝槽（TST)，穿過襯底端漏極電極 、半導體襯底加裝置區延伸，並裸露出裝置端柵極電極 的襯底端’從而將它變成襯底端裸露的裝置端栅極電極 襯底端裸露的裝置端柵極電極。 在-個較典型的實施例中，製備直通襯底溝槽包括： 在製備中的裝置的裝置端上方，連接__個臨時的支推概 底，並將其翻轉。 在襯底端漏極電極上方，使用並形成一個帶視窗的溝槽 掩膜的圖案’掩膜視窗相當於直通襯底溝槽的尺寸，刻 蝕掉掩膜視窗内的那部分襯底端漏極電極，但在襯底端 漏極電極-半導體襯底交界面處截止。 定向刻蝕穿過在掩膜視窗内的那部分半導體襯底和裝置 區，但在裝置區-裝置端柵極電極的交界面以及裝置區— 裝置端鈍化物的交界面截止，從而製成直通襯底溝槽。 除去帶窗口的溝槽掩膜。 除去臨時的支撐襯底。 在使用並形成一個帶視窗的溝槽掩膜的圖案之前，對於 上述内容可以作以下改進，在襯底端漏極電極上方可以 製備一個帶視窗的襯底端鈍化物（SSPV)，定義襯底端 漏極電極的裸露區，以便在底部源極M0SFET的晶圓後工 藝封裝時，塗敷焊錫材料。 100118378 表單编號A0101 第12頁/共45頁 1003229267-0 201143009 在另:個實施财，提出卜種具有以下結構的半導體 裝置： 一個在半導體晶片第一邊上的第一導電墊； -個在第-導《下面的溝槽，其中除去了半導體材料 ’其中第-墊從第二邊裸露出來，第二邊在半導編 的對邊上；以及 個導電連接線，從第二邊上連接到導電墊。 在-個較典型的實施例中，導電連接線為接合引線、導 電夾片、導電帶或焊料凸塊焊盤。在另—個較典型的實 施例中’導電連接線至少部分位於溝射，第—端連接 到第-塾上’第二端在半導體晶片的第二邊上的溝槽外 〇 在另-個較典型的實施例中，半導體裝置可以是一個垂 直場效應管（FET)，第-塾是—個柵極塾。柵極塾所處 的位置可以被垂直場效應管的有源區包圍著或部分包圍 著。半導體裝置還包括一個在柵極墊上方的支撐結構。 柵極墊可以被裝置的有源區完全包圍，支撐結構可以是 一個延伸的源極電極◊導電連接線可以是—個接合引線 、導電夾片、導電帶或焊料凸塊焊盤。 對於本領域的技術人員，本發明的這些方面及其多個實 施例將在本說明的其餘部分中做出說明。 【實施方式】 [0004]本文所含的上述及以下說明和附圖僅用於說明本發明的 一個或多個現有的較佳實施例，以及一些典型的可選件 和/或可選實施例。說明及附圖用於解釋說明，就其本身 而言，並不侷限本發明。因此，本領域的技術人員將輕 1003229267-0 100118378 表單編號A0101 第13頁/共45頁 201143009 鬆掌握各種改動、變化和修正。這些改動、變化和修正 也應遇為屬於本發明的範圍。 第1C圖表示原有技術的底部漏極功率MOSFET裝置1的剖 面圖’該裝置帶有—個有源部分la以及一個柵極互連部 分lb ’它們都位於帶有底部漏極金屬層22的半導體襯底 (SCS)21上方。有源部分la在半導體襯底21的半導體 裝置區（SDR) 3内’具有多個相互間隔的源極—本體區23 以及帶溝槽的栅極區24,它們都位於半導體襯底21上方 。在本例中，半導體襯底21可以由一個在重摻雜的接觸 層21a上方的輕摻雜的外延漂移層21b構成。多個源極—本 體區23與—個帶圖案的親源極電極（Intimate source electrode) 25連接而且並聯。與之類似，儘管為了避 免對本領域的技術人員產生不必要的混淆，此處的連接 細即沒有詳述，但是有源部分1&帶溝槽的栅極區24在第 一維度上（X-Y平面）通過一個帶溝槽的柵極滑道區24a ’並聯到位於裝置端鈍化物（DSPV) 29下方的栅極互連 錚分lb的帶圖案的柵極電極26上。裝置端絕緣物28a、 28b位於半導體襯底21上方，分別使帶圖案的栅極電極 26和帶圖案的親源極電極25與下面的半導體裝置結構絕 緣’除了那些需要接觸的地方。 第2A圖表示本發明所述的底部源極功率MOSFET 31的剖 面圖，其中有源部分31a和柵極互連部分3ib都位於帶有 漏極金屬層22的半導體襯底（SCS) 21上。儘管在此沒有 詳述，但是正面處理後，底部源極功率MOSFET 31可以 倒裝。應明確，底部源極功率肋卯耵31的有源部分31a 100118378 極55在帶圖案的親源極 1003229267-0 除了具有額外的帶圖案的源極電 表單編號A0101 第14頁/共45頁 201143009 電極25上方並與之電連接之外，其他都與底部漏極功率 M0SFET裝置1的有源部分la類似。在栅極互連部分 内，直通襯底溝槽（TST) 57已經穿過半導體概底21延 伸’觸及襯底端裸露的裝置端柵極電極（SEDGE) 56，帶 有裸露的襯底端裸露的裝置端柵極電極部分56a。直通概 底溝槽57具有一個直通襯底溝槽尺寸57a，其幾何特徵 是深度為TSTD，寬度為TSTW。
對應襯底端裸露的裝置端柵極電極56,帶圖案的源極電 極55也已經延伸到柵極互連部分31b，還帶有一個延伸的 支樓架55a，堆疊在下面，同時與帶有裝置端鈍化物29 的襯底端裸露的裝置端栅極電極56分開。此外，延伸的 支撐架55a的投射尺寸（χ-γ平面）必須基本上包图住概 底端裸露的裝置端柵極電極56相應的投射尺寸》因此， 在底部源極功率M0SFET 31的晶圓後工藝封裝時，延伸 的支撐架55a可以從結構上支撐襯底端裸露的裝置端桃極 電極5 6 〇 第2B圖表示本發明的一個可選實施例的剖面圖，其中含 有直通襯底溝槽5 7的栅極互連部分31 b位於有源部八 31a之間。因此，源極電極55具有一個延伸的支#年η ’可以完全覆蓋並支撐直通襯底溝槽57。 第3A圖表示本發明的底部源極功率M0SFET 35的第―實 施例的剖面圖。根據第2A圖的說明，對於本領域的技術 人員而言，為了便於說明，在下文中省去對於底部源極 功率M0SFET裝置的裝置端（例如源極-本體區、栅極溝柃 等）的詳細說明》要注意，第3A圖是第2A圖的翻轉圖。 作為特例’半導體襯底21可以由矽製成，帶有—個重推 100118378 表單編號A0101 第15頁/共45頁 1003229267-0 201143009 雜的接觸層21a和一個輕摻雜的漂移層21b，輕摻雜的漂 移層21b是通過在重摻雜的接觸層2ia上方外延生長製成 ，的。漏極金屬層22可以由欽〜錄-銀（nNiAg)製成。帶 圖案的親源極電極25和襯底端裸露的裝置端柵極電極56 可以由鋁-銅（AlCu)製成。裝置端鈍化物29可以由氧 化物和/或聚醯亞胺製成。帶圖案的源極電極55可以由銅 (Cu)製成。一些相關的幾何參數範圍為：裝置端鈍化 物29的厚度~1微米至10微米；延伸的支撐架55a的厚度 〜5微来至20微米。延伸的支撐架55a可以（在垂直方向上 )完全重迭襯底端裸露的裝置端栅極電極56，甚至延伸 到襯底端裸露的裝置端柵極電極56上方，以提供額外的 支撐。 第3B圖表示底部源極功率MOSFET 35省去有、原部八的a 圓後工藝封裝。在本例中，通過—相1 ^ ^個導電連接線33 (例 如接合引線）’穿過直通襯底溝榉 货57，連接到襯底端裸 露的裝置端柵極電極56上。對; ' 痛域的技術人員而言 ，只要TSTD和TSTW可以適應導雷砝& 电建接線及其相關的封裝 工具，就可以用接合板或焊料凸塊焊盤（Wderb )代替導電連接線33。在這一點π TSTW / TSTD較佳 的縱橫比約為〇. 2至20。作為一個鉍狀 U較典型的實施例， TSTW的範圍可以從10〇微米至5〇〇 從25微緑500微米。還要注意，如果^TSTD的範圍可以 57襯有絕緣材料，以鈍化半導體概 而要直通襯底溝槽 ，炎目至氏21不同的裸露表面 時（參見美國申請1 2/749696 )，产^ &時’作為晶圓後工 藝封裝的一部分，可以用包圍著接人 a。W線33並同時鈍化 100118378 半導體襯底21的成型混料填充直通璁底溝槽π。 第16頁/共45頁 表單編號A0101 篱16頁/共45頁 1003229267-0 201143009
作為示例，第3C圖表示含有底部源極功率M〇SEFT 35以 及引線框32的半導體封裝50。底部源極功率M〇SFET 35 安裝在引線框部分32b上，引線框部分32b用作下墊板。 因此，親源極電極25被連接到引線框部分32b上，（例如 通過在部分32b上安裝帶圖案的源極電極55)。通過任意 適合的導電連接線33a ’例如接合引線、導電帶、導電炎 片等’穿過直通襯底溝槽57 ’可以將柵極電極（sedge 56)連接到引線框部分32c上。通過導電連接線36 (也可 以包括接合引線、導電帶、導電夾片等），漏極金屬層 22也可以連接到引線框部分32a上，如果有必要，其他的 半導體晶片（圖中沒有表示出）也可以同底部源極功率 M0SFET 35 —起封裝。此後，成型混料37 (其輪廓如圖 中虛線所示）密封封裝50。成型混料37也可以填充在直 通襯底溝槽57中。
第4A圖至第4H圖表不第3A圖所示的底部源極功率jjosfeT 裝置的製備過程。在第4A圖中，用傳統的半導體晶圓工 藝’在臨時的半導體襯底（ISS) 70上方，一起製備 M0SFET裝置區（FETDR) 71同帶圖案的親源極電極25、 帶圖案的柵極電極26以及裝置端鈍化物29,臨時的半導 體襯底（ISS) 70的厚度TISS足夠大，可以與傳統的半 導體晶圓工藝相容。作為一個典型示例，TISS的範圍可 以在600-800微米之間。帶圖案的親源極電極25位於帶 圖案的柵極電極26附近，帶圖案的柵極電極26通過裝置 端鈍化物29與它絕緣，裝置端鈍化物29也覆蓋了帶圖 案的柵極電極26的裝置端表面。 在第4B圖中，在裝置端鈍化物29上方，同延伸的支撑架 100118378 表單編號A0101 第17頁/共45頁 1003229267-0 201143009 55a —起延伸帶圖案的親源極電極25，直到它基本蓋住了 裝置端純化物29下方的帶g案的柵極電極26的裝置端表 =。它的實現可以通過在帶圖案的親源極電極25的裝置 端表面上方，通過-個帶梘窗的掩膜（此處省略，以簡 化視圖）電鏟金屬，直到形成延伸的支稽架…為止。作 為—個典型示例，可以使用帶掩膜的厚銅（Cu)電鍍工 藝。此外，厚Cu電鑛之後可以進行化學機械抛光（CMp) ，使電鍍的頂面平整，然後形成一個鎳_金（Ni_Au)層 或薄焊錫層，以防止銅被氧化。 在第4C圖中，將臨時的半導體襯底（ISS) 7〇的背面向下 減薄至所需厚度為TSCS的半導體襯底21。然後，在半導 體襯底21的襯底端（即裝置端的對面）上方，形成—個 襯底端漏極金屬層22。例如，通過背部研磨工藝，Tscs 的厚度可以減至50微米-300微米之間，並用鈦_鎳_銀（ Ti~Ni-Ag)製備漏極金屬層22。 第4D圖至第4G圖表示製備直通襯底溝槽57，穿過漏極金 屬層22延伸，半導體襯底21含有M0SFET裝置區（FET-⑽）71並裸露出襯底端裸露的裝置端栅極電極56。在第 仙圖中，在製備中裝置的装置端上定向連接一個臨時的 支携'概底72，並使其概底（漏極）端向上。例如，可以 用玻璃、矽或廣義的處理晶圓等製備臨時的支撐襯底72 〇 在第4E圖中，在漏極金屬層22上方，使用一個帶視窗的 溝槽掩膜74並形成圖案，掩膜視窗75相當於直通襯底溝 槽57預製的直通襯底溝槽尺寸57a (χ_γ平面）。例如 ’帶視窗的溝槽掩膜74可以是一種光致抗蚀劑。 100118378 表單編號A0101 第18頁/共45頁 ιη的 201143009 圖中，定向舰掩膜視窗％下面的那部分半導體 ^ 21和裝置區7卜_終止«置區7卜襯底端裸 、置端栅極電極56的交界面以及裝置區7卜裝置端 如物29的交界面處’從而製成直通襯底溝槽57。例 ^ 時可以利用一些帶有錐度的垂直溝槽壁的等離子
^ 在個較典型的實施例中，TSTD的範圍為100微米 :〇微米，典型的TSTW的範圍為150微米至200微米， 最小約為100微米。 在第4Η圖中，剝去帶視窗的溝槽掩膜74，然後脫粘並除 去臨時的支撐襯底72 ’製成具有所需厚度TMOSFET的底 部源極功率MOSFET。
第5圖表示本發明所述的底部源極功率M〇SFET部分33b的 另—個實施例的剖面圖。此時，在漏極金屬層22上方， 添加—個帶視窗的襯底端鈍化物（SSPV) 27，從而限定 一個裸露的漏極金屬區80，用於在晶圓後處理封裝時， 塗抹和限制焊錫材料流入此處。例如，可以用氧化物、 氮化物或聚醯亞胺等製備SSPV27。在製備過程中，可以 在漏極金屬層22 (第4E圖）上方使用帶視窗的溝槽掩膜 74並形成圖案之前，製備SSPV 27 » 第6圖表示添加了裝置端載體（DSC) 40的底部源極功率 MOSFET部分34b的另一個實施例的刮面圖。底部源極功 率MOSFET部分34b除了不帶有延伸的源極電極55以及延 伸的支撐架55a，並在其裝置端上添加了由載體材料40a 100118378 表單编號A0101 第19頁/共45頁 1003229267_0 201143009 製成的裝置端載體（DSC) 40 (例如通過絕緣仲介粘合層 (ILBL) 60將載體材料4〇a組合或粘合在裝置端上）之 外，其他都與第3A圖所示的裝置基本相同。更多的細節 請參照美國申請1 2/749, 696 ’本領域的技術人員應理解 以下特點： 半導體襯底21應帶有襯底近乎消失的厚度TSCS，即半導 體概底21包含的襯底部分接觸層21a可以在厚度上減少 並近似消失’由於裝置端載體4〇的結構剛性，厚度TSCS 可以與半導體裝置區的厚度TSDR相比擬。 裝置端載體（DSC) 40具有多個帶圖案的背面載體金屬 41a、41b、41c，接觸帶圖案的源極電極25，一個帶圖 案的正面載體金屬墊42a和多個直通載體導電通孔43a、 43b、43c分別將帶圖案的背面載體金屬化4ia ' 41b、 41c連接到帶圖案的正面載體金屬化墊42a上。 裝置端載體40的厚度TDSC足夠大，可以為半導體裝置提 供充足的結構剛性’襯底近乎消失的厚度TSCS產生一個 很低的背部襯底電阻，直通載體導電通孔43a、43b、 43c對接觸的帶圖案的親源極電極25產生彳艮低的正面接觸 電阻。 另一個不太顯著的特點是，由於在底部源極功率MOSFET 部分34b的晶圓處理時，裝置端鈍化物29並不需要覆蓋 襯底端裸露的裝置端柵極電極56，因此頂部裸露的襯底 端裸露的裝置端栅極電極56簡化了貼裝裝置端載體40 之前相關的晶圓級探測測試。在某些更加典型的實施例 中，TDCS的範圍約為1〇〇微米至400微米。TSCS的範圍約 為5微米至100微米’鑒於裴置端載體40的剛性，不存在 100118378 表單編號A0101 第20頁/共45頁 1003229267-0 201143009 擊穿的危險，TSCS也可以小於5〇微米。 第7圖表示類似於第6圖的底部源極功率M〇SFET的另一個 實施例的剖面圖，但是其中裝置端載體4〇被成型混料9〇 代替，成型混料90包圍著焊料凸塊焊盤95，通過源極電 極55a ’連接到親源極電極25上。還可選擇，在襯底端裸 露的裝置端柵極電極56上形成栅極電極551；)，作為製備 源極電極55a的副產品，但從源極電極55a或從焊料凸塊 焊盤95上沒有連接。所添加的源極電極55a可以有利於順 利連接到焊料凸塊焊盤95的焊錫材料上。
Ο [0005] 100118378 上述說明包含許多特殊細節，這些細節僅作為對本發明 現有的較佳實施例提供解釋說明，而不應看做是對本發 明範圍的侷限。例如，添加帶有溝槽柵極的功率m〇sfet 裝置，本發明所述的底部源極功率m〇sfet的原理也適用 於橫向雙擴散MOSFET (LDMOS)以及垂直雙擴散m〇sfet (VDMOS)等其他裝置類型。又例如，本發明的原理也適 用於微型電子機械系統（MEMS)的結構和製備。以上說 明和附圖參照具體結構’給出了各種典型的實施例。對 於本領域的技術人員應顯而易見，本發明也可用於其他 具體形式，上述各種實施例經過輕鬆修改，就可以適合 於其他具體應用。鑒於本專利檔，本發明的範圍不應由 上述具體的典型實施例所限定，而應由以下的申請專利 範圍限定。在申請專利範圍的内容及其等價範圍内的任 何及全部修正，都應屬於本發明的真實意圖和範圍内。 【圖式簡單說明】 為了更加完整地忒明本發明的各種實施例，可參照附圖 。但是，這些附圖僅用作解釋說明，並不作為本發明範 1003229267-0 表單編號Α0101 第21頁/共45頁 201143009 圍的侷限。 第1A圖表示美國專利7554154中所述的第一項原有技術 的帶溝槽的底部源極橫向擴散MOS (BS-LDM0S)裝置的 剖面圖； 第1B圖表示利用直通襯底通孔（TSV)的第二項原有技術 底部源極功率MOSFET裝置的剖面圖； 第1C圖表示帶有多個帶溝槽的栅極的原有技術的底部漏 極功率MOSFET裝置的剖面圖； 第2A圖表示本發明的一個實施例所述的帶有多個帶溝槽 的栅極的底部源極功率MOSFET裝置的剎面圖； 第2B圖表示本發明的一個可選實施例所述的帶有多個帶 溝槽的柵極的底部源極功率MOSFET裝寰的剖面圖； 第3A圖表示本發明的第一實施例所述的底部源極功率 MOSFET裝置的剖面圖； 第3B圖表示利用接合引線，第3人圖所禾裝置的晶圓後工 藝封裝； 第3C圖表示一種含有本發明所述的底部源極功率m〇SFET 裝置的半導體封裝； 第4A圖至第4H圖表示製備第3A圖所示裝置的製備工藝； 第5圖表示本發明所述的底部源極功率M〇SFET裝置的第二 實施例的剖面圖； 第6圖表示本發明所述的帶有額外的裝置端載體的底部源 極功率MOSFET裝置的第三實施例的剖面圖；以及 第7圖表示本發明所述的底部源極功率裝置的另一 個實施例的剖面圖。 100118378 【主要元件符號說明】 表單編號A0101 第22頁/共45頁 1003229267-0 201143009 [0006] TST/57 :直通襯底溝槽 TST :寬度
W TSTD :深度 MOSFET : M0SFET :功率金屬-氧化物-半導體場效應管 ISS/70 :臨時半導體襯底 SCS/21 :半導體襯底 SDR/3 :半導體裝置區 DSC/40 :裝置端載體 la/31a :有源部分
lb/31b :柵極互連部分 21a :接觸層 21b :漂移層 22 :漏極金屬層 23 :源極-本體區 2 4 .拇極區 2 4 a .棚極滑道區 25 :親源極電極 26 :柵極電極 28a/28b :裝置端絕緣物 29 :裝置端鈍化物（DSPV) 31/35 :底部源極功率MOSFET 32 :引線框 32a/32b/32c :引線框部分 33a/36 :導電連接線 33b/34b :底部源極功率MOSFET部分 37/90 :成型混料 100118378 表單編號A0101 第23頁/共45頁 1003229267-0 201143009 40a :載體材料 41a/41b/41c :背面載體金屬 42a :正面載體金屬墊 43a/43b/43c :直通載體導電通孔 50 :半導體封裝 5 5 :源極電極 55a :支撐架 55b :柵極電極 56 :裝置端柵極電極（SEDGE) 56a :柵極電極部分 57a :直通襯底溝槽尺寸 60 :絕緣仲介粘合層（ILBL) 71 : M0SFET裝置區（FETDR) 72 :支撐襯底 74 :溝槽掩膜 75 :掩膜視窗 80 :漏極金屬區 95 :焊料凸塊焊盤 105 : P+襯底 110 : P-外延層 115 :沉降區 125 :漏極漂移區 130 :場氧化物 13 5 :柵極氧化物 140 :柵極 160 : N +摻雜源極區 100118378 表單編號A0101 第24頁/共45頁 1003229267-0 201143009 165 :柵極隔片 170-S :源極金屬 170-G :栅極遮罩材料 180 : BPSG層 185 :純化層 190 : Ν +摻雜區 199 :頂部漏極金屬 Ο
100118378 表單編號Α0101 第25頁/共45頁 1003229267-0

Claims (1)

  1. 201143009 七 申請專利範圍： .一種帶有裸露在襯底端的梦 姑里'"夏端電極（SEDE)的半導體 裝置，該半導體裝置包括： 幻千命si 一個半導體襯底（SCS)，且 底端以及位於裝置端的半;^置端、裝置端對面的襯 多個裝置端電極（DSE)开體裝置區（識）； 體裝置區相接觸，用於半^*在裝置端上方，並與半導 至少一個直通襯底溝槽（ …丁以及 觸及裝置端電極，從而牌’穿過半導體襯底延伸’ 底端的裝置端電極，裝置端電極變成裸露在襯 襯底_裸露在概底：=接線，直通 一端 _端 ^ 裝置，其中，該半導體裝置是一 個垂直半導體裝置。 .如申請專利範圍第丨項所 雷搞Μ議、 所迷的帶有裸露在襯底端的裝置端 電極（SEDE)的半導體 裝置，其中，還包括一個與襯底 端相接觸的襯底端電極（SSE)。 •如申請專利範圍第丨項所 4的帶有裸露在襯底端的裝置端 電極（SEDE)的半導體 44 A m衮置，其中，導電連接線是一個 '引線、接合灸片、導電帶或焊料凸塊焊盤。 ^專利範圍第丨項所述的帶有裸露在襯底端 電極（SEDE)的半導體验 置’其中’還包括對應於裸露 在襯底端的裝置端電極 DSPV)。 位於襄置端的裝置端鈍化物( .如申請專職項所述的帶有裸露在襯底端的裝置端 100118378 表單編號A0101 第26頁/共45頁 1003229267-0 201143009 電極（SEDE)的半導體裝置，其中，還包括一個對應至 少—個裸露在襯底端的裝置端電極的農置端鈍化物（ DSPV)，以及 除了所述的至少一個裸露在襯底端的裝置端電極之外，在 所述的裝置端電極中還有一個預設電極帶有一個延伸的支 推架’堆積在下方同時通過所述的裝置端鈍化物與所述的 至少一個裸露在襯底端的裝置端電極分開，以便在晶圓後 處理封裝時給所述的至少一個裸露在襯底端的裝置端電極 結構上的支撐。 7 .如申請專利範圍第6項所述的帶有裸露在襯底端的裝置端 電極（SEDE)的半導體裝置，其中，該延伸的支撐架尺 寸投射在主半導體襯底平面上的尺寸，包住了所述裸露在 襯底端的裝置端電極相應的投射尺寸。 8 .如申請專利範圍第1項所述的帶有裸露在襯底端的裝置端 電極（SEDE)的半導體裝置，其中，直通襯底溝槽沿主 半導體襯底平面的寬度為TSTW，垂直於主半導體觀底平 面的深度為TSTD，縱橫比TSTW/TSTD為0. 2至20。 9 ·如申請專利範圍第8項所述的帶有裸露在襯底端的裝置端 電極（SEDE)的半導體裝置，其中，TSTW為100微米至 500微米，TSTD為25微米至500微米。 10 .如申請專利範圍第1項所述的帶有裸露在襯底端的裝置^ 電極（SEDE)的半導體裝置’其中，還包括一個與半導 體襯底相接觸的襯底端漏極電極，並且相應地： 半導體裝置區具有一個源極區、一個柵極區以及一個本體 區；並且 裝置端電極具有： 1003229267-0 100118378 表單编號A0101 第27頁/共45頁 201143009 一個接觸源極區和本體區的源極電極，並且帶有延伸的支 撐架；以及 一個接觸柵極區的裸露在襯底端的裝置端電極， 從而使該半導體裝置是一種底部源極金屬氧化物半導體場 效應管（M0SFET)。 11 .如申請專利範圍第10項所述的帶有裸露在襯底端的裝置端 電極（SEDE)的半導體裝置，其中，源極電極還包括一 個延伸的支撐架，支撐著裸露在襯底端的裝置端電極。 12 .如申請專利範圍第1項所述的帶有裸露在襯底端的裝置端 電極（SEDE)的半導體裝置，其中，還包括在它的裝置 端，通過絕緣仲介接合層（ILBL)的接合裝置端載體（ DSC)，其中： 半導體襯底具有一個襯底近乎消失的厚度TSCS，該厚度 可以和半導體裝置區的厚度TSDR相比擬； 裝置端載體具有帶圖案的背面載體金屬，接觸一個裝置端 電極，該裝置端電極不是一個裸露在襯底端的裝置端電極 ，一個帶圖案的正面載體金屬墊和多個直通載體導電通孔 分別將背面載體金屬連接到正面載體金屬墊上；並且 裝置端載體的厚度TDSC足夠大到 裝置端載體可以為半導體裝置提供充足的結構剛性，襯底 近乎消失的厚度T S C S使接觸的裝置端電極產生很低的背 部襯底電阻，直通載體導電通孔使接觸的裝置端電極產生 很低的正面接觸電阻。 13 . —種用於製備帶有至少一個裸露在襯底端的裝置端電極（ SEDE)的方法，以便與夕卜部環境互聯，其中，該方法包 括： 100118378 表單編號A0101 第28頁/共45頁 1003229267-0 201143009 ' a)製備一個半導體襯底（SCS)，並在它的裝置端中製 備一個半導體裝置區（SDR); b) 在裝置端上，製備多個裝置端電極（DSE)，並與半 導體裝置區相接觸，用於半導體裝置的運行；並且 c) 製備至少一個直通襯底溝槽（TST)，延伸穿過半導 體襯底，觸及一個預定的裝置端電極，從而將所述的裝置 端電極變成所述的至少一個裸露在襯底端的裝置端電極。 14 .如申請專利範圍第13項所述的方法，其中，製備直通襯底 溝槽包括： 〇 定向刻蝕穿過在預定掩膜視窗内的那部分半導體襯底和半 導體裝置區，並終止在半導體裝置區-裸露在襯底端的裝 置端電極的交界面，從而製成直通襯底溝槽。 15 .如申請專利範圍第13項所述的方法，其中，還包括，在步 驟b )和c )之間： bl)提供一個帶有橫向延伸的支撐架延伸一個裝置端電極 ，直到覆蓋住所述的至少一個裸露在襯底端的裝置端電極 的裝置端表面，該裝置端電極不是所述的預定的裝置端電 ^ 極，提供裝置端鈍化物（DSPV)位於延伸的支撐架和裸 露在襯底端的裝置端電極之間，並將它們分開。 16 .如申請專利範圍第15項所述的方法，其中，延伸所述的裝 置端電極包括通過帶視窗的掩膜，在所述的裝置端電極的 裝置端表面上方電鍍金屬，直到形成延伸的支撐架為止。 17 . —種半導體裝置，具有： 一個由半導體材料製成的半導體晶片，並且具有第一邊和 第二邊； 一個位於半導體晶片第一邊上的導電第一墊； 100118378 表單編號A0101 第29頁/共45頁 1003229267-0 201143009 一個在導電第一墊下方的溝槽，其中除去半導體材料，通 過所述的溝槽，第一墊從半導體晶片的第二邊上裸露出來 :以及 ^ 一個導電的連接線，從所述的第二邊穿過所述的溝槽，連 接到所述的導電第一墊上。 18 .如申請專利範圍第17項所述的半導體裝置，其中，導電的 連接線為接合引線、導電夾片或導電帶或焊料凸塊焊盤。 19 .如申請專利範圍第17項所述的半導體裝置，其中，導電連 接線至少部分位於所述的溝槽内，導電連接線第一端連接 到第一墊上，導電連接線第二端在半導體晶片第二邊上所 述的溝槽外。 20 .如申請專利範圍第17項所述的半導體裝置，其中，所述的 半導體裝置為垂直場效應管（FET)，所述的第一墊為栅 極墊。 21 .如申請專利範圍第20項所述的半導體裝置，其中，栅極墊 所在的位置至少部分被FET的有源區包圍。 22 .如申請專利範圍第20項所述的半導體裝置，其中，還包括 柵極墊上方的一個支撐結構。 23 .如申請專利範圍第20項所述的半導體裝置，其中，導電連 接線為接合引線、導電夾片、導電帶或焊料凸塊焊盤。 100118378 表單編號A0101 第30頁/共45頁 1003229267-0
TW100118378A 2010-05-28 2011-05-25 帶有襯底端裸露的裝置端電極的半導體裝置及其製備方法 TWI447884B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/790,773 US8866267B2 (en) 2010-05-28 2010-05-28 Semiconductor device with substrate-side exposed device-side electrode and method of fabrication

Publications (2)

Publication Number Publication Date
TW201143009A true TW201143009A (en) 2011-12-01
TWI447884B TWI447884B (zh) 2014-08-01

Family

ID=45021400

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100118378A TWI447884B (zh) 2010-05-28 2011-05-25 帶有襯底端裸露的裝置端電極的半導體裝置及其製備方法

Country Status (2)

Country Link
US (2) US8866267B2 (zh)
TW (1) TWI447884B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8525334B2 (en) * 2010-04-27 2013-09-03 International Rectifier Corporation Semiconductor on semiconductor substrate multi-chip-scale package
US8987878B2 (en) * 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
US8519473B2 (en) 2010-07-14 2013-08-27 Infineon Technologies Ag Vertical transistor component
US20120146111A1 (en) * 2010-12-14 2012-06-14 Shu-Ming Chang Chip package and manufacturing method thereof
US9373613B2 (en) * 2013-12-31 2016-06-21 Skyworks Solutions, Inc. Amplifier voltage limiting using punch-through effect
CN106463426B (zh) * 2014-06-27 2020-03-13 索尼公司 半导体器件及其制造方法
KR102382635B1 (ko) * 2016-06-09 2022-04-05 매그나칩 반도체 유한회사 전력 반도체의 웨이퍼 레벨 칩 스케일 패키지 및 제조 방법
US11222858B1 (en) * 2020-06-19 2022-01-11 Alpha And Omega Semiconductor International Lp Semiconductor package having enlarged gate pad and method of making the same
CN114496987B (zh) * 2022-04-18 2022-08-02 绍兴中芯集成电路制造股份有限公司 Mosfet功率器件及其形成方法、csp封装模块

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566749B1 (en) * 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US8294208B2 (en) * 2008-03-04 2012-10-23 International Rectifier Corporation Semiconductor device having a gate contact on one surface electrically connected to a gate bus on an opposing surface

Also Published As

Publication number Publication date
US9355953B2 (en) 2016-05-31
US20110291245A1 (en) 2011-12-01
TWI447884B (zh) 2014-08-01
US8866267B2 (en) 2014-10-21
US20150035049A1 (en) 2015-02-05

Similar Documents

Publication Publication Date Title
TW201143009A (en) Semiconductor device with substrate-side exposed device-side electrode and method of fabrication
TW493262B (en) Vertical conduction flip-chip device with bump contacts on single surface
TWI482281B (zh) 半導體裝置及其製造方法
US7646079B2 (en) Semiconductor device, method of manufacturing the same, circuit board, and method of manufacturing the same
JP5319084B2 (ja) 半導体装置
US8742490B2 (en) Vertical power transistor die packages and associated methods of manufacturing
TWI459506B (zh) 形成半導體裝置的背部電極到頂邊接觸窗之結構及方法
US10553675B2 (en) Isolation of semiconductor device with buried cavity
TW201041089A (en) Power MOSFET package
TW201807806A (zh) 具有叉指狀背對背mosfet的器件結構
TW201140800A (en) Stackable power MOSFET, power MOSFET stack, and process of manufacture
TW201205762A (en) Wafer level chip scale package
CN102651398A (zh) 半导体器件
TW200929408A (en) Wafer level chip scale packaging
US11335627B2 (en) Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
KR101138580B1 (ko) 웨이퍼 레벨 벅 컨버터
CN102738036A (zh) 晶圆级mosfet金属化
US20070152269A1 (en) Vertical DMOS device in integrated circuit
CN106024856B (zh) 包括平面栅极和沟槽场电极结构的半导体器件
TW200830517A (en) Semiconductor device
TW201234601A (en) Vertical semiconductor device and manufacturing method therefor
JP2009164288A (ja) 半導体素子及び半導体装置
CN102832244B (zh) 带有衬底端裸露的器件端电极的半导体器件及其制备方法
CN114026684A (zh) 半导体器件
US11031321B2 (en) Semiconductor device having a die pad with a dam-like configuration