201033988 六、發明說明： 【發日^^斤屬之技術領域】 本發明係涉及一種在液晶顯示裝置中分離源‘驅動器積體電路 (integrated circuit，1C)之接地的技術，尤其係涉及一種在具有玻璃上置晶片 (chip-on-glass，COG)串級結構的液晶顯示裝置中，具彼此分離之高電壓電 源接地和低電壓電源接地的源極驅動器積體電路。 【先前技術】 液晶顯示器(liquid crystal display，LCD)係指利用液晶分子的排列依所 ❹施加之電壓改變的特性，經穿過液晶的光線顯示影像資料的裝置 。在這些 裝置中’最常使用利用矽ic製造方法所製造的薄骐電晶體(thin film transistor，TFT) LCD。 第1圖係說明傳統LCD結構的示意圖。 TFT LCD包括LCD面板30和驅動電路。LCD面板30包括TFT陣列 基板和彩色濾光片基板，彼此面向並且其間相距一預定間隔而彼此附接， - 並且液晶層注入至在該預定間隔之中。驅動電路係配置以驅動LCD面板30。 驅動電路包括閘極驅動器1C 40，配置以依次對每一圖框施加掃描信號 至閘極線、源極驅動器1C 20，配置以驅動源極線，以響應閘極驅動器IC 的掃描信號、時序控制單元10，配置以控制閘極驅動器IC 4〇和源極驅動 〇 器1C 20並輸出像素資料、以及電源供應單元(圖中未示），配置以供應用於 LCD裝置中的各種驅動電壓。 傳統上，已使用各種方法將驅動器IC連接至LCD面板。近來，隨著 精細安裝技術的發展，通常已此用COG方法，其中驅動器ic係直接安裝 和連接在玻璃基板上。 第2圖係說明傳統c〇G型LCD裝置的示意圖。 參考第2圖’可看出源極驅動器IC晶片221至224和閘極驅動器忙 晶片231至233係直接安裝在LCD面板的玻璃基板240上。 在COG方法中，安裝在LCD面板上的源極驅動器IC晶片和閘極驅動 器1C晶片，係透過玻璃上佈線，L〇G)方法而彼此連接在該 方法中，係將#號線直接安裝在LCD面板的基板上，並分別從時序控制單 4 201033988 元210和電源供應單元接收控制信號和驅動電壓。 …當晶片利用上述C0G方法安裝時’可使用各種方法以接收資料、控 信號和電源。在這些方法中，已㈣列串級方法，其她畴控制單^輸 出的各種龍和控偷號以及賴供應單元所供觸電_施加至第一^ 極驅動器1C，虹其他祕驅動器IC係配置以依次 ^201033988 6. Technical Description: The present invention relates to a technique for separating the ground of a source 'driver integrated circuit (1C) in a liquid crystal display device, and more particularly to A liquid crystal display device having a chip-on-glass (COG) cascade structure, a source driver integrated circuit having a high voltage power supply ground and a low voltage power supply ground separated from each other. [Prior Art] A liquid crystal display (LCD) refers to a device that displays image data through light passing through a liquid crystal by utilizing a characteristic that a liquid crystal molecule is arranged to change depending on a voltage applied thereto. Among these devices, a thin film transistor (TFT) LCD manufactured by the 矽ic manufacturing method is most often used. Figure 1 is a schematic diagram showing the structure of a conventional LCD. The TFT LCD includes an LCD panel 30 and a driving circuit. The LCD panel 30 includes a TFT array substrate and a color filter substrate which are faced to each other and attached to each other at a predetermined interval therebetween - and the liquid crystal layer is implanted into the predetermined interval. The drive circuit is configured to drive the LCD panel 30. The driving circuit includes a gate driver 1C 40 configured to sequentially apply a scan signal to each of the frames to the gate line, the source driver 1C 20, and configured to drive the source line in response to the scan signal and timing control of the gate driver IC The unit 10 is configured to control the gate driver IC 4 and the source driver unit 1C 20 and output pixel data, and a power supply unit (not shown) configured to supply various driving voltages for use in the LCD device. Traditionally, various methods have been used to connect the driver IC to the LCD panel. Recently, with the development of fine mounting technology, the COG method has been generally used, in which the driver ic is directly mounted and attached to a glass substrate. Fig. 2 is a schematic view showing a conventional c〇G type LCD device. Referring to Fig. 2, it can be seen that the source driver IC chips 221 to 224 and the gate driver busy chips 231 to 233 are directly mounted on the glass substrate 240 of the LCD panel. In the COG method, a source driver IC chip and a gate driver 1C chip mounted on an LCD panel are connected to each other through a glass-on-wire (L〇G) method, and the ## line is directly mounted on the method. The control panel and the driving voltage are received from the timing control unit 4 201033988 element 210 and the power supply unit, respectively, on the substrate of the LCD panel. ...when the wafer is mounted using the above COG method, various methods can be used to receive data, control signals, and power. Among these methods, the (four) column cascade method, the other dragon control and the sneak number of the other domain control unit and the electric shock supplied by the supply unit are applied to the first electrode driver 1C, and the other secret driver IC system configuration In order to ^
接收資料、控制錢和魏。 崎器1C 第3，係說明傳統c〇G串級結構中所供應之電源的方法之圖式。 參考第3 ®，連接至n綠應賴猶路和連接 ❹ VSSj的線路係高電壓電源供應線，配置以供應電源至在職驅^ 内狀尚電壓下運作的電路，並且連接至第三電源供應電塵vcc的 =和連接至第四電職應電壓VSS1的線路魏電㈣職麟配置以 供應電源至在源極,_H IC _之低電壓下運作的電路。 所供ίί 有⑽__ LCD裝置巾，供應裝置 所供應的電源係施加至第—源極驅動器IC，並且第二源極驅動器冗透 一源，驅動器1C内部的電源供應線來接收電源。 技=一源極驅動$ IC從第一源極驅動胃IC接收電源時，由於第一源 驅^器1C的電流和電源供應線的電阻^可在非常高位準處發生接地彈 ®曰驅動源極驅動器IC的輸出時，接轉跳的位準進一步增加。Receive information, control money and Wei. Kawasaki 1C No. 3 is a diagram illustrating a method of supplying power in a conventional c〇G cascade structure. Refer to Section 3®, the line-connected high-voltage power supply line connected to nGreen and the VSSj, configured to supply power to the circuit operating under the operating voltage and connected to the third power supply. The electric dust vcc = and the line connected to the fourth electric duty voltage VSS1 Wei (4) is configured to supply power to the circuit operating at the low voltage of the source, _H IC _. The power supply supplied by the supply device is applied to the first-source driver IC, and the second source driver is redundant to a source, and the power supply line inside the driver 1C receives the power. Technology = a source driver $ IC from the first source drive gastric IC receiving power, due to the current of the first source driver 1C and the power supply line resistance ^ can occur at a very high level grounding elastic 曰 曰 drive source When the output of the pole driver IC is output, the level of the jump jump is further increased.
㈣ΐ 圖係說明具有C〇G串級結構的傳MCD裝置中源極驅動器1C 内部接地電壓短路之狀態的圖式。 β ^考第4A圖’除非增加單獨的過程’冑電壓電源供應線的接地GND ’ ^疋Φ、電源供應電壓VSS2 ’以及低電壓電源供應線的接地gnd，即是 S ^供應電堡VSS1，由於位牌而短路’或者由於金屬線而在源極驅動(4) The figure shows a state in which the internal ground voltage of the source driver 1C is short-circuited in the MCD device having the C〇G cascade structure. β ^考第4A' 'unless adding a separate process' 胄 voltage supply line ground GND ' ^ 疋 Φ, power supply voltage VSS2 ' and the grounding gnd of the low-voltage power supply line, that is, S ^ supply electric VSS1, Short circuit due to position plate or drive at source due to metal wire
Is 1C内部短路。 你夕^ ί吏用^種C〇G串級結構時’接地彈跳的位準可在接收高電壓電源運 雷厭器1<：所有輸出之區間期間變得非常高。進而，可導致使用低 電壓電源的數崎輯電路的運作丨現問題。 魏明具有c〇g串級結構的傳統lcd裝置中源極驅動器ic 内部接地電壓短路之狀態的另—圖式。 參考第4B圖，可看出使用高電壓電源的電路方塊之P位拼HV-PW和 5 201033988 使用低電壓電源的電路方塊之p位解LV_PW係在基板上短路。 ^。第5圖係顯不具有C0G串級結構的傳统LCD裝置中透過測量源極驅 Λ動器1C的接地位準所獲得之結果的圖式。 ， 參考第5圖，第二源極驅動器IC具有接地位準，係第一源極驅動器忙 的接地位準之二城二倍以上，並且接地位轉跳輕間對應至源極驅動 器1C的輪出運作區間。 【發明内容】 因此，本發明已努力以解決先前技術中所發生的問題，並且本發明的 目的是提供具有C0G串級結構的源極驅動器1C，其中高電壓電源接地和低 髎 €塵電源接地係分離的，以防止當驅動源極駆動器IC時高電壓電源接地的 雜訊對使用低電壓的邏輯電路造成影響。 、 為了達到上述目的，依據本發明的一個特點，提供了一種具彼此分離 之高電壓電源接地及低電壓電源接地的C0G串級結構之源極驅動器積體電 路。該源極驅動器積體電路包括·_ 一第一電源供應電壓線，配置以提供第 一電源供應電壓至使用高電壓的高電壓運作電路方塊；一第二電源供應電 壓線，配置以提供第二電源供應電壓至使用高電壓的高電壓運作電路方 塊；一第三電源供應電壓線，配置以提供第三電源供應電壓至使用低電壓 的低電壓運作電路方塊；以及一第四電源供應電壓線，配置以提供第四電 φ 源供應電壓至使用低電壓的低電壓運作電路方塊。該第二電源供應電壓線 和該第四電源供應電壓線係彼此分離。 v 【實施方式】 現在參考圖式更加詳細地描述本發明較佳實施例。無論如何，圖式和 說明書中所用的相同的符號說明代表相同或類似的部分。 本發明的優點是提供具彼此分離之高電壓電源接地和低電壓電源接地 的源極驅動器1C，以防止高電壓接地電屋的雜訊對使用低電麼電源的邏輯 電路造成影響。 以下，將參考圖式詳細描述本發明之實施例。 第6圖係說明依據本發明實施例之源極驅動器1C中高電壓電源接地和 201033988 低電壓電源接地的金屬線彼此分離之狀態的圖式β 參考第6圖，依據本發明實施例的源極驅動器IC 6〇〇，其中高電壓電 源接地和低電壓電源接地係彼此分離，包括第一電源供應電壓線61〇、第二 電源供應電壓線620、第三電源供應電壓線63〇和第四電源供應電壓線64〇。 第一電源供應電壓線610係配置以提供第一電源供應電壓vdd至使用 咼電壓的高電壓運作電路方塊650’而第二電源供應電壓線62〇係配置以提 供第二電源供應電壓VSS2至高電壓運作電路方塊65〇。 第三電源供應電壓線630係配置以提供第三電源供應電壓vcc至使用 低電壓的低電壓運作電路方塊660,而第四電源供應電壓線64〇係配置以提 供第四電源供應電壓VSS1至低電壓運作電路方塊66〇。 ® 鱗’LCD面板的鶴^ IC包括需要高電壓處理類比信號的高電壓運 作電路方塊和需要低電壓的低電壓運作電路方塊，如數位邏輯電路。 在本發明實施例中，高電壓運作電路方塊65〇在第一電源供應電壓 VDD和第二電源供應電壓VSS2之間運作，而低電壓運作電路方塊66〇在 -第二電源供應電壓VCC和第四電源供應電壓vssi之間運作。 在此情況下’第二電源供應電壓VSS2對應至使用高電壓的高電壓運作 電路方塊650的接地電壓HV-GND，而第四電源供應電壓VSS1對應至使 用低電壓的低電壓運作電路方塊660的接地電壓LV-GND。 在本發明實施例中’移除高電壓運作電路方塊65〇的接地電壓hv_gnd Ο 和低電壓運作電路方塊_的接地電壓lv-gnd之的金祕，以分離高 電壓運作電路方塊65G的接地 HV_GND和低電舰作轉方塊66〇的 接地電壓LV-GND。 金屬線的移除可在佈線過程巾仔細設計，並且可使驗驗工具檢查高 電壓運作電路方塊65G的接地是否與低電壓運作電路方塊66〇的接 分離。 同時，環繞，電壓運作電路方塊的⑽可提供在低電壓運作電路方塊 下面’從而分離高電遂運作電路方塊65〇的接地電壓勝_和低電壓運 作電路方塊660的接地電壓lv-GM)。 在此情況下’ _可為深層，其形絲低電壓運作電路方塊下 面深層的位置，從而環繞低電壓運作電路方塊。 7 201033988 - 第7圖係說明源極驅動器ic中高電壓電源接地和低電壓電源接地利用 位阱彼此分離之狀態的圖式。 參考第7圖’可看出依據本發明實施例的源極驅動器1C包括提供在低 電壓運作電路方塊LV NMOS/LV PMOS下面的深層N位阱DNW，以分離 高電壓運作電路方塊HV NOMS/HV PMOS的接地電壓HV-GND與低電壓 運作電路方塊LV NMOS/LV PMOS的接地電壓LV-GND，從而接地電壓不 會短路。 即是，高電壓電源接地和低電壓電源接地係透過形成在基板上的位阱 而彼此完全分離。由於先前技術中已知形成位阱的製程，因此在此省略描 述0 ❹ 第8圖係顯示依據本發明實施例中測量源極驅動器IC的接地位準所獲 得之結果的圖式。 當高電壓運作電路方塊的接地電壓HV-GND與低電壓運作電路方塊的 接地電壓LV-GND彼此分離，高電壓運作電路方塊的接地電塵HV_GND的 彈跳所導致的電源雜訊不會對低電壓運作電路方塊造成影響。因此，可減 少低電壓運作電路錢的接地電壓LV-GND轉跳，如第8圖所示。 、依據本發明實施_祕驅動器IC巾’高電地和低電壓接地係彼 此分離’以減少祕轉^ IC的輸丨驅動運行躺發生接轉跳。因此， 由於高電壓轉賴導賴電雜财會干擾使職電壓的邏輯 ® 電路，從而可提高低電壓電源的頻率界限和電壓界限。 、可理解的疋上所述者僅為用以解釋本發明之較佳實施例，並非企圖據 以對本發明作任何形式上之關，是以，凡有在相同之發鴨神下所作有 關本發明之任何修飾或變更，皆仍應包括在本發明意圖保護之範鳴。 【圖式簡單說明】 =所附賦其巾提供關於本發明實施觸進-步理解並且結合與構成本 =明書的-部份，朗本發明的實施例並域描述_同提供對於 施例之原則的解釋。圖式中： 钱乃貫 第1圖係說明傳統LCD結構的示意圖； 第2圖係說明傳、统COGS LCD裝置的示意圖； 201033988 . $3 +級結射所供應之龍财法之圖式； 第4A圖係說明具有C0G串級結構的傳統LCD裝置中源極驅動 内部接地電壓短路之狀態的圖式，] ^ 第4B圖係說明具有C〇g串級結構的傳統LCD裝置中源極驅動 内部接地電壓短路之狀態的另一圖式； 第5圖係顯示具有C〇g串級結構的傳統LCD裝置中透過測量源極 動器1C的接地位準所獲得之結果的圖式； 、 第6圖係說明依據本發明實施例之源極驅動器IC中高電壓電源接地和 低電壓電源接地的金屬線彼此分離之狀態的圖式； 第7圖係說明依據本發明實施例之源極驅動器1C中高電壓電源接地和 低電壓電源接地利用位阱彼此分離之狀態的圖式；以及 第8圖係顯示依據本發明實施例中測量源極驅動器IC的接地位 得之結果的圖式。 厅獲 【主要元件符號說明】 10 時序控制單元 240 玻璃基板 20 源極驅動器1C 600 源極驅動器1C 30 LCD面板 610 第一電源供應電壓線 40 閘極驅動器1C 620 第二電源供應電壓線 210 時序控制單元 630 第二電源供應電壓線 221 源極驅動器1C晶片 640 第四電源供應電壓線 222 源極驅動器1C晶片 650 冋電壓運作電路方塊 223 源極驅動器1C晶片 660 ,電壓運作電路方塊 224 源極驅動器1C晶片 VCC 第二電源供應電壓 231 閘極驅動器1C晶片 VDD 第一電源供應電壓 232 閘極驅動器1C晶片 VSS1 第四電源、供應電壓 233 閘極驅動器1C晶片 VSS2 第二電振供應電麼Is 1C internal short circuit. When you use the C〇G cascade structure, the level of the ground bounce can become very high during the interval of receiving the high voltage power supply 1<: all outputs. Further, the operation of the digital chip circuit using a low voltage power supply can cause problems. Wei Ming has another pattern of the state in which the grounding voltage of the source driver ic is short-circuited in the conventional lcd device of the c〇g cascade structure. Referring to Figure 4B, it can be seen that the P-bit HV-PW and 5 201033988 of the circuit block using the high-voltage power supply are short-circuited on the substrate by the p-bit LV_PW of the circuit block using the low-voltage power supply. ^. Fig. 5 is a view showing the result obtained by measuring the ground level of the source drive actuator 1C in a conventional LCD device having no COG cascade structure. Referring to FIG. 5, the second source driver IC has a ground level, which is more than twice the busy ground level of the first source driver, and the ground bit transitions to the wheel of the source driver 1C. Out of the operating range. SUMMARY OF THE INVENTION Accordingly, the present invention has been made in an effort to solve the problems occurring in the prior art, and an object of the present invention is to provide a source driver 1C having a COG cascade structure in which a high voltage power supply is grounded and a low power supply is grounded. Separated to prevent noise from grounding of high voltage power supplies when driving the source actuator IC, which affects the use of low voltage logic circuits. In order to achieve the above object, in accordance with a feature of the present invention, a source driver integrated circuit of a COG cascade structure having a high voltage power supply ground and a low voltage power supply ground separated from each other is provided. The source driver integrated circuit includes a first power supply voltage line configured to provide a first power supply voltage to a high voltage operating circuit block using a high voltage, and a second power supply voltage line configured to provide a second a power supply voltage to a high voltage operation circuit block using a high voltage; a third power supply voltage line configured to provide a third power supply voltage to a low voltage operation circuit block using a low voltage; and a fourth power supply voltage line, The configuration is to provide a fourth electrical φ source supply voltage to a low voltage operating circuit block using a low voltage. The second power supply voltage line and the fourth power supply voltage line are separated from each other. [Embodiment] A preferred embodiment of the present invention will now be described in more detail with reference to the drawings. In any case, the same symbolic descriptions used in the drawings and the description represent the same or similar parts. It is an advantage of the present invention to provide a source driver 1C having a high voltage power supply ground and a low voltage power supply ground separated from each other to prevent the noise of the high voltage grounded house from affecting the logic circuit using the low power supply. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 6 is a diagram showing a state in which a high voltage power supply ground of a source driver 1C and a metal line of a low voltage power supply ground of 201033988 are separated from each other according to an embodiment of the present invention. FIG. 6 is a diagram showing a source driver according to an embodiment of the present invention. IC 6〇〇, wherein the high voltage power ground and the low voltage power ground are separated from each other, including the first power supply voltage line 61〇, the second power supply voltage line 620, the third power supply voltage line 63〇, and the fourth power supply The voltage line is 64 〇. The first power supply voltage line 610 is configured to provide a first power supply voltage vdd to a high voltage operation circuit block 650' using a threshold voltage and a second power supply voltage line 62 to configure a second power supply voltage VSS2 to a high voltage. Operation circuit block 65〇. The third power supply voltage line 630 is configured to provide a third power supply voltage vcc to the low voltage operation circuit block 660 using the low voltage, and the fourth power supply voltage line 64 is configured to provide the fourth power supply voltage VSS1 to low The voltage operation circuit block 66〇. The ® 鳞 LCD panel's crane IC includes high-voltage operating circuit blocks that require high-voltage processing of analog signals and low-voltage operating circuit blocks that require low voltage, such as digital logic circuits. In the embodiment of the present invention, the high voltage operation circuit block 65 is operated between the first power supply voltage VDD and the second power supply voltage VSS2, and the low voltage operation circuit block 66 is at the second power supply voltage VCC and the first The four power supply voltage vsSi operates. In this case, the 'second power supply voltage VSS2 corresponds to the ground voltage HV-GND of the high voltage operation circuit block 650 using the high voltage, and the fourth power supply voltage VSS1 corresponds to the low voltage operation circuit block 660 using the low voltage. Ground voltage LV-GND. In the embodiment of the present invention, the ground voltage hv_gnd Ο of the high voltage operation circuit block 65 and the ground voltage lv-gnd of the low voltage operation circuit block _ are removed to separate the ground HV_GND of the high voltage operation circuit block 65G. And the low-voltage ship makes the grounding voltage LV-GND of the turn 66. The removal of the wire can be carefully designed in the routing process and the inspection tool can check whether the ground of the high voltage operating circuit block 65G is separated from the low voltage operating circuit block 66. At the same time, the surrounding (10) voltage operating circuit block can be provided under the low voltage operating circuit block to separate the ground voltage _ and the ground voltage lv-GM of the low voltage operating circuit block 660. In this case, _ can be a deep layer whose low voltage operates below the deep square of the circuit block, thereby operating the circuit block around the low voltage. 7 201033988 - Fig. 7 is a diagram showing the state in which the high voltage power supply ground and the low voltage power supply ground in the source driver ic are separated from each other by the bit wells. Referring to FIG. 7, it can be seen that the source driver 1C according to an embodiment of the present invention includes a deep N-bit well DNW provided under the low voltage operation circuit block LV NMOS/LV PMOS to separate the high voltage operation circuit block HV NOMS/HV. The PMOS ground voltage HV-GND and the low voltage operation circuit block LV NMOS / LV PMOS ground voltage LV-GND, so that the ground voltage will not be short-circuited. That is, the high voltage power supply ground and the low voltage power supply ground are completely separated from each other by the bit well formed on the substrate. Since the process of forming a bit well is known in the prior art, the description is omitted here. FIG. 8 is a view showing the result obtained by measuring the ground level of the source driver IC in accordance with an embodiment of the present invention. When the ground voltage HV-GND of the high voltage operation circuit block and the ground voltage LV-GND of the low voltage operation circuit block are separated from each other, the power supply noise caused by the bounce of the ground electric dust HV_GND of the high voltage operation circuit block does not affect the low voltage. The operation of the circuit block has an effect. Therefore, the ground voltage LV-GND of the low voltage operating circuit can be reduced, as shown in Fig. 8. According to the present invention, the high-power ground and the low-voltage grounding are separated from each other to reduce the transmission of the transmission drive. Therefore, because the high voltage is transferred to the logic ® circuit that interferes with the operating voltage, the frequency limit and voltage limit of the low voltage power supply can be increased. It is to be understood that the foregoing description is only illustrative of the preferred embodiments of the invention, and is not intended to be in any form in accordance with the invention. Any modifications or alterations should still be included in the intended protection of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings provide a touch-step understanding of the implementation of the present invention and incorporate the components of the present invention, and the embodiments of the present invention are described in the same manner. An explanation of the principles. In the drawings: Figure 1 shows the schematic diagram of the traditional LCD structure; Figure 2 shows the schematic diagram of the transmission and COGS LCD device; 201033988 . The diagram of the Longfa method supplied by the $3 + level junction; 4A is a diagram illustrating a state in which the source driving internal ground voltage is short-circuited in a conventional LCD device having a C0G cascade structure, ] ^ FIG. 4B illustrates a source driving internal in a conventional LCD device having a C〇g cascade structure. Another diagram of a state in which the ground voltage is short-circuited; FIG. 5 is a diagram showing a result obtained by measuring the ground level of the source electrode 1C in a conventional LCD device having a C〇g cascade structure; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a view showing a state in which a metal line of a high voltage power supply ground and a low voltage power supply ground are separated from each other in a source driver IC according to an embodiment of the present invention; FIG. 7 is a view showing a high voltage in a source driver 1C according to an embodiment of the present invention. A diagram of a state in which the power supply ground and the low voltage power supply are separated from each other by the bit wells; and FIG. 8 is a view showing a result of measuring the grounding position of the source driver IC in accordance with an embodiment of the present invention. Hall [Key Component Symbol Description] 10 Timing Control Unit 240 Glass Substrate 20 Source Driver 1C 600 Source Driver 1C 30 LCD Panel 610 First Power Supply Voltage Line 40 Gate Driver 1C 620 Second Power Supply Voltage Line 210 Timing Control Unit 630 Second Power Supply Voltage Line 221 Source Driver 1C Chip 640 Fourth Power Supply Voltage Line 222 Source Driver 1C Chip 650 冋 Voltage Operation Circuit Block 223 Source Driver 1C Chip 660, Voltage Operation Circuit Block 224 Source Driver 1C Wafer VCC Second Power Supply Voltage 231 Gate Driver 1C Chip VDD First Power Supply Voltage 232 Gate Driver 1C Wafer VSS1 Fourth Power Supply, Supply Voltage 233 Gate Driver 1C Chip VSS2 Second Power Supply