201031032 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體發光元件用模板基板等，更詳言 之，係關於包含ΠΙ族氮化物化合物半導體之半導體發光 元件用模板基板及其製造方法等。此外，本發明係關於使 用半導體發光元件用模板基板之半導體發光元件之製造方 法及半導體發光元件。 【先前技術】 近年來，III族氮化物半導體作爲半導體發光元件用 的材料受到矚目。III族氮化物半導體，係於藍寶石（ sapphire )等基板上，藉由有機金屬化學氣相成長法（ MOCVD )或分子線取向附生（epitaxy )法（MBE法）等 形成薄膜。 作爲減低對使用這樣的III族氮化物半導體之半導體 ❹ 發光元件的內部之光的封入，改善光的取出效率之方法， 例如可以舉出專利文獻1。 於專利文獻1，記載著對第一層表面加工凹凸，而在 具有與第一層不同折射率之第二層內埋入凹凸使其成長， 形成這些凹凸狀之折射率界面後，於其上藉由形成被層積 包含發光層的半導體結晶層的元件構造，而被賦予使產生 於發光層的橫方向的光朝向外界發出之新穎構造的發光元 件。 此外，於專利文獻2，亦記載著藉由在基板上形成由 -5- 201031032 非與基板C面平行的表面所構成之複數之凸部，而在基板 上形成由C面所構成的平面與由凸部所構成的上面之加工 基板，接著於該加工基板上使取向附生成長前述III族氮 化物半導體層，使凸部以III族氮化物半導體層掩埋之III 族氮化物半導體層之製造方法。 一般而言加工前的基板，例如藍寶石板其平坦度 GBIR很差，特別是越大口徑的基板越不容易製造平坦的 基板。例如2吋（約50mm)之藍寶石板的平坦度GBIR 通常爲1 5μιη程度。 [先行技術文獻] [專利文獻] [專利文獻1丨日本專利特開2002-2806 1 1號公報 [專利文獻2]國際公開公報第2008/08 1 7 1 7號小冊 【發明內容】 [發明所欲解決之課題] 然而，一般在藍寶石製的基板表面形成凹凸時，會有 在其上很難使結晶性優異的III族氮化物半導體層成長的 問題。例如，在被形成複數凸部的基板上以取向附生成長 ΠI族氮化物半導體層的場合，必須要使複數之凸部的大 小或形狀形成爲均一。亦即，凸部的大小或形狀若有差異 ’或者複數之凸部偏處於基板上的話，其後III族氮化物 半導體層不會均一地成長。因此，不只會有使取向附生成 -6 - 201031032 長ΠΙ族氮化物半導體層後所得的半導體發光元件晶片之 最終的產率大幅減低，而且還有作爲半導體兀件之發光特 性降低的情形。 此外，作爲在基板上形成複數凸部的方法’通常採用 光蝕刻法。但是，根據本案發明人檢討的結果’判明了在 此場合，基板厚度的差異如果偏大的話，會有凸部大小或 形狀變成不均一的傾向。 Φ 本發明之目的在於提供能夠以高產率製造光取出效率 優異之半導體發光元件的半導體發光元件用模板基板及其 製造方法，以及半導體發光元件之製造方法。 [供解決課題之手段] 亦即，根據本發明，提供以下之[Π〜[26]。 [1] 一種半導體發光元件用模板基板，其特徵爲至少具有 :於表面被形成複數凸部的基板、於基板之複數凸部被形 Φ 成之面上被形成薄膜之III族氮化物半導體所構成之緩衝 層；顯示被形成凸部之基板的表面之未被形成均一形狀之 凸部所佔之面積的比率之不良面積率在1 0%以下。 [2] 如前項[1]之半導體發光元件用模板基板，其中基板之 表面之不良面積率不包含零。 [3] 如前項[1]或[2]之半導體發光元件用模板基板，其中不 良面積率在0.0 1 %〜10%之範圍內。 [4] 如前項[1]~〜[3]之任一之半導體發光元件用模板基板， 其中基板之複數凸部，具有基部寬幅〇·〇5μηι〜5μιη、高度 201031032 0.05μιη~5μιη，且高度爲基部寬幅之1/4以上’且鄰接之 凸部間之間隔爲基部寬幅之〇.5倍〜5倍。 [5] 如前項[1]~[4]之任一之半導體發光元件用模板基板’ 其中基板之複數凸部，具有最大直徑〇.5μιη〜2μιη、高度 0.5μηι〜2μηι，且與鄰接之凸部之間隔爲〇.5μηι〜2μιη。 [6] 如前項[1]~[5]之任一之半導體發光元件用模板基板’ 其中基板係由藍寶石（sapphire )所構成。 [7] 如前項[1]〜[6]之任一之半導體發光元件用模板基板’ 參 其中基板之最大直徑爲 50mm〜200mm，基板的厚度爲 0 · 5 mm〜2mm。 [8] 如前項[1]~[7]之任一之半導體發光元件用模板基板’ 其中緩衝層之ΠΙ族氮化物半導體，係藉由濺鍍法形成之 氮化鋁膜。 [9] 如前項[1]~[8]之任一之半導體發光元件用模板基板’ 其中於緩衝層上，進而包含由ΙΠ族氮化物半導體所構成 之下底層。 © [1〇]如前項[9]之半導體發光元件用模板基板，其中III族 氮化物半導體，係氮化鎵（GaN )。 [1 1]如前項[1]〜[8]之任一之半導體發光元件用模板基板’ 其中於緩衝層上，進而包含由III族氮化物半導體所構成 之下底層及η型半導體層之層積構造。 [12]如前項[1 1]之半導體發光元件用模板基板，其中III 族氮化物半導體，係氮化鎵（GaN ) ，n型半導體層包含 η型氮化鎵系化合物半導體。 -8- 201031032 [13] 如前項[1]〜[12]之任一之半導體發光元件用模板基板 ，其中基板’使用平坦度GBIR在ΙΟμιη以下之藍寶石板 ，藍寶石板之表面被形成複數凸部。 [14] 如前項[13]之半導體發光元件用模板基板，其中平坦 度GBIR，在0·01μιη〜5μηι之範圍內。 [15] —種半導體發光元件用模板基板之製造方法，係具有 ΠΙ族氮化物半導體層的半導體發光元件用模板基板之製 φ 造方法，其特徵爲具有：在平坦度GBIR爲1〇μιη以下之 藍寶石製的基板表面形成複數凸部之基板加工步驟，及於 基板之表面藉由濺鍍形成由III族氮化物半導體所構成之 厚度0.0 2 μιη〜0.1 μιη之緩衝層之緩衝層形成步驟。 [16] 如前項[15]之半導體發光元件用模板基板之製造方法 ，其中被形成於基板之凸部，具有最大直徑0.05μηι〜5μιη 、高度0.05μπι〜5μπι之半球形狀。 [17] 如前項[15]或[16]之半導體發光元件用模板基板之製 φ 造方法’其中顯示被形成複數凸部的基板的表面之未被均 一形成之凸部所佔之比率之不良面積率在1 0 %以下。 Π8]如前項[15]〜[17]之任一之半導體發光元件用模板基板 之製造方法，其中基板之部位平坦度SBIR爲1.5 μιη以下 〇 [19] 一種半導體發光元件之製造方法，其特徵爲包含：於 前項Π]至[14]之任一之半導體發光元件用模板基板，進而 依序形成由III族氮化物半導體所構成之η型層、發光層 及Ρ型層之步驟。 -9- 201031032 U〇]如前項[19]之半導體發光元件之製造方法，其中包含 將半導體發光元件用模板基板，移至與製造該半導體發光 元件用模板基板時所使用之取向附生（epitaxial )成長爐 不同之第2取向附生成長爐，於半導體發光元件用模板基 板，進而依序形成由III族氮化物半導體所構成之η型層 、發光層及Ρ型層之步驟。 [21] —種半導體發光元件係具有III族氮化物半導體層之 半導體發光元件，其特徵爲具有：至少具有於表面被形成 @ 複數凸部的基板、於被形成複數之凸部之面上被形成薄膜 之III族氮化物半導體所構成之緩衝層之模板基板、及依 序被形成於模板基板之緩衝層上之III族氮化物半導體所 構成之η型層，發光層及Ρ型層；於模板基板之基板的表 面，顯示未被形成均一形狀之凸部所佔之面積的比率之不 良面積率在1〇°/。以下。 [22] 如前項[21]之半導體發光元件，其中模板基板之基板 的表面之不良面積率不包含零。 〇 [23] 如前項[21]或[22]之半導體發光元件，其中模板基板 之基板，係平坦度GBIR在ΙΟμηι以下之藍寶石板。 [24] 如前項[21]或[23]之半導體發光元件，其中模板基板 之緩衝層之ΠΙ族氮化物半導體，係藉由濺鍍法形成之氮 化鋁膜。 [25] 如前項[21]~[24]之任一之半導體發光元件，其中於模 板基板之緩衝層上，進而包含由ΠΙ族氮化物半導體所構 成之下底層。 -10- 201031032 [26]如前項[25]之半導體發光元件，其中於下底層上，進 而包含由III族氮化物半導體所構成之η型層。 根據本發明，提供半導體發光元件用模板基板，其特 徵爲至少具有：於表面被形成複數凸部的基板、於基板之 複數凸部被形成之面上被形成薄膜之III族氮化物半導體 所構成之緩衝層；顯示被形成凸部之基板的表面之未被形 成均一形狀之凸部所佔之面積的比率之不良面積率在10% ® 以下。 此處，於本發明適用之半導體發光元件用模板基板， 基板之複數凸部的形狀並沒有限定，但較佳者可以舉出藉 由在基板之（0001) C面上形成由不平行於C面的表面所 構成之複數凸部，而在基板上被形成由C面所構成的平面 與由凸部所構成的上面之構造。在此場合，前述凸部，係 基部寬幅〇.〇5μιη~5μιη、高度0·05μιη~5μιη，且高度爲基部 寬幅之1/4以上者，且鄰接之該凸部間之間隔爲該基部寬 φ 幅之0.5倍〜5倍者較佳。 又，在本說明書，凸部的形狀爲半球或圓錐、角錐等 的場合，前述基部寬幅亦有記載爲凸部的最大直徑的場合 〇 此外，於本發明適用之半導體發光元件用模板基板， 複數之前述凸部，最好具有基部寬幅〇·5μιη〜2μιη、高度 0.5 μιη~2 μηι >且與鄰接之凸部之間隔爲〇.5μιη~2μιη。 此外，基板以由藍寶石構成較佳。基板之最大直徑爲 50mm〜200mm，基板的厚度爲0.5mm〜2mm爲較佳。 -11 - 201031032 此外，於本發明適用之半導體發光元件用模板基板， 基板之複數凸部被形成之面上形成薄膜的緩衝層之III族 氮化物半導體，最好是藉由濺鍍法形成的氮化鋁膜或以其 他方法形成的氮化鎵系化合物半導體。 此外，於前述緩衝層上，最好是進而包含由氮化鎵所 構成的下底層之半導體發光元件用模板基板。此外，最好 是進而於緩衝層上，包含依序被形成由氮化鎵所構成的下 底層及η型氮化鎵系化合物半導體的層積構造之半導體發 光元件用模板基板。 進而，基板最好是使用平坦度GBIR在5μιη以下之藍 寶石板，藍寶石板之表面被形成複數凸部者。 其次，根據本發明，提供具有III族氮化物半導體層 的半導體發光元件用模板基板之製造方法，其特徵爲具有 :在平坦度GBIR爲5 μιη以下之藍寶石製的基板表面形成 複數凸部之基板加工步驟，及於基板之表面藉由濺鍍形成 由ΠΙ族氮化物半導體所構成之厚度0·02μιη〜Ο.ίμηι之緩 衝層之緩衝層形成步驟。 此處，於本發明適用之半導體發光元件用模板基板之 製造方法，最好是被形成於基板之凸部，具有最大直徑 0·5μιη〜2μηι、高度0.5μιη~2μιη之半球形狀。 進而，以顯示被形成複數凸部的基板的表面之未被均 一形成之凸部所佔之比率之不良面積率在1 〇%以下較佳， 以0.0 1 %~10%之範圍更佳，以0.0 1 %〜2%之範圍特佳。 此外，基板之部位平坦度SBIR爲1·5μιη以下較佳。 201031032 [發明之效果] 根據本發明，藉由使用不良面積率被調製在1 〇%以下 之半導體發光元件用模板基板，可以使所得的半導體發光 元件晶片之產率提高。此處，半導體發光元件用模板基板 之不良面積率，例如係以後述之坎德拉測定法來測定的。 此外，根據本發明的話，藉由使用平坦度（GBIR ) 1 Ομιη以下之基板，可以製造根據坎德拉測定法之不良面 φ 積率在1 〇%以下之半導體發光元件用模板基板。 【實施方式】 以下，針對本發明之實施型態進行詳細說明。又，本 發明並不以下列實施型態爲限定內容，在不逸脫其要旨的 範圍內可以進行種種變形而實施。此外，使用的圖面係供 說明本實施型態之用者，並不代表實際的大小。 圖1係說明本實施型態適用的半導體發光元件用模板 Φ 基板之一例之圖。如圖1所示，半導體發光元件用模板基 板IQ，具有：於表面被形成複數凸部102的基板101、及 於基板101之複數凸部102被形成之面上被形成薄膜之 ΠΙ族氮化物半導體所構成之緩衝層12;進而具有以掩埋 複數凸部102的方式被成膜於III族氮化物半導體所構成 的緩衝層12上之III族氮化物半導體層（下底層）13。 (基板101 ) 基板101係由與III族氮化物半導體不同之材料所構 -13- 201031032 成。作爲構成基板101支材料，例如可以舉出藍寶石、碳 化矽（silicon carbide，Sic)、矽、氧化鋅、氧化鎂、氧 化錳、氧化锆、氧化錳鋅鐵、氧化鎂鋁、硼化锆、氧化鎵 、氧化銦、氧化鋰鎵、氧化鋰鋁、氧化銨鎵、氧化鑭緦鋁 鉬、氧化緦鈦、氧化鈦、給、鎢、鉬等。其中，以藍寶石 、碳化矽（silicon carbide，SiC)較佳，又以藍寶石特佳[Technical Field] The present invention relates to a template substrate for a semiconductor light-emitting device, and the like, and more particularly to a template substrate for a semiconductor light-emitting device including a cerium nitride compound semiconductor and a method of manufacturing the same Wait. Further, the present invention relates to a method of manufacturing a semiconductor light-emitting device using a template substrate for a semiconductor light-emitting device, and a semiconductor light-emitting device. [Prior Art] In recent years, Group III nitride semiconductors have attracted attention as materials for semiconductor light-emitting elements. The group III nitride semiconductor is formed on a substrate such as sapphire, and is formed into a thin film by an organometallic chemical vapor deposition (MOCVD) method or an epitaxy method (MBE method). For example, Patent Document 1 discloses a method of reducing the light extraction efficiency of the inside of the semiconductor light-emitting device using such a group III nitride semiconductor. Patent Document 1 describes that the unevenness is formed on the surface of the first layer, and the unevenness is embedded in the second layer having a refractive index different from that of the first layer, and the irregular refractive index interface is formed thereon. By forming an element structure in which a semiconductor crystal layer containing a light-emitting layer is laminated, a light-emitting element having a novel structure in which light in a lateral direction of the light-emitting layer is emitted toward the outside is provided. Further, in Patent Document 2, it is also described that a plurality of convex portions composed of a surface of -5 - 201031032 which is not parallel to the surface of the substrate C are formed on the substrate, and a plane formed by the C surface is formed on the substrate. The processed substrate on the upper surface of the convex portion is then formed on the processed substrate to form a group III nitride semiconductor layer having a length of the group III nitride semiconductor layer and a portion III nitride semiconductor layer buried in the group III nitride semiconductor layer method. Generally, the substrate before processing, such as a sapphire plate, has a poor flatness of GBIR, and in particular, a substrate having a larger diameter is less likely to be a flat substrate. For example, the flatness GBIR of a 2 吋 (about 50 mm) sapphire plate is usually about 15 μm. [PRIOR ART DOCUMENT] [Patent Document 1] [Patent Document 1] Japanese Patent Laid-Open Publication No. 2002-2806 1 1 [Patent Document 2] International Publication Publication No. 2008/08 1 7 1 Booklet [Invention Content] [Invention [Problem to be Solved] However, when irregularities are formed on the surface of a sapphire substrate, it is difficult to grow a group III nitride semiconductor layer having excellent crystallinity. For example, in the case where a long-group I nitride semiconductor layer is formed by alignment on a substrate on which a plurality of convex portions are formed, it is necessary to form the size or shape of the plurality of convex portions to be uniform. That is, if the size or shape of the convex portion is different or the plurality of convex portions are biased on the substrate, the group III nitride semiconductor layer does not uniformly grow. Therefore, there is a case where the final yield of the semiconductor light-emitting device wafer obtained by the orientation-forming of the -6 - 201031032 lanthanide nitride semiconductor layer is greatly reduced, and the light-emitting characteristics as a semiconductor element are also lowered. Further, as a method of forming a plurality of convex portions on a substrate, a photolithography method is generally employed. However, according to the results of the review by the inventors of the present invention, it has been found that in the case where the difference in the thickness of the substrate is too large, the size or shape of the convex portion tends to be uneven. Φ An object of the present invention is to provide a template substrate for a semiconductor light-emitting device which can produce a semiconductor light-emitting device having excellent light extraction efficiency at a high yield, a method for producing the same, and a method for producing a semiconductor light-emitting device. [Means for Solving the Problem] That is, according to the present invention, the following [Π~[26] is provided. [1] A template substrate for a semiconductor light-emitting device, characterized in that it has at least a substrate on which a plurality of convex portions are formed on a surface, and a group III nitride semiconductor in which a plurality of thin portions of the substrate are formed into a thin film. The buffer layer is formed; the ratio of the area ratio of the area occupied by the convex portion of the surface of the substrate on which the convex portion is formed is not more than 10%. [2] The template substrate for a semiconductor light-emitting device according to [1], wherein the surface area ratio of the substrate does not include zero. [3] The template substrate for a semiconductor light-emitting device according to [1] or [2], wherein the defective area ratio is in the range of 0.01% to 10%. [4] The template substrate for a semiconductor light-emitting device according to any one of [1] to [3], wherein the plurality of convex portions of the substrate have a base width 〇·〇5μηι 5 μιη, a height of 201031032 0.05 μιη to 5 μιη, and The height is 1/4 or more of the width of the base portion and the interval between the adjacent convex portions is 5.5 times to 5 times the width of the base portion. [5] The template substrate for a semiconductor light-emitting device according to any one of [1] to [4] wherein the plurality of convex portions of the substrate have a maximum diameter of 55 μm to 2 μm, a height of 0.5 μηι 2 to 2 μηι, and a convexity adjacent thereto The interval between the parts is 〇.5μηι~2μιη. [6] The template substrate for a semiconductor light-emitting device according to any one of [1] to [5] wherein the substrate is made of sapphire. [7] The template substrate for a semiconductor light-emitting device of any one of the above [1] to [6] wherein the maximum diameter of the substrate is 50 mm to 200 mm, and the thickness of the substrate is 0 · 5 mm to 2 mm. [8] The template substrate for a semiconductor light-emitting device according to any one of [1] to [7] wherein the buffer layer bismuth nitride semiconductor is an aluminum nitride film formed by a sputtering method. [9] The template substrate for a semiconductor light-emitting device according to any one of [1] to [8], wherein the buffer layer further comprises a lower layer composed of a lanthanum nitride semiconductor. [1] The template substrate for a semiconductor light-emitting device according to the above [9], wherein the group III nitride semiconductor is gallium nitride (GaN). [1] The template substrate for a semiconductor light-emitting device of any one of [1] to [8], wherein the buffer layer further includes a lower layer and a lower layer of the n-type semiconductor layer composed of a group III nitride semiconductor. Product structure. [12] The template substrate for a semiconductor light-emitting device according to the above [1], wherein the group III nitride semiconductor is gallium nitride (GaN), and the n-type semiconductor layer comprises an n-type gallium nitride compound semiconductor. The sapphire plate for a semiconductor light-emitting device of any one of the above-mentioned [1] to [12], wherein the substrate 'is a sapphire plate having a flatness GBIR of less than or equal to ΙΟμηη, and a plurality of convex portions are formed on the surface of the sapphire plate. . [14] The template substrate for a semiconductor light-emitting device according to [13], wherein the flatness GBIR is in the range of 0·01 μm to 5 μm. [15] A method for producing a template substrate for a semiconductor light-emitting device, which is a method for fabricating a template substrate for a semiconductor light-emitting device having a bismuth nitride semiconductor layer, characterized in that the flatness GBIR is 1 μm or less A substrate processing step of forming a plurality of convex portions on the surface of the sapphire substrate, and a buffer layer forming step of forming a buffer layer having a thickness of 0.0 2 μm to 0.1 μm composed of a group III nitride semiconductor by sputtering on the surface of the substrate. [16] The method for producing a template substrate for a semiconductor light-emitting device according to the above [15], wherein the convex portion formed on the substrate has a hemispherical shape having a maximum diameter of 0.05 μm to 5 μm and a height of 0.05 μm to 5 μm. [17] The method for producing a template substrate for a semiconductor light-emitting device according to the above [15] or [16], wherein a ratio of a portion of the surface of the substrate on which the plurality of convex portions are formed is not uniformly formed is displayed. The area ratio is below 10%. The method for producing a template substrate for a semiconductor light-emitting device according to any one of the items [15] to [17] wherein the substrate has a flatness SBIR of 1.5 μm or less. [19] A method of manufacturing a semiconductor light-emitting device, characterized in that The method of forming the n-type layer, the light-emitting layer, and the Ρ-type layer composed of the group III nitride semiconductor in sequence with the template substrate for a semiconductor light-emitting device according to any one of the above items [1] to [14]. The method for producing a semiconductor light-emitting device according to the above [19], which comprises moving the template substrate for a semiconductor light-emitting device to epitaxial growth used in the production of the template substrate for the semiconductor light-emitting device (epitaxial) The step of forming the n-type furnace in the second orientation of the growth furnace and forming the n-type layer, the light-emitting layer, and the ruthenium layer formed of the group III nitride semiconductor in the template substrate for the semiconductor light-emitting device. [21] A semiconductor light-emitting device comprising a semiconductor light-emitting device having a group III nitride semiconductor layer, characterized in that: at least a substrate having a surface formed with a plurality of convex portions is formed on a surface on which a plurality of convex portions are formed a template substrate for forming a buffer layer formed of a film of a group III nitride semiconductor, and an n-type layer formed of a group III nitride semiconductor sequentially formed on a buffer layer of the template substrate, a light-emitting layer and a germanium layer; The surface area of the substrate of the template substrate shows a ratio of the area ratio of the area occupied by the convex portion which is not formed into a uniform shape at 1 〇 °. the following. [22] The semiconductor light-emitting device according to [21], wherein the surface area ratio of the substrate of the template substrate does not include zero. [23] The semiconductor light-emitting device according to [21] or [22] wherein the substrate of the template substrate is a sapphire plate having a flatness GBIR of ΙΟμηι or less. [24] The semiconductor light-emitting device according to [21] or [23], wherein the bismuth nitride semiconductor of the buffer layer of the template substrate is an aluminum nitride film formed by a sputtering method. [25] The semiconductor light-emitting device according to any one of [21] to [24] wherein the buffer layer of the template substrate further comprises a lower layer formed of a lanthanum nitride semiconductor. [26] The semiconductor light-emitting device according to [25], wherein on the lower substrate, an n-type layer composed of a group III nitride semiconductor is further included. According to the invention, there is provided a template substrate for a semiconductor light-emitting device, comprising: a substrate having a plurality of convex portions formed on a surface thereof; and a group III nitride semiconductor formed on a surface on which a plurality of convex portions of the substrate are formed; The buffer layer; the ratio of the area occupied by the surface of the surface of the substrate on which the convex portion is formed is not 10% ® or less. Here, in the template substrate for a semiconductor light-emitting device to which the present invention is applied, the shape of the plurality of convex portions of the substrate is not limited, but it is preferably formed by being non-parallel to C on the (0001) C plane of the substrate. The plurality of convex portions formed by the surface of the surface are formed on the substrate by a plane formed by the C surface and a top surface composed of the convex portions. In this case, the convex portion has a base width of 〇.5μιη to 5μιη, a height of 0·05μιη to 5μιη, and a height of 1/4 or more of the base width, and the interval between the adjacent convex portions is It is preferable that the base width is 0.5 times to 5 times the width φ. In the case where the shape of the convex portion is a hemisphere, a cone, a pyramid, or the like, the width of the base portion is also described as the maximum diameter of the convex portion, and the template substrate for a semiconductor light-emitting device to which the present invention is applied, Preferably, the plurality of convex portions have a base width 〇·5 μm to 2 μmη, a height of 0.5 μm to 2 μηι > and a distance from the adjacent convex portion of 〇.5 μιη to 2 μιη. Further, the substrate is preferably made of sapphire. The maximum diameter of the substrate is 50 mm to 200 mm, and the thickness of the substrate is preferably 0.5 mm to 2 mm. -11 - 201031032 Further, in the template substrate for a semiconductor light-emitting device to which the present invention is applied, a group III nitride semiconductor in which a buffer layer of a thin film is formed on a surface on which a plurality of convex portions of a substrate are formed is preferably formed by sputtering. An aluminum nitride film or a gallium nitride-based compound semiconductor formed by other methods. Further, it is preferable that the buffer layer further includes a template substrate for a semiconductor light-emitting device of a lower underlayer composed of gallium nitride. Further, it is preferable that the buffer layer further includes a template substrate for a semiconductor light-emitting device in which a lower layer of gallium nitride and a layer structure of an n-type gallium nitride-based compound semiconductor are sequentially formed. Further, it is preferable that the substrate is a sapphire plate having a flatness GBIR of 5 μm or less, and a plurality of convex portions are formed on the surface of the sapphire plate. According to the invention, there is provided a method for producing a template substrate for a semiconductor light-emitting device having a group III nitride semiconductor layer, comprising: a substrate having a plurality of convex portions formed on a surface of a sapphire substrate having a flatness GBIR of 5 μm or less And a buffer layer forming step of forming a buffer layer of a thickness of 0·02 μm to ί.ίμηι composed of a lanthanum nitride semiconductor by sputtering on the surface of the substrate. Here, the method for producing a template substrate for a semiconductor light-emitting device to which the present invention is applied is preferably formed in a convex portion of a substrate, and has a hemispherical shape having a maximum diameter of 0.5 μm to 2 μm and a height of 0.5 μm to 2 μm. Further, the ratio of the area ratio of the portion of the surface of the substrate on which the plurality of convex portions are formed is not uniformly formed is preferably 1% or less, more preferably 0.01% to 10%, and more preferably The range of 0.0 1 % to 2% is particularly good. Further, it is preferable that the portion flatness SBIR of the substrate is 1·5 μm or less. [Effect of the Invention] According to the present invention, the yield of the obtained semiconductor light-emitting device wafer can be improved by using a template substrate for a semiconductor light-emitting device having a defective area ratio of 1% or less. Here, the defective area ratio of the template substrate for a semiconductor light-emitting device is measured, for example, by a Candela measurement method to be described later. Further, according to the present invention, by using a substrate having a flatness (GBIR) of 1 Ομη or less, it is possible to manufacture a template substrate for a semiconductor light-emitting device having a defective surface φ product ratio of 1 〇% or less according to the Candela measurement method. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail. Further, the present invention is not limited to the following embodiments, and various modifications can be made without departing from the spirit and scope of the invention. Further, the drawings used are for the purpose of describing the embodiment, and do not represent actual size. Fig. 1 is a view showing an example of a template Φ substrate for a semiconductor light-emitting device to which the present embodiment is applied. As shown in FIG. 1, the template substrate IQ for a semiconductor light-emitting device has a substrate 101 on which a plurality of convex portions 102 are formed on the surface, and a cerium nitride formed on a surface on which the plurality of convex portions 102 of the substrate 101 are formed. The buffer layer 12 composed of a semiconductor; further comprising a group III nitride semiconductor layer (lower bottom layer) 13 formed on the buffer layer 12 composed of a group III nitride semiconductor so as to bury the plurality of convex portions 102. (Substrate 101) The substrate 101 is made of a material different from that of the group III nitride semiconductor -13-201031032. Examples of the material constituting the substrate 101 include sapphire, silicon carbide (Sic), bismuth, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, magnesium aluminum oxide, zirconium boride, and oxidation. Gallium, indium oxide, lithium gallium oxide, lithium aluminum oxide, gallium ammonium oxide, lanthanum aluminum molybdenum oxide, titanium ruthenium oxide, titanium oxide, donor, tungsten, molybdenum, and the like. Among them, sapphire, silicon carbide (SiC) is preferred, and sapphire is especially good.
(複數之凸部102 ) 圖2係說明被形成複數凸部1〇2的基板1〇1之一例之 圖。如圖2所示，被形成於基板1〇1之複數凸部102，以 具有特定之最大直徑幻（基部寬幅d,)與高度h、成爲均 一大小與均一形狀的方式被形成。在本實施型態，作爲凸 部102之形狀，例如可以舉出半球狀。但，於本發明，凸 部102的形狀並無特別限定。 在本實施型態，凸部 102之最大直徑 di以在 0.5μιη~2μιη之範圍特佳。最大直徑d!過小的話，使用基 板101形成III族氮化物半導體發光元件的場合，恐怕會 無法充分得到使光線散射反射的效果。最大直徑\過大 的話，掩埋凸部102使取向附生成長III族氮化物半導體 層（下底層）13的場合，會有產生不被平坦化的部分， 或是成長時間變長而生產性降低的傾向。 在本實施型態，凸部102之高度h以在〇.5μηι〜2μιη 之範圍特佳。高度h過小的話，使用基板101形成ΠΙ族 -14- 201031032 氮化物半導體發光元件的場合，恐怕會無法充分得到使光 線散射反射的效果。高度h過大的話，很難掩埋凸部102 使取向附生成長III族氮化物半導體層（下底層）13，會 有無法充分得到III族氮化物半導體層（下底層）1 3之表 面的平坦性之場合。 進而，複數之凸部102係在基板101之表面設特定的 間隔d2而被配置的。在本實施型態，複數凸部1 02之間 _ 隔d2以在0.5μιη~2μηι之範圍特佳。 間隔過度小的話，使取向附生成長時，亦有從C 面所構成的凹部的平面上之結晶成長變成很難促進，要使 凸部102以III族氮化物半導體層（下底層）13完全埋入 變得困難的場合，亦有無法充分得到III族氮化物半導體 層（下底層）13的表面的平坦性的場合。在此場合，形 成在掩埋凸部102的III族氮化物半導體層（下底層）13 上構成發光構造的半導體層的結晶的場合，此結晶成爲被 φ 形成很多小坑，會有導致被形成的III族氮化物半導體發 光元件的輸出或電氣特性等的惡化之傾向。 間隔d2過度大時，彳έ用基板101形成III族氮化物半 導體發光元件的場合，恐怕會在基板101與被形成於基板 101的III族氮化物半導體層之界面之光的散射反射的機 會減少，而無法充分提高光的取出效率。 如圖2所示，複數之凸部102，係在基板101之表面 1 〇 1 S上等間隔地被配置爲棋盤眼狀。 在本實施型態，藉由在基板1〇1上形成均一形狀的複 -15- 201031032 數凸部102，而使基板101與III族氮化物半導體層（下 底層）13之界面成爲凹凸形狀。因此，在具有這樣的構 造之半導體發光元件用模板基板％之上設LED構造之半 導體發光元件，藉由界面之光的散射反射，增大光的取出 效率。藉由被形成於藍寶石板表面的凹凸，利用結晶成長 於橫方向而減低結晶缺陷，可以使內部量子效率提高。 (緩衝層12) _ 緩衝層12，係藉由有機金屬化學氣相成長法（ MOCVD )而形成具有如後述之半導體發光元件的發光構 造（亦稱爲LED構造）的化合物半導體層之際，作爲發 揮緩衝功能的薄膜層而設於基板101上者。藉由設置緩衝 層12，成膜於緩衝層12上的III族氮化物半導體層（下 底層）13與進而被成膜於其上的具有LED構造的化合物 半導體層，成爲具有良好配向性及結晶性的結晶膜。 作爲構成緩衝層12的III族氮化物半導體，以含有 0 鋁較佳，以含有III族氮化物之氮化鋁特佳。作爲構成緩 衝層12的材料，只要是以一般式AlGalnN (氮化鋁鎵銦 )表示之III族氮化物半導體即可沒有特別限定。進而作 爲V族含有砷或磷亦可。緩衝層12，包含鋁的組成的場 合，以氮化鎵鋁（GaAIN )較佳，鋁之組成在50%以上者 較佳。 在本實施型態，緩衝層12的厚度爲0.0 2 μιη〜0.1 μιη。 緩衝層12的厚度過薄的話，可能會無法藉由緩衝層12充 -16- 201031032 分得到緩和基板101與III族氮化物半導體層（下底層） 13之晶格常數的差異之效果，緩衝層12的厚度過厚時， 成膜處理時間變長，會有生產性降低的傾向。 (半導體發光元件用模板基板Ιβ) 此處，於本實施型態，在前述基板101上，至少包含 緩衝層12 ’進而被成膜III族氮化物半導體層所構成之 φ 111族氮化物半導體層（下底層）13及η型半導體層14( 參照圖4)所選出之至少1層。這樣的半導體層積基板稱 爲半導體發光元件用模板基板。亦即，於本實施型態，半 導體發光元件用模板基板IQ，意味著不具有發光功能的半 導體層積層基板。以下，亦把半導體發光元件用模板基板 ，簡稱爲「模板基板」。這樣的模板基板，單獨被製造、 使用、販賣。進而，模板基板成爲製造半導體發光元件之 有效的原料基板。在此場合，使用特定之取向附生（ 〇 epitaxial )成長爐製造模板基板後，進而，於與製造該模 板基板時所使用之取向附生成長爐不同之第2取向附生成 長爐，於模板基板之上，依序形成至少由III族氮化.物半 導體所構成之發光層15及p型半導體層16，製造III族 氮化物半導體發光元件1。 (III族氮化物半導體層13(下底層）） 作爲使用於ΠΙ族氮化物半導體層（下底層）1 3支材 料，使用含鎵之ΠΙ族氮化物（氮化鎵系化合物半導體） -17- 201031032 ，特別是可是適切地使用氮化鋁鎵（AlGaN )或氮化鎵（(Multiple convex portion 102) Fig. 2 is a view showing an example of the substrate 1〇1 on which the plurality of convex portions 1〇2 are formed. As shown in Fig. 2, the plurality of convex portions 102 formed on the substrate 1〇1 are formed to have a specific maximum diameter illusion (base width d,) and height h, and have a uniform size and a uniform shape. In the present embodiment, the shape of the convex portion 102 is, for example, a hemispherical shape. However, in the present invention, the shape of the convex portion 102 is not particularly limited. In the present embodiment, the maximum diameter di of the convex portion 102 is particularly preferably in the range of 0.5 μm to 2 μm. When the maximum diameter d! is too small, when the group III is used to form the group III nitride semiconductor light-emitting device, the effect of scattering and reflecting light may not be sufficiently obtained. When the maximum diameter is too large, when the buried convex portion 102 is oriented to form a long group III nitride semiconductor layer (lower bottom layer) 13, a portion which is not flattened may be formed, or the growth time may be long and the productivity may be lowered. tendency. In the present embodiment, the height h of the convex portion 102 is particularly preferably in the range of 〇.5μηι to 2μηη. When the height h is too small, when the lanthanum-14-201031032 nitride semiconductor light-emitting device is formed using the substrate 101, the effect of scattering and reflecting light may not be sufficiently obtained. When the height h is too large, it is difficult to bury the convex portion 102 to form a long group III nitride semiconductor layer (lower underlayer) 13 and the flatness of the surface of the group III nitride semiconductor layer (lower layer) 13 may not be sufficiently obtained. The occasion. Further, the plurality of convex portions 102 are arranged at a predetermined interval d2 on the surface of the substrate 101. In the present embodiment, the interval d2 between the plurality of convex portions 102 is particularly preferably in the range of 0.5 μm to 2 μm. When the interval is too small, the growth of the crystal on the plane of the concave portion formed by the C surface becomes difficult to promote when the orientation is formed to be long, and the convex portion 102 is completely formed of the group III nitride semiconductor layer (lower bottom layer) 13 When the embedding becomes difficult, the flatness of the surface of the group III nitride semiconductor layer (lower layer) 13 may not be sufficiently obtained. In this case, when the crystal of the semiconductor layer of the light-emitting structure is formed on the group III nitride semiconductor layer (lower layer) 13 of the buried bump 102, the crystal is formed into a large number of pits by φ, which may result in formation. The tendency of the III-nitride semiconductor light-emitting device to deteriorate in output, electrical characteristics, and the like. When the interval d2 is excessively large, when the substrate 101 is formed into a group III nitride semiconductor light-emitting device, there is a fear that the chance of scattering reflection of light at the interface between the substrate 101 and the group III nitride semiconductor layer formed on the substrate 101 is reduced. , and the efficiency of light extraction cannot be sufficiently improved. As shown in Fig. 2, a plurality of convex portions 102 are arranged in a checkerboard shape at equal intervals on the surface 1 〇 1 S of the substrate 101. In the present embodiment, the interface of the substrate 101 and the group III nitride semiconductor layer (lower layer) 13 is formed into an uneven shape by forming a uniform -15-201031032 number convex portion 102 on the substrate 1?. Therefore, a semiconductor light-emitting element having an LED structure is provided on the template substrate % for a semiconductor light-emitting device having such a configuration, and light extraction efficiency is increased by scattering reflection of light at the interface. The internal quantum efficiency can be improved by the irregularities formed on the surface of the sapphire plate, and the crystal growth is increased in the lateral direction to reduce the crystal defects. (Buffer Layer 12) The buffer layer 12 is formed by a compound metal semiconductor layer having a light-emitting structure (also referred to as an LED structure) of a semiconductor light-emitting device to be described later by an organic metal chemical vapor deposition method (MOCVD). A film layer having a buffer function is provided on the substrate 101. By providing the buffer layer 12, the group III nitride semiconductor layer (lower underlayer) 13 formed on the buffer layer 12 and the compound semiconductor layer having the LED structure formed thereon are formed to have good alignment and crystallization. Sexual crystalline film. As the group III nitride semiconductor constituting the buffer layer 12, it is preferable to contain 0 aluminum, and it is preferable to contain aluminum nitride containing a group III nitride. The material constituting the buffer layer 12 is not particularly limited as long as it is a group III nitride semiconductor represented by a general formula of AlGalnN (aluminum gallium nitride). Further, as the group V, arsenic or phosphorus may be contained. The buffer layer 12, which includes the composition of aluminum, is preferably aluminum gallium nitride (GaAIN), and the composition of aluminum is preferably 50% or more. In the present embodiment, the buffer layer 12 has a thickness of 0.02 μm to 0.1 μm. If the thickness of the buffer layer 12 is too thin, the effect of relaxing the difference in lattice constant between the substrate 101 and the group III nitride semiconductor layer (lower layer) 13 by the buffer layer 12 may be reduced by the buffer layer 12, the buffer layer. When the thickness of 12 is too thick, the film formation treatment time becomes long, and productivity tends to be lowered. (Template substrate Ιβ for semiconductor light-emitting device) Here, in the present embodiment, a φ 111-nitride semiconductor layer including at least a buffer layer 12 ′ and a film-forming group III nitride semiconductor layer is formed on the substrate 101 . At least one layer selected from the lower layer 13 and the n-type semiconductor layer 14 (see FIG. 4). Such a semiconductor laminated substrate is referred to as a template substrate for a semiconductor light-emitting element. In other words, in the present embodiment, the template substrate IQ for a semiconductor light-emitting device means a semiconductor laminated substrate having no light-emitting function. Hereinafter, the template substrate for a semiconductor light-emitting device is also simply referred to as a "template substrate". Such a template substrate is separately manufactured, used, and sold. Further, the template substrate is an effective raw material substrate for manufacturing a semiconductor light-emitting device. In this case, a template substrate is produced by using a specific orientation epitaxial growth furnace, and further, a second orientation is generated in a template different from that used in the production of the template substrate. On the substrate, the light-emitting layer 15 and the p-type semiconductor layer 16 composed of at least a group III nitride semiconductor are sequentially formed to fabricate the group III nitride semiconductor light-emitting device 1. (Group III nitride semiconductor layer 13 (lower bottom layer)) As a material for use in a lanthanum nitride semiconductor layer (lower bottom layer), a gallium-containing lanthanide nitride (gallium nitride-based compound semiconductor) -17- 201031032, in particular, the appropriate use of aluminum gallium nitride (AlGaN) or gallium nitride (
GaN)。本實施型態適用的半導體發光元件用模板基板U 之III族氮化物半導體層（下底層）1 3，係如後所述作爲 具有半導體發光元件的LED構造之化合物半導體層的下 底層而發揮功能者。 在本實施型態，由ΠΙ族氮化物半導體層所構成之III 族氮化物半導體層（下底層）13的厚度爲0.1 μηι以上， 較佳者爲〇.5μιη以上進而更佳者爲Ιμιη以上。但是，III Q 族氮化物半導體層（下底層）13的厚度，最好爲15μπι以 下。III族氮化物半導體層（下底層）13的厚度過薄的話 ，形成於前述緩衝層12上的III族氮化物半導體層的下 底層之結晶性變差，會影響到模板基板之翹曲。ΙΠ族氮 化物半導體層（下底層）13的厚度過厚的話，模板基板 的翹曲有變大的傾向。 (不良面積率） 〇 於本實施型態適用的半導體發光元件用模板基板1〇， 基板101之複數凸部102被形成的表面101s，不良面積 率在10%以下，較佳者爲2%以下。此外，不良面積率以 不含零較佳，尤以0.01〜10%之範圍更佳。此處，不良面 積率，例如係以坎德拉測定法測定。 此處，所謂不良面積率，係被形成於基板101的表面 101s之複數凸部102之中，凸部102的高度h、基部寬幅 \、間隔與所期望的數値不同，未被形成爲所期望的 -18- 201031032 形狀的部分，亦即未被形成爲均一形狀的凸部1 〇2 部分）所佔面積的比例，定量地評價基板101 101S全體的凸部102的均一性的指數。但是，凸 由基板101上脫落者或者有傷痕者也被包含於不良 〇 在本實施型態，藉由使基板101之被形成複 102的表面101s之不良面積率在10%以下，可以 φ 用半導體發光元件用模板基板1〇調製的半導體發 晶片之產率提局。 不良面積率，例如使用光學式表面解析裝置（ KLA-Tencor公司製造：Candela)，作爲測定模式 長405nm的雷射之散射計（scatterometer)來測定 ，雷射波長爲 635nm或 405nm均可，較佳者j 40 5nm者。因爲波長越短，可以進行更高精度的表 〇 φ 次定步驟係把被形成複數凸部102的基板101 匣，裝設於解析裝置。基板101以搬送臂自動吸附 夾盤之旋轉台座，開始測定。基板1〇1以5 000rpm 旋轉，以15μιη之間距掃描表面101s之全面。不 部的感度隨凸部1 02的形狀而不同，所以有必要預 最佳的負側與正側之閾値。測定約3分鐘結束，不 部被映射，算出不良產生部的面積（不良面積）。 積以總面積來除，可以算出不良面積率。 於本實施型態，具有複數凸部102的基板1〇1 (不良 的表面 部102 面積率 數凸部 提筒使 光元件 例如， 採用波 。但是 爲波長 面解析 放入卡 於偏極 的轉速 良產生 先調整 良產生 不良面 ，以使 -19- 201031032 用 SEMI 規格(Semiconductor Equipment and Materials International，例如 Ml-03 02 )之平坦度（GBIR : Global Back Side Ideal Range)在ΙΟμπι以下之藍寶石板較佳， 平坦度（GBIR)爲5μηι以下者更佳。 此處，SEMI規格之平坦度（GBIR)，係被規定爲表 示藍寶石板的平坦度（Flatness )之指標之廣域（global )平坦度（所謂 TTV: Total Thickness Variation)之一 。平坦度（GBIR )係以藍寶石板爲背面基準，被定義爲 _ 表面高度的最大値與最小値之差（μηι )。平坦度（GBIR )之數値越小，藍寶石板的厚度越爲均一。 於本實施型態，使用前述平坦度（GBIR)爲ΙΟμπι以 下，較佳者爲5μιη以下之藍寶石板的話，如圖1所示， 可以於藍寶石板的表面形成具有均一形狀的複數凸部102 。接著，藉由被形成具有如此般均一形狀的複數凸部102 ，可以使基板1 〇 1的表面1 01 s之根據坎德拉測定法之不 良面積率爲1 0%以下。結果，使用這樣的半導體發光元件 @ 用模板基板1〇可以提高最終所得到的半導體發光元件晶 片的產率。 此處，在本實施型態，使用的藍寶石板的平坦度（ GBIR)以ΙΟμπι以下較隹，以5μιη以下更佳。此外，藍 寶石板之平坦度（GBIR)，以在Ο.ΟΙμηι〜ΙΟμιη的範圍較 佳，以在Ο.ΟΙμπι〜5μιη之範圍更佳，以在0.01μηι~4μπι之 範圍又更佳，以在0.1μιη~3μηι之範圍最佳。 此外，如圖2所示，形成複數凸部102的藍寶石板， -20- 201031032 把其表面分割爲寬幅12.5mmx高度16mm之部位（site) 的場合’部位平坦度（SBIR · Site Back Side Ideal Range )滿足1·5μιη以下之基準的比例（稱爲SBIR合格率（％ ))爲90%以上者較佳。GaN). The group III nitride semiconductor layer (lower layer) 13 of the template substrate U for a semiconductor light-emitting device to which the present embodiment is applied functions as a lower layer of a compound semiconductor layer having an LED structure of a semiconductor light-emitting element as will be described later. By. In the present embodiment, the thickness of the group III nitride semiconductor layer (lower layer) 13 composed of the lanthanum nitride semiconductor layer is 0.1 μη or more, preferably 〇5 μm or more, and more preferably Ιμηη or more. However, the thickness of the III Q-nitride semiconductor layer (lower underlayer) 13 is preferably 15 μm or less. When the thickness of the group III nitride semiconductor layer (lower layer) 13 is too small, the crystallinity of the lower underlayer of the group III nitride semiconductor layer formed on the buffer layer 12 is deteriorated, which may affect the warpage of the template substrate. When the thickness of the bismuth nitride semiconductor layer (lower layer) 13 is too thick, the warpage of the template substrate tends to become large. (Non-area area ratio) In the template substrate 1 for a semiconductor light-emitting device to which the present embodiment is applied, the surface 101s on which the plurality of convex portions 102 of the substrate 101 are formed has a defective area ratio of 10% or less, preferably 2% or less. . Further, the defective area ratio is preferably not contained in the range of from 0.01 to 10%, particularly preferably from 0.01 to 10%. Here, the defective area ratio is measured, for example, by the Candela method. Here, the defective area ratio is formed in the plurality of convex portions 102 formed on the surface 101s of the substrate 101. The height h of the convex portion 102, the width of the base portion, and the interval are different from the desired number, and are not formed as The ratio of the area occupied by the desired portion of the shape of -18 to 201031032, that is, the portion of the convex portion 1 〇 2 which is not formed into a uniform shape, is quantitatively evaluated as an index of the uniformity of the convex portion 102 of the entire substrate 101 101S. However, the protrusion or the flaw on the substrate 101 is also included in the present embodiment, and the surface area 101s of the substrate 101 formed by the substrate 101 has a defective area ratio of 10% or less. The yield of the semiconductor wafer prepared by the template substrate 1 for semiconductor light-emitting elements is improved. The defective area ratio is measured by, for example, an optical surface analysis apparatus (manufactured by KLA-Tencor Co., Ltd.: Candela) as a scatterometer measuring a laser having a length of 405 nm, and the laser wavelength is 635 nm or 405 nm, preferably. J 40 5nm. Since the wavelength is shorter, a higher precision can be performed. φ The next step is to mount the substrate 101 on which the plurality of convex portions 102 are formed, in the analysis device. The substrate 101 automatically adsorbs the rotating pedestal of the chuck by the transfer arm, and starts measurement. The substrate 1〇1 was rotated at 5 000 rpm, and the surface was scanned for a total of 101 s at a distance of 15 μm. The sensitivity of the non-part differs depending on the shape of the convex portion 102, so it is necessary to pre-optimize the threshold of the negative side and the positive side. The measurement was completed for about 3 minutes, and the area was not mapped, and the area (poor area) of the defective portion was calculated. The product is divided by the total area, and the bad area ratio can be calculated. In the present embodiment, the substrate 1〇1 having the plurality of convex portions 102 (the defective surface portion 102 has a large area ratio, and the convex portion lifts the optical element, for example, a wave is used. However, the wavelength surface is analyzed and the rotational speed is applied to the polarized pole. Good production first adjusts the bad side, so that -19-201031032 uses the SEMI specification (Semiconductor Equipment and Materials International, such as Ml-03 02) flatness (GBIR: Global Back Side Ideal Range) in the sapphire board below ΙΟμπι Preferably, the flatness (GBIR) is preferably 5 μηι or less. Here, the flatness (GBIR) of the SEMI specification is defined as the global flatness of the index indicating the flatness of the sapphire plate ( One of the so-called TTV: Total Thickness Variation. The flatness (GBIR) is based on the sapphire plate as the back reference and is defined as the difference between the maximum 値 and the minimum 表面 of the surface height (μηι ). The flatness (GBIR) Small, the thickness of the sapphire plate is more uniform. In the present embodiment, the sapphire plate having a flatness (GBIR) of ΙΟμπι or less, preferably 5 μm or less is used. As shown in Fig. 1, a plurality of convex portions 102 having a uniform shape may be formed on the surface of the sapphire plate. Then, by forming the plurality of convex portions 102 having such a uniform shape, the surface of the substrate 1 〇1 can be made 101. The poor area ratio of s according to the Candela measurement method is 10% or less. As a result, the yield of the semiconductor light-emitting device wafer finally obtained can be improved by using such a semiconductor light-emitting device @ with the template substrate 1 。. Type, the flatness (GBIR) of the sapphire plate used is ΙΟμπι or less, preferably 5 μm or less. In addition, the flatness of the sapphire plate (GBIR) is preferably in the range of Ο.ΟΙηηι~ΙΟμιη, in Preferably, the range of ΟΙμπι~5μιη is more preferably in the range of 0.01 μm to 4 μm, and is preferably in the range of 0.1 μm to 3 μm. Further, as shown in FIG. 2, the sapphire plate forming the plurality of convex portions 102 is -20- 201031032 When the surface is divided into a wide 12.5mm x 16mm height site, the site flatness (SBIR · Site Back Side Ideal Range) satisfies the base of 1·5μιη or less. A quasi-proportion (referred to as SBIR pass rate (%)) of 90% or more is preferred.
此處，部位平坦度（SBIR)係被規定作爲表示SEMI 規格之藍寶石板的平坦度之指標之一。部位平坦度（ SBIR )，被定義爲以藍寶石板作爲背面基準，於矯正藍 φ 寶石板的背面爲平面的狀態，虛擬把晶圓區分爲複數相同 形狀的部位而以一個部位之中心爲基準面時之表面高度的 最大値與最小値之差（μιη )。 (半導體發光元件用模板基板之製造方法） 其次，說明本實施型態適用的半導體發光元件用模板 基板之製造方法。 圖3係說明半導體發光元件用模板基板1〇的製造步 φ 驟之圖。如圖3(a)所示，如前所述首先準備平坦度（ GBIR)爲5μιη以下之藍寶石板10。藍寶石板10之最大 直徑爲50mm〜200mm，厚度通常爲0.5mm~2mm之範圍。 在本實施型態，使用具有最大直徑iOOmm與厚度0.9mm 之藍寶石板1〇。 其次，如圖3 ( b )所示，加工平坦度（GBIR )爲 5 μιη以下之藍寶石板10的表面l〇ls上被形成具有均一形 狀的複數凸部1〇2的基板101 (基板加工步驟）。於基板 加工步驟，進行形成規定基板1〇1上之凸部1〇2的平面配 -21 - 201031032 置的遮罩之圖案化步驟，即使用藉由圖案化步驟形成的遮 罩而蝕刻基板101形成凸部102之蝕刻步驟。圖案化步驟 ，一般可以採用光蝕刻法或翻印（reprint )法。 此處，於圖案化步驟，例如，於藍寶石板10的表面 101s存在小坑（pit)的話，於表面101s以旋轉塗布機塗 布光阻的場合，以此小坑爲基點產生放射狀的不均。這樣 的不均部分，一般因爲光阻的膜厚很薄，蝕刻後凸部1 02 的高度會改變，不良面積率有增加的傾向。此外，藍寶石 _ 板10的表面101S存在微粒（particle)等異物的場合， 同樣也有不良面積率增大的傾向。進而，藉由蝕刻步驟前 之收授操作等，於表面l〇ls之圖案產生傷痕的話，會成 爲不良面積率增大的原因。 蝕刻步驟，以使用乾蝕刻法或濕蝕刻法較佳。此處， 於乾蝕刻步驟，例如在真空室內不純物落下至藍寶石板 10的表面101s上時，該部分不被蝕刻，不被形成凸部 102。此部分也成爲不良面積率增加的原因。 @ 又，作爲形成凸部1 的方法，不以前述蝕刻法爲限 。例如於藍寶石板10把成爲凸部102的材料，藉由濺鍍 法、蒸鍍法、CVD法等層積而形成凸部102亦可。在此 場合，作爲成爲凸部102之材料，使用具有與藍寶石板 1 〇幾乎同等折射率的材料較佳，例如可以使用 A1203、Here, the position flatness (SBIR) is defined as one of the indexes indicating the flatness of the sapphire plate of the SEMI specification. The flatness of the part (SBIR) is defined as a sapphire plate as the back reference, and the back surface of the corrected blue φ gemstone plate is flat, and the wafer is virtually divided into a plurality of portions of the same shape and the center of one portion is used as a reference surface. The difference between the maximum 値 and the minimum 表面 of the surface height at the time (μιη). (Manufacturing Method of Template Substrate for Semiconductor Light Emitting Element) Next, a method of manufacturing the template substrate for a semiconductor light emitting element to which the present embodiment is applied will be described. Fig. 3 is a view showing a manufacturing step of a template substrate 1 for a semiconductor light-emitting device. As shown in Fig. 3(a), first, a sapphire plate 10 having a flatness (GBIR) of 5 μm or less is prepared as described above. The sapphire plate 10 has a maximum diameter of 50 mm to 200 mm and a thickness of usually 0.5 mm to 2 mm. In the present embodiment, a sapphire plate having a maximum diameter of iOOmm and a thickness of 0.9 mm is used. Next, as shown in FIG. 3(b), the substrate 101 having the uniform shape of the plurality of convex portions 1〇2 formed on the surface l〇ls of the sapphire plate 10 having a processing flatness (GBIR) of 5 μm or less (substrate processing step) ). In the substrate processing step, a masking step of forming a mask of the plane portion 21 - 201031032 on the predetermined substrate 1 〇 1 is performed, that is, the substrate 101 is etched using the mask formed by the patterning step. An etching step of forming the convex portion 102. The patterning step can generally be performed by photolithography or reprinting. Here, in the patterning step, for example, when there is a pit on the surface 101s of the sapphire plate 10, when the surface 101s is coated with a photoresist by a spin coater, radial unevenness is generated based on the small pit. . Such unevenness is generally because the film thickness of the photoresist is very thin, and the height of the convex portion 102 after etching changes, and the defective area ratio tends to increase. Further, when the surface 101S of the sapphire plate 10 has foreign matter such as particles, the defective area ratio tends to increase. Further, if a flaw is generated in the pattern of the surface l?ls by the receiving operation or the like before the etching step, the defective area ratio is increased. The etching step is preferably performed using a dry etching method or a wet etching method. Here, in the dry etching step, for example, when the impurities fall into the surface 101s of the sapphire panel 10 in the vacuum chamber, the portion is not etched, and the convex portion 102 is not formed. This part is also the reason for the increase in the bad area ratio. @ Further, as a method of forming the convex portion 1, it is not limited to the above etching method. For example, the sapphire plate 10 may be formed of a material of the convex portion 102 by lamination, a vapor deposition method, a CVD method or the like to form the convex portion 102. In this case, as the material to be the convex portion 102, a material having a refractive index almost equal to that of the sapphire plate 1 is preferably used, and for example, A1203,
SiN、Si〇2 等。 此外，把被塗布於前述基板1 〇 1上的光阻分割爲胞（ cell )狀而曝光的場合，鄰接的胞之間產生間隙的話會形 -22- 201031032 成未被曝光的部分，於形成在凸部102上的III族氮化物 半導體層產生階差。此處，於ΙΠ族氮化物半導體層，至 少包含由緩衝層12、III族氮化物半導體層所構成之下底 層13、η型半導體層14等。 同樣地，鄰接的胞重疊的話會出現雙重曝光的部分， 所以形成於凸部102上的III族氮化物半導體層會產生階 差。在此場合，於III族氮化物半導體層的表面，於對平 _ 坦定向（orientation flat )水平的方向或垂直的方向上， 會產生線狀的階差。 進而，胞內之基板101的表面l〇ls的平坦度（GBIR )過度大時，胞內不被均一地曝光，會有胞內光阻圖案形 狀變得不均一的傾向。因此，於其後之蝕刻步驟所得到的 凸部102，被形成爲所期望的形狀，及與其不同形狀者。 接著，於形成在凸部102上之III族氮化物半導體層之表 面，於具有這些之不同形狀的凸部102的界面產生階差， 〇 於產生的階差的部分有發生小坑等成長缺陷的傾向。 此外，形成於基板101的表面l〇ls全面的複數個凸 部1 02之中的不均一的形狀的部分，藉由坎德拉測定法， 評價不良面積率。不良面積率過度大時，於基板101的表 面l〇ls上藉由取向附生成長而形成的III族氮化物半導體 層上發生階差或小坑等缺陷，特別是有對ESD (靜電放電 )抵抗力弱等電氣特性劣化的傾向。 作爲減低不良面積率之方法，例如可以舉出如以下之 方法。首先，在曝光塗布於基板101上的光阻時，把基板 -23- 201031032 101載置於台座上，使用特定的減壓裝置，由被載置的基 板101的背面側來減壓吸附保持於台座上（真空保持）。 此時，基板101翹曲的場合，在台座上以使變成平坦的方 式矯正基板101。特別是基板101爲藍寶石製的場合，基 板101的直徑由2吋至4吋、由4吋至6吋越大口徑，基 板101之翹曲越容易變大。進而，基板101的厚度越大， 基板1 〇 1的剛性變得越大。因此，有必要採用可以把基板 1 0 1更強力地保持於台座上之偏極夾盤。此外，必須要剛 _ 性高的台座。又，基板101爲藍寶石製的場合，翹曲形狀 可以藉由基板製造時之熱處理、單面鏡面硏磨、雙面鏡面 硏磨、選擇板厚等來調整。 其次，前述之真空保持的場合，基板1 〇 1之背面側被 吸附保持於台座，所以特別是基板101的厚度差異很大的 話，表面側之平坦性會變差。因此，藉由蝕刻步驟形成的 各胞內的凸部102的形狀有變成不均一的傾向。此場合， 藉由減低以基板101的背面爲基準之厚度的差異，或者減 @ 低基板101的表面側之局部的凹凸’使所得到的凸部102 的形狀變成均一。 此外，曝光被塗布於基板101上的光阻時’藉由縮小 每1次之曝光面積，可以減低基板101的表面101s存在 的凹凸的影響。曝光方法可以舉出1次曝光晶圓全面的方 法，或將晶圓分割爲胞狀而進行的方法。分割晶圓的場合 ，分割面積越小，基板1〇1的表面101s的凹凸的影響就 越減低。但是分割面積過度小的話’會有生產性變差的傾 -24- 201031032 向。 接著，如圖3 ( c )所示，於基板丨〇丨的表面 ’形成由III族氮化物半導體所構成之緩衝層12 ( 形成步驟）。在本實施型態’緩衝層12，係藉由 形成III族氮化物半導體。藉由濺鍍形成緩衝層^ 合，真空室內之對氮原料與非活性氣體的流量之氮 比，氮原料最好佔5〇%〜100%，較佳者爲成爲75% φ 此外’藉由濺鍍法’形成具有柱狀結晶（多結 緩衝層12的場合，真空室內之對氮原料與非活性 流量之氮流量之比，氮原料最好佔1 %〜5 0 %，較佳 爲 25%。 其次，如圖3 ( d )所示，在本實施型態，緩 成步驟後，於被形成緩衝層12的基板101的上面 埋凸部102的方式，藉由MOCVD法成膜III族氮 導體層（下底層）13。又，在本實施型態，III族 φ 半導體層（下底層）13之最大厚度Η最好是凸部 高度h(參照圖2)的2倍以上。 ΙΠ族氮化物半導體層（下底層）13的最大厚j 薄的話，III族氮化物半導體層（下底層）13的表 的平坦性不夠充分，所以構成被層積於III族氮化 體層（下底層）13上的LED構造之結晶的結晶性 低的傾向》 作爲以MOCVD法層積III族氮化物半導體層 層）1 3的場合所使用的攜帶氣體，例如使用氫（ 101s 上 緩衝層 濺鍍而 2的場 流量之 〇 晶）的 氣體的 者爲成 衝層形 ，以掩 化物半 氮化物 1 02的 荽Η太 面 13a 物半導 會有降 (下底 H2 )、 -25- 201031032 氮（& ) ’·作爲III族原料之鎵（Ga )源使用三甲基鎵（ TMG )、三乙基鎵（TEG ) ，·作爲鋁源使用三甲基鋁（ TMA )、三乙基鋁（TEA ):作爲銦源使用三甲基銦（ TMI )、三乙基銦（TEI):作爲V族原料之氮源使用氨 (NH3 )、聯氨（N2H4 )等。此外，作爲摻雜劑，於n型 作爲矽原料可以使用甲矽烷（SiH4 )、乙矽烷（Si2H6 ) :作爲鍺原料可以使用鍺烷（germane，GeH4 )、四甲基鍺 ((CH3)4Ge)、四乙基鍺（（C2H5)4Ge)等有機鍺化合物 ;於P型作爲鎂原料可以利用環戊二烯鎂（Cp2Mg )。 於本實施型態，藉由於半導體發光元件用模板基板IQ 形成III族氮化物半導體層（下底層）1 3，如後所述，使 得被成膜於此上之III族氮化物半導體所構成的η型層、 發光層、Ρ型層所構成的發光構造（LED構造）之結晶的 結晶性變得良好。結果，可得內部量子效率優異，漏電流 很少的高輸出之半導體發光元件。 (III族氮化物半導體發光元件） 圖4係顯示III族氮化物半導體發光元件之一例之剖 面圖。如圖4所示，III族氮化物半導體發光元件1，係 具有於圖1所示的層積構造之半導體發光元件用模板基板 1〇之III族氮化物半導體層（下底層）13上被形成LED 構造20之構造。LED構造20，依序被層積η型半導體層 14、發光層15、ρ型半導體層16。進而’於ρ型半導體 層16上被層積透明正極17，於其上被形成正極焊墊18’ -26- 201031032 同時於被形成在ri型半導體層14的η型接觸層14a之露 出區域14d被層積負極19。 (LED 構造 20 ) 構成LED構造20之η型半導體層14，具有η型接觸 層14a及η型覆蓋（clad)層14b。發光層15，具有交互 層積障壁層15a及井層15b的構造。p型半導體層16，被 _ 層積P型覆蓋層16a及p型接觸層16b。 (η型半導體層14 ) 作爲η型半導體層14之η型接觸層14a，與下底層 之III族氮化物半導體層（下底層）13同樣使用氮化鎵系 化合物半導體。此外，構成III族氮化物半導體層（下底 層）13及η型接觸層14a的氮化鎵系化合物半導體以相 同組成較佳，這些之合計膜厚設定於〇.1μηι~20μιη之範圍 ^ ，較佳者爲 0.5μιη〜15μιη、進而更佳者爲設定在 1μιη~12μηι 之範圍。 η型覆蓋層14b，可以藉由AlGaN、GaN、GalnN等 來形成。此外作爲這些構造之異性（hetero )接合或複數 次層積之超格子構造亦可。採GalnN的場合，最好是比 發光層15之GalnN的能帶間隙更大較佳。η型覆蓋層 14b的膜厚，最好爲5nm~500nm，更佳者爲5nm〜100nm 之範圍。 -27- 201031032 (發光層15 ) 發光層15，係交互反覆層積由氮化鎵系化合物半導 體所構成之障壁層15a、及含有銦的氮化鎵系化合物半導 體所構成之井層15b，且於η型半導體層14側及p型半 導體層16側依被配置的順序層積障壁層15a而形成的。 在本實施型態，發光層15係交互反覆被層積6層障壁層 15a與5層井層15b，發光層15之最上層與最下層被配設 障壁層15a，各障壁層15a間被配設井層15b的構成。 ❹ 作爲障壁層15a，例如，可以適切使用含銦之氮化鎵 系化合物半導體所構成的井層1 5b能帶間隙能量更大的 AlcGai.eN ( 0S0 .3)等氮化鎵系化合物半導體。 此外，於井層15b，作爲含銦的氮化鎵系化合物半導 體，例如可以使用Gai.sInsN ( 0<s<0_4 )等氮化鎵銦。 (p型半導體層16 ) P型半導體層16’係由p型覆蓋層16a及p型接觸層 φ 16b所構成。作爲 p型覆蓋層〗6a，較佳者可以舉出 AldGai-dN C 0.4)。卩型覆蓋層16a的膜厚，最好爲 lnm~400nm，更佳者爲 5nm 〜l〇〇nm。 作爲p型接觸層16b，可以舉出至少包含AleGa, N (0Se<0.5)而成的氮化鎵系化合物半導體層。p型接觸 層1 6 b的膜厚’沒有特別限定，但以1 〇 n m〜5 〇 〇 n m較佳， 更佳者爲50nm〜200nm。 -28- 201031032 (透明電極1 7 ) 作爲構成透明正極17的材料，例如可以舉出IT〇( In2〇3-Sn〇2)、ΑΖΟ(ΖηΟ-Α12〇3)、ΙΖ〇(Ιη2〇3_Ζη〇) 、GZO (Zn0-Ga203)等從刖公知的材料。此外，透明正 極17的構造沒有特別限定’可以採用從前公知的構造。 透明正極17’亦可以覆蓋p型半導體層16上之幾乎全面 的方式形成，亦可形成爲格子狀或樹$ &。 (正極焊墊1 8 ) 作爲形成於透明正極17上的電極之正極焊墊18，例 如由從前公知之金、鋁 '鎳、銅等材料所構成。正極焊墊 18的構造沒有特別限定，可以採用從前公知的構造。 正極焊塾18的厚度爲i〇〇nrn〜i〇〇〇nrn，較佳者爲 300nm〜500nm之範圍內〇 ❹ （負極1 9 ) 如圖4所示，負極19，係於被成膜於基板u上的緩 衝層12及III族氮化物半導體層（下底層）13上進而成 膜的LED構造20(n型半導體層14、發光層15及p型半 導體層16)，以接於n型半導體層14之n型接觸層14a 的方式被形成。因此，形成負極19時，除去p型半導體 層16、發光層15以及η型半導體層14之一部分，形成η 型接觸層14a的露出區域14d，於此上形成負極19。 作爲負極19的材料，各種組成及構造之負極係已知 -29- 201031032 技術 通常 造20 之基 而得 件用 可以 氮化 者以 由從 與螢 用於 視型 明， ，可以無任何限制地使用這些週知的負極，可以用此 領域廣爲人知的慣用手段來設置。 於本實施型態III族氮化物半導體發光元件1， 是在半導體發光元件用模板基板上成膜出LED構 ，接著硏削/硏磨處理半導體發光元件用模板基板u 板101調整爲特定的厚度，其後，切斷爲適當大小， 具有特定厚度的基板11之半導體發光元件晶片。 如前所述，使用本實施型態適用的半導體發光元 模板基板1〇之III族氮化物半導體發光元件1 ’例如 作爲組合此與螢光體而成的燈管來使用。組合ΙΠ族 物半導體發光元件1與螢光體之燈管，可以藉由該業 週知的手段來做出該業者所週知的構成。此外，亦可 前技藝，藉由採用組合ΠΙ族氮化物半導體發光元件 光體而可以改變發光色之技術。作爲燈管之例，可以 一般用途之砲彈型、可攜帶電子產品的背光用途之側 、用於顯示器之頂視型等所有用途。 [實施例] 其次，顯示實施例及比較例進而更詳細說明本發 但本發明並不以這些實施例爲限。 (1 )平坦度（GBIR )、部位平坦度（SBIR)之測定 調製半導體發光元件用模板基板時使用的藍寶石板的 平坦度（GBIR )與部位平坦度（SBIR )係藉由以下的步 201031032 驟來測定的（單位Ρ01)。數値越小，監寶石板的厚度差 異越小。 此處，在本實施型態藍寶石板之平坦度（GBIR)及 部位平坦度（SBIR )之測定’係藉由雷射光斜向入射干 涉計（（股）Nitech (音譯）公司製造：平坦度測量儀（ flatness-tester) FT-17)來評價的。平坦度（GBIR)及部 位平坦度（SB IR )之側定，係將直徑4吋（100mm )'厚 φ 度0.9mm之藍寶石板固定於平坦度測量儀的陶瓷製真空 吸附夾具，由垂直往觀測者方向傾斜8度的狀態下進行測 定。測定係以排除藍寶石板的外週1mm (內部（inside ) 値1 m m )之範圍來進行的。 (2)不良面積率之測定 被形成於藍寶石製的基板表面的複數凸部的不良面積 率，係依照以下步驟進行測定的（單位％ )。不良面積率 φ 越小，複數之凸部的形狀越均一。 此處，在本實施型態，以光學式表面解析裝置（ KLA-Tencor公司製造·· CS20)，測定凹凸加工後之藍寶 石板表面的不良面積。直徑4吋（100mm)、厚度〇.9mm 之藍寶石板表面的測定約3分鐘結束，凸部不良部被映射 ’算出不良面積。此時’將不良面積以測定範圍之總面積 來除，得到不良面積率。 不良面積率=不良面積（坎德拉測定値）/總面積 -31 - 201031032 (3 ) SBIR合格率 調製半導體發光元件用模板基板時使用的藍寶石板的 SB IR合格率係藉由以下的基準來判定。 所謂SBIR合格率係以前述公知的SBIR測定算出來 的。部位（site)的大小（胞尺寸）爲寬幅12.5mmx高度 16mm的場合，可以覆蓋直徑4吋（100mm)全面的部位 數爲44個。此時，各部位內的平坦度的合格判定爲 1 .5pm以下。例如，合格的部位數爲22個的場合，SBIR φ 合格率爲5 0 %。 (4 ) ESD產率 使用調製的半導體發光元件用模板基板製造之III族 氮化物半導體發光元件之ESD產率係藉由以下基準來判 定。 所謂 ESD ( electro-static discharge ;靜電放電）係 指靜電破壞試驗，供評價直到將前述III族氮化物半導體 ❿ 發光元件實裝於電子機器爲止之收授過程中，III族氮化 物半導體發光元件對於受到的靜電放電之耐受性之用的信 賴性試驗。 靜電破壞試驗一般有HBM法（Human Body Model) 與MM法（Machine Model)。在本實施型態，作爲試驗 裝置使用ESD探針，依據HBM法，把被形成於直徑4吋 (100mm)之前述半導體發光元件用模板基板上的ΠΙ族 氮化物半導體發光元件，抽樣實施面內400個靜電破壞試 -32- 201031032 驗。此時，在靜電破壞試驗把稱爲探針的針抵壓於前述 III族氮化物半導體發光元件之正極焊墊與負極，使高電 壓反方向施加數次，施加20V時之電流値爲10//A以上 的場合判斷爲靜電破壞。此時，不產生破壞的樣本數除以 總樣本數稱爲ESD產率。 (5)晶片綜合產率 φ 使用調製的半導體發光元件用模板基板製造之III族 氮化物半導體發光元件之晶片綜合產率係藉由以下基準來 判定。晶片綜合產率係指電氣特性及ESD試驗達到合格 基準的晶片數除以總樣本數之比例。 (實施例1 ~6 '、比較例） 依照以下的步驟，調製最大直徑l〇〇mm、厚度0.9mm 之由（000 1 ) C面所構成的藍寶石板的表面，形成表1所 φ 示之具有直徑 Φ 與高度之半球狀的複數凸部的半導體發 光元件用模板基板，使用此來製造III族氮化物半導體發 光元件。SiN, Si〇2, etc. Further, when the photoresist coated on the substrate 1 〇1 is divided into cells and exposed, a gap is formed between adjacent cells, and -22-201031032 is formed as an unexposed portion. The group III nitride semiconductor layer on the convex portion 102 generates a step. Here, the bismuth nitride semiconductor layer contains at least the underlayer 13, the n-type semiconductor layer 14, and the like which are composed of the buffer layer 12 and the group III nitride semiconductor layer. Similarly, if the adjacent cells overlap, a double-exposed portion appears, so that the group III nitride semiconductor layer formed on the convex portion 102 is stepped. In this case, a linear step is generated on the surface of the group III nitride semiconductor layer in a direction perpendicular to the level of the orientation flat or in a direction perpendicular thereto. Further, when the flatness (GBIR) of the surface 10?s of the intracellular substrate 101 is excessively large, the intracellular cells are not uniformly exposed, and the shape of the intracellular resist pattern tends to be uneven. Therefore, the convex portion 102 obtained in the subsequent etching step is formed into a desired shape and a shape different therefrom. Then, on the surface of the group III nitride semiconductor layer formed on the convex portion 102, a step is generated at the interface of the convex portion 102 having these different shapes, and a growth defect such as a small pit occurs in a portion where the step is generated. Propensity. Further, a portion of the plurality of convex portions 102 which are formed on the surface of the substrate 101, which is a whole of the plurality of convex portions 102, is evaluated for the defective area ratio by the Candela measurement method. When the defective area ratio is excessively large, a defect such as a step or a small pit occurs on the group III nitride semiconductor layer formed by the formation of the alignment on the surface 10 ls of the substrate 101, in particular, there is a pair of ESD (electrostatic discharge). A tendency to deteriorate electrical characteristics such as weak resistance. As a method of reducing the defective area ratio, for example, the following methods can be mentioned. First, when exposing the photoresist applied to the substrate 101, the substrate -23-201031032 101 is placed on a pedestal, and a specific pressure reducing device is used to decompress and hold the substrate on the back side of the substrate 101 to be placed thereon. On the pedestal (vacuum hold). At this time, when the substrate 101 is warped, the substrate 101 is corrected in a flat manner on the pedestal. In particular, when the substrate 101 is made of sapphire, the diameter of the substrate 101 is from 2 吋 to 4 吋, and the diameter of the substrate 101 is larger, and the warpage of the substrate 101 is more likely to become larger. Further, the greater the thickness of the substrate 101, the greater the rigidity of the substrate 1 〇 1 becomes. Therefore, it is necessary to use a polarizing chuck that can hold the substrate 110 strongly on the pedestal. In addition, it is necessary to have a pedestal with a high degree of sufficiency. Further, when the substrate 101 is made of sapphire, the warped shape can be adjusted by heat treatment at the time of substrate production, single-sided mirror honing, double-sided mirror honing, thickness selection, and the like. When the vacuum holding is performed, the back side of the substrate 1 〇 1 is adsorbed and held by the pedestal. Therefore, particularly when the thickness of the substrate 101 is large, the flatness on the surface side is deteriorated. Therefore, the shape of the convex portion 102 in each cell formed by the etching step tends to be non-uniform. In this case, the shape of the obtained convex portion 102 is made uniform by reducing the difference in thickness based on the back surface of the substrate 101 or by reducing the local unevenness on the surface side of the substrate 101. Further, when the exposure is applied to the photoresist on the substrate 101, the effect of the unevenness of the surface 101s of the substrate 101 can be reduced by reducing the exposure area per one time. The exposure method may be a method in which the wafer is exposed one time, or a method in which the wafer is divided into cells. In the case of dividing the wafer, the smaller the divided area, the less the influence of the unevenness on the surface 101s of the substrate 1〇1 is. However, if the area of the division is too small, there will be a decline in productivity -24-201031032. Next, as shown in Fig. 3 (c), a buffer layer 12 composed of a group III nitride semiconductor is formed on the surface ' of the substrate ( (forming step). In the present embodiment, the buffer layer 12 is formed by forming a group III nitride semiconductor. By forming a buffer layer by sputtering, the ratio of nitrogen to the flow rate of the nitrogen raw material and the inert gas in the vacuum chamber is preferably from 5% to 100%, preferably 75% φ. The sputtering method 'forms a columnar crystal (in the case of the multi-junction buffer layer 12, the ratio of the nitrogen flow rate to the nitrogen flow rate in the vacuum chamber to the inert flow rate, and the nitrogen raw material preferably accounts for 1% to 50%, preferably 25 Next, as shown in FIG. 3(d), in the present embodiment, after the grading step, the convex portion 102 is buried on the upper surface of the substrate 101 on which the buffer layer 12 is formed, and the III group is formed by MOCVD. The nitrogen conductor layer (lower bottom layer) 13. Further, in the present embodiment, the maximum thickness Η of the group III φ semiconductor layer (lower bottom layer) 13 is preferably twice or more the height h of the convex portion (see Fig. 2). When the maximum thickness j of the nitride semiconductor layer (lower layer) 13 is thin, the flatness of the surface of the group III nitride semiconductor layer (lower layer) 13 is insufficient, so that the composition is laminated on the group III nitride layer (lower layer). The tendency of the crystal structure of the LED structure on 13 to have low crystallinity" as a layer III nitride half by MOCVD The carrier gas used in the case of the bulk layer 1 3 is, for example, a gas which is formed by using hydrogen (a buffer of a buffer layer of 101 s and a field flow of 2) to form a punched layer to mask a semi-nitride. The 半太面13a material semi-conductor will drop (lower bottom H2), -25- 201031032 nitrogen (&) '· as a group III raw material gallium (Ga) source using trimethylgallium (TMG), three B Gallium (TEG), as a source of aluminum, trimethylaluminum (TMA), triethylaluminum (TEA): as a source of indium, trimethylindium (TMI), triethylindium (TEI): as a group V A nitrogen source of the raw material is ammonia (NH3), hydrazine (N2H4) or the like. Further, as the dopant, methane (SiH4) or ethane oxide (Si2H6) can be used as the ruthenium raw material: ruthenium (germane, GeH4) or tetramethyl ruthenium ((CH3)4Ge) can be used as the ruthenium raw material. An organic ruthenium compound such as tetraethyl ruthenium ((C2H5)4Ge); and a p-type magnesium raw material, a cyclopentadienyl magnesium (Cp2Mg) can be used. In the present embodiment, a group III nitride semiconductor layer (lower underlayer) 13 is formed by a template substrate IQ for a semiconductor light-emitting device, and a group III nitride semiconductor formed thereon is formed as will be described later. The crystallinity of the crystal of the light-emitting structure (LED structure) composed of the n-type layer, the light-emitting layer, and the Ρ-type layer is good. As a result, a high-output semiconductor light-emitting element having excellent internal quantum efficiency and little leakage current can be obtained. (Group III nitride semiconductor light-emitting device) Fig. 4 is a cross-sectional view showing an example of a group III nitride semiconductor light-emitting device. As shown in FIG. 4, the group III nitride semiconductor light-emitting device 1 is formed on a group III nitride semiconductor layer (lower bottom layer) 13 of a template substrate 1 of a semiconductor light-emitting device having a laminated structure shown in FIG. The construction of the LED construction 20. In the LED structure 20, the n-type semiconductor layer 14, the light-emitting layer 15, and the p-type semiconductor layer 16 are sequentially laminated. Further, a transparent positive electrode 17 is laminated on the p-type semiconductor layer 16, and a positive electrode pad 18'-26-201031032 is formed thereon while being exposed to the exposed region 14d of the n-type contact layer 14a of the ri-type semiconductor layer 14. The negative electrode 19 is laminated. (LED structure 20) The n-type semiconductor layer 14 constituting the LED structure 20 has an n-type contact layer 14a and an n-type clad layer 14b. The light-emitting layer 15 has a configuration in which the barrier layer 15a and the well layer 15b are alternately laminated. The p-type semiconductor layer 16 is laminated with a p-type cladding layer 16a and a p-type contact layer 16b. (n-type semiconductor layer 14) As the n-type contact layer 14a of the n-type semiconductor layer 14, a gallium nitride-based compound semiconductor is used similarly to the group III nitride semiconductor layer (lower layer) 13 of the lower underlayer. Further, the gallium nitride-based compound semiconductor constituting the group III nitride semiconductor layer (lower underlayer) 13 and the n-type contact layer 14a is preferably the same composition, and the total film thickness is set in the range of 〇.1μηι to 20μιη, The preferred one is from 0.5 μm to 15 μm, and more preferably from 1 μm to 12 μm. The n-type cladding layer 14b can be formed by AlGaN, GaN, GalnN or the like. Further, it is also possible to use a hyperlattice structure in which a hetero bond or a plurality of layers of these structures are laminated. In the case of GalnN, it is preferable that the energy band gap of GalnN of the light-emitting layer 15 is larger. The film thickness of the n-type cladding layer 14b is preferably 5 nm to 500 nm, and more preferably 5 nm to 100 nm. -27-201031032 (Light-emitting layer 15) The light-emitting layer 15 is a well layer 15b formed by a barrier layer 15a composed of a gallium nitride-based compound semiconductor and a gallium nitride-based compound semiconductor containing indium. The barrier layer 15a is formed by laminating the barrier layer 15a in the order of the n-type semiconductor layer 14 side and the p-type semiconductor layer 16 side. In the present embodiment, the light-emitting layer 15 is alternately laminated with six barrier layers 15a and five well layers 15b. The uppermost layer and the lowermost layer of the light-emitting layer 15 are provided with barrier layers 15a, and the barrier layers 15a are arranged. The configuration of the well layer 15b is provided. ❹ As the barrier layer 15a, for example, a gallium nitride-based compound semiconductor such as AlcGai.eN (0S0.3) which has a higher gap energy than the well layer 15b made of a gallium nitride-based compound semiconductor containing indium can be used. Further, in the well layer 15b, as the indium-containing gallium nitride-based compound semiconductor, for example, gallium nitride indium such as Gai.sInsN (0<s<0>0_4) can be used. (p-type semiconductor layer 16) The p-type semiconductor layer 16' is composed of a p-type cladding layer 16a and a p-type contact layer φ 16b. As the p-type cladding layer 6a, AldGai-dN C 0.4) is preferable. The film thickness of the ruthenium type cap layer 16a is preferably from 1 nm to 400 nm, more preferably from 5 nm to 10 nm. The p-type contact layer 16b may be a gallium nitride-based compound semiconductor layer containing at least AleGa, N (0Se < 0.5). The film thickness ' of the p-type contact layer 166b is not particularly limited, but is preferably 1 〇 n m 5 5 〇 〇 n m , more preferably 50 nm to 200 nm. -28- 201031032 (Transparent Electrode 1 7 ) Examples of the material constituting the transparent positive electrode 17 include IT〇(In2〇3-Sn〇2), ΑΖΟ(ΖηΟ-Α12〇3), and ΙΖ〇(Ιη2〇3_Ζη〇). ), GZO (Zn0-Ga203) and other materials known from 刖. Further, the configuration of the transparent positive electrode 17 is not particularly limited. A configuration known from the prior art can be employed. The transparent positive electrode 17' may be formed to cover the p-type semiconductor layer 16 in an almost comprehensive manner, or may be formed in a lattice shape or a tree & (Positive Electrode Pad 18) The positive electrode pad 18 which is an electrode formed on the transparent positive electrode 17 is made of, for example, a material such as gold or aluminum 'nickel or copper which is known in the prior art. The structure of the positive electrode pad 18 is not particularly limited, and a structure known in the prior art can be employed. The thickness of the positive electrode pad 18 is i〇〇nrn~i〇〇〇nrn, preferably in the range of 300 nm to 500 nm (negative electrode 19). As shown in Fig. 4, the negative electrode 19 is formed into a film. The LED structure 20 (the n-type semiconductor layer 14, the light-emitting layer 15, and the p-type semiconductor layer 16) which is further formed on the buffer layer 12 and the group III nitride semiconductor layer (lower underlayer) 13 on the substrate u to be connected to the n-type The manner of the n-type contact layer 14a of the semiconductor layer 14 is formed. Therefore, when the negative electrode 19 is formed, one portion of the p-type semiconductor layer 16, the light-emitting layer 15, and the n-type semiconductor layer 14 is removed, and the exposed region 14d of the n-type contact layer 14a is formed, and the negative electrode 19 is formed thereon. As the material of the negative electrode 19, the negative electrode of various compositions and configurations is known to be -29-201031032, and the technique is generally used for nitriding, and the member can be nitrided for use as a visual type, and can be used without any limitation. The use of these well-known negative electrodes can be set by conventional means well known in the art. In the present invention, the group III nitride semiconductor light-emitting device 1 is formed by forming an LED structure on a template substrate for a semiconductor light-emitting device, and then dicing/honing the template substrate for the semiconductor light-emitting device u board 101 to a specific thickness. Thereafter, the semiconductor light-emitting element wafer of the substrate 11 having a specific thickness is cut into an appropriate size. As described above, the group III nitride semiconductor light-emitting device 1' of the semiconductor light-emitting element template substrate 1 to which the present embodiment is applied is used, for example, as a lamp tube in which the phosphor is combined. The combination of the steroid semiconductor light-emitting device 1 and the phosphor tube can be made by a well-known means in the art. Further, it is also possible to change the technique of illuminating color by using a combination of a bismuth nitride semiconductor light-emitting device light body. As an example of the lamp tube, it can be used for general purpose cannonball type, side of backlight for portable electronic products, and top view type for display. [Examples] Next, the examples and comparative examples will be described in further detail, but the present invention is not limited to the examples. (1) Measurement of flatness (GBIR) and site flatness (SBIR) The flatness (GBIR) and the positional flatness (SBIR) of the sapphire plate used for modulating the template substrate for a semiconductor light-emitting device are as follows: 201031032 To determine (unit Ρ 01). The smaller the number, the smaller the difference in thickness of the gemstone plate. Here, the flatness (GBIR) and the flatness (SBIR) of the sapphire plate of this embodiment are measured by a laser oblique oblique incident interferometer (manufactured by Nitech): flatness measurement Instrument (flatness-tester) FT-17) to evaluate. The flatness (GBIR) and the flatness of the part (SB IR ) are fixed to the ceramic vacuum suction fixture of the flatness measuring instrument by fixing the sapphire plate with a diameter of 4 吋 (100 mm ) and a thickness of 0.9 mm. The measurement was performed with the observer tilted by 8 degrees. The measurement was carried out by excluding the range of 1 mm (inside 値1 m m ) of the outer periphery of the sapphire plate. (2) Measurement of defective area ratio The defective area ratio of the plurality of convex portions formed on the surface of the substrate made of sapphire was measured in accordance with the following procedure (unit: %). The smaller the area ratio φ is, the more uniform the shape of the plurality of convex portions is. Here, in the present embodiment, the surface area of the sapphire slate after the uneven processing was measured by an optical surface analysis device (manufactured by KLA-Tencor Co., Ltd., CS20). The measurement of the surface of the sapphire plate having a diameter of 4 吋 (100 mm) and a thickness of 99 mm was completed in about 3 minutes, and the defective portion of the convex portion was mapped to calculate a defective area. At this time, the defective area was divided by the total area of the measurement range to obtain a defective area ratio. Non-small area ratio = unsatisfactory area (candela measurement) / total area -31 - 201031032 (3) SBIR yield The SB IR yield of the sapphire plate used for modulating the template substrate for a semiconductor light-emitting device is determined by the following criteria. The SBIR pass rate is calculated by the above-described known SBIR measurement. When the size of the site (cell size) is 12.5 mm wide and 16 mm in height, the number of parts covering the entire diameter of 4 吋 (100 mm) is 44. At this time, the pass level of the flatness in each part was judged to be 1.5 pm or less. For example, when the number of qualified parts is 22, the SBIR φ pass rate is 50%. (4) ESD yield The ESD yield of the group III nitride semiconductor light-emitting device produced using the template substrate for a semiconductor light-emitting device to be prepared was determined by the following criteria. ESD (electro-static discharge) refers to an electrostatic breakdown test for evaluation until the III-nitride semiconductor 发光 light-emitting device is mounted on an electronic device, and the group III nitride semiconductor light-emitting device is A reliability test for the resistance to electrostatic discharge. Electrostatic damage tests generally include the HBM method (Human Body Model) and the MM method (Machine Model). In the present embodiment, an ESD probe is used as a test device, and a bismuth nitride semiconductor light-emitting device formed on a template substrate for a semiconductor light-emitting device having a diameter of 4 Å (100 mm) is sampled in a plane by the HBM method. 400 electrostatic breakdown tests - 32- 201031032. At this time, in the electrostatic breakdown test, a needle called a probe was pressed against the positive electrode pad and the negative electrode of the group III nitride semiconductor light-emitting device, and the high voltage was applied in the opposite direction several times, and the current 値 when applied at 20 V was 10/. In the case of /A or more, it is judged to be electrostatic breakdown. At this time, the number of samples that do not cause damage divided by the total number of samples is called ESD yield. (5) Integrated wafer yield φ The wafer integrated yield of the group III nitride semiconductor light-emitting device fabricated using the template substrate for a semiconductor light-emitting device to be prepared was determined by the following criteria. The integrated wafer yield is the ratio of the number of wafers whose electrical characteristics and ESD tests have passed the acceptance criteria divided by the total number of samples. (Examples 1 to 6', Comparative Example) The surface of a sapphire plate composed of a (000 1 ) C-plane having a maximum diameter of 10 mm and a thickness of 0.9 mm was prepared in accordance with the following procedure, and was formed as shown in Table 1. A template substrate for a semiconductor light-emitting device having a plurality of hemispherical convex portions having a diameter Φ and a height, and a III-nitride semiconductor light-emitting device is produced using the template substrate.
表1所示之平坦度（GBIR) 、SBIR合格率之直徑4 吋（100mm)、板厚90 0μιη之藍寶石板10之（〇〇〇1) C 面上，藉由以下所示之步驟形成直徑（最大直徑或基部寬 幅）、高度不同的凸部，形成基板101。 此時，基板加工係以公知之光蝕刻法形成遮罩，以乾 蝕刻法蝕刻藍寶石板1 0而形成凸部。又，作爲曝光法， -33- 201031032 使用利用紫外線之步進機（stepper)曝光法。 此外，於乾鈾刻使用BC13與Cl2之混合氣體。其後 ，爲了評價凸部加工之均一性，使用光學式表面解析裝置 (Candela)算出不良面積率。 其次，於此基板上，藉由濺鍍法形成如圖1所示 之膜厚3 Onm之氮化鋁層所構成之緩衝層12後，藉由有 機金屬化學氣相成長法（MOCVD )，在依序層積未摻雜 之氮化鎵層所構成的厚度4.5μπι之III族氮化物半導體層 ❹ (下底層）13、摻雜矽（濃度lxl〇19/cm3)之氮化鎵所構 成的厚度3μπι之η型接觸層14a爲止的狀態下由MOCVD 裝置取出而作爲模板基板。 其後，於前述模板基板上，藉由MOCVD法，依序層 積摻雜矽（濃度lxl〇18/cm3 )之厚度約2nm的InQ1GaQ.9N 層與厚度約2nm之氮化鎵層交互層積20次之超格子構造 之η型覆蓋（clad )層14b、由氮化鎵所構成的厚度 6_5nm之障壁層15a與N所構成的厚度3.0nm @ 之井層15b交互層積6次之後，最後設置障壁層15a之多 重量子井構造之發光層 15、厚度 4nm之未摻雜 Al〇.Q7GaQ 93 N與摻雜鎂（濃度4xl019/Scm3 )之氮化鎵所 構成的厚度3 nm之層交互層積3次之p型覆蓋層16a'及 摻雜鎂（濃度lxl〇2()/cm3)氮化鎵所構成厚度0.15μιη之 Ρ型接觸層16b而成爲化合物半導體晶圓。此時，LED構 造20之III族氮化物半導體層之總膜厚爲8μπι。 接著，使用如此進行而得到之成爲LED構造的各層 -34- 201031032 之被形成的基板，藉以下所示之步驟，製作ΠΙ族氮化物 半導體發光元件。首先，藉由公知之光蝕刻技術，於成爲 LED構造的各層之被形成的基板之ρ型接觸層上，形成具 有由IZO所構成之透明正極、與於此透明正極上依序層積 鈦、鉑及金的構造之正極焊墊。 接著，對被形成正極焊墊（bonding pad)的基板進 行乾蝕刻，使形成負極的部分之η型半導體層露出，於露 φ 出之η型半導體層上形成具有依序層積鈦、鉑及金的構造 之負極。 接著，以硏削及硏磨薄板化被形成正極焊墊及負極之 基板的背面，成爲鏡狀之面。接著，將此基板分割爲 3 50 μιη正方之正方形晶片狀，成爲半導體發光元件晶片。 結果顯不於表1。 [表1] 凸部的形 狀直徑X 高度μιη 平坦度 (GBIR) μιη 部位平坦 度(SBIR) μιη SBIR 合格率 % 坎德拉不 良面積率 % ESD 產率 % 晶片綜 合產率 % 實 施 例 1 Φ1.7χ1.0 8.0 1.5 56 5.7 90 71 2 5.2 1.5 96 2.4 92 73 3 4.0 1.5 100 1.1 95 84 4 2.0 1.5 100 1.0 96 85 5 Φ0.8χ0.7 3.0 1.5 100 1.5 90 80 6 2.0 1.5 100 1.0 95 85 7 Φ1.7x1.0 1.2 1.5 100 0.01 99 91 8 Φ 1.7x1.0 9.5 1.5 41 9.8 90 65 比較例 Φ1.7x1.0 12.4 1.5 11 13.4 89 31 -35- 201031032 由表1所示結果，可知在使用坎德拉不良面積率在 1 〇%以下的基板的場合（實施例1 ~實施例8 )，可以得到 LED晶片的綜合產率超過6 5 %之特別的效果。又，坎德拉‘ 不良面積率爲0%之基板無法使用。 此外，在具有同一形狀的凸部的基板（實施例1〜實 施例4、實施例7、實施例8 ) ，GBIR値越小SBIR合格 率越高時，有晶片綜合產率變高的傾向。特別，可知 GBIR値在5μιη以下的場合（實施例3〜實施例6、實施例 @ 7)，顯示晶片綜合產率超過80%之顯著效果。 對此，使用坎德拉不良面積率超過10%的基板的場合 (比較例），可知其後的LED晶片之綜合產率極端低到 3 1 %。藉此，凸部形狀產生不均一很低部分的話，使取向 附生成長ΠΙ族氮化物半導體層（下底層）13的場合，因 凸部的階差影響無法被均一地平坦化，所以應該會在該階 差的邊界附近容易產生錯位（dislocation)或小坑（pit) ，結果導致除了 ESD產率降低以外也使低電流洩漏（漏 @ 電流）所致之電氣特性不良率增加。 【圖式簡單說明】 圖1係說明本實施型態適用的半導體發光元件用模板 基板之一例之圖。 圖2係說明被形成複數凸部的基板之圖。 圖3係說明半導體發光元件用模板基板的製造步驟之 圖。 -36- 201031032 圖4係顯示III族氮化物半導體發光元件之一例之剖 面圖。 【主要元件符號說明】 1 : III族氮化物半導體發光元件 1 1、1 0 1 :基板 12 :緩衝層 ❹ 13 ·‘ III族氮化物半導體層（下底層） 14 : η型半導體層 1 5 :發光層 16 : ρ型半導體層 1 7 :透明電極 1 8 :正極焊墊 1 9 :負極 20 ： LED構造 ⑩ 102 :凸部 1〇 :半導體發光元件用模板基板 -37-The flatness (GBIR) shown in Table 1, the diameter of the SBIR yield of 4 吋 (100 mm), and the (〇〇〇1) C plane of the sapphire plate 10 having a plate thickness of 90 μm are formed by the steps shown below. The substrate 101 is formed by a convex portion having a maximum diameter or a base width and a different height. At this time, the substrate processing is formed by a known photolithography method, and the sapphire plate 10 is etched by dry etching to form a convex portion. Further, as an exposure method, -33-201031032 uses a stepper exposure method using ultraviolet rays. In addition, a mixed gas of BC13 and Cl2 is used for dry uranium engraving. Thereafter, in order to evaluate the uniformity of the convex portion processing, the optical area analysis device (Candela) was used to calculate the defective area ratio. Next, on the substrate, a buffer layer 12 composed of an aluminum nitride layer having a thickness of 3 Onm as shown in FIG. 1 is formed by sputtering, and then subjected to an organic metal chemical vapor deposition method (MOCVD). Forming a group III nitride semiconductor layer 下 (lower bottom layer) having a thickness of 4.5 μm and a gallium nitride doped with germanium (concentration lxl 〇 19/cm 3 ) The n-type contact layer 14a having a thickness of 3 μm was taken out by the MOCVD apparatus to form a template substrate. Thereafter, on the template substrate, an InQ1GaQ.9N layer having a thickness of about 2 nm and a gallium nitride layer having a thickness of about 2 nm is layer-by-layer laminated by an MOCVD method. The n-type clad layer 14b of the super-lattice structure of 20 times, the barrier layer 15a of 6_5 nm thick composed of gallium nitride and the well layer 15b of 3.0 nm @ formed by N are alternately laminated 6 times, and finally The light-emitting layer 15 of the multiple quantum well structure of the barrier layer 15a, the interlayer layer of the thickness of 4 nm, which is composed of undoped Al〇.Q7GaQ 93 N having a thickness of 4 nm and gallium nitride doped with magnesium (concentration of 4×10 1 /Scm 3 ) The p-type cladding layer 16a' and the doped magnesium (concentration lxl〇2()/cm3) gallium nitride are formed into a compound semiconductor wafer having a thickness of 0.15 μm. At this time, the total film thickness of the group III nitride semiconductor layer of the LED structure 20 was 8 μm. Next, using the substrate formed of each layer -34 - 201031032 which is obtained in the LED structure thus obtained, a bismuth nitride semiconductor light-emitting device was produced by the procedure shown below. First, a transparent positive electrode made of IZO is formed on the p-type contact layer of the substrate to be formed of each layer of the LED structure by a known photo-etching technique, and titanium is sequentially laminated on the transparent positive electrode. Positive electrode pads for platinum and gold construction. Next, the substrate on which the positive electrode bonding pad is formed is dry-etched to expose the n-type semiconductor layer of the portion where the negative electrode is formed, and the layered titanium, platinum, and the like are formed on the n-type semiconductor layer. The negative electrode of the gold structure. Next, the back surface of the substrate on which the positive electrode pad and the negative electrode are formed by boring and honing is formed into a mirror-like surface. Next, the substrate was divided into a square wafer shape of 3 50 μm square to form a semiconductor light-emitting device wafer. The results are not shown in Table 1. [Table 1] Shape of the convex portion Diameter X Height μιη Flatness (GBIR) μιη Part Flatness (SBIR) μιη SBIR Passivity % Candela Bad Area Rate % ESD Yield % Wafer Comprehensive Yield % Example 1 Φ1.7χ1. 0 8.0 1.5 56 5.7 90 71 2 5.2 1.5 96 2.4 92 73 3 4.0 1.5 100 1.1 95 84 4 2.0 1.5 100 1.0 96 85 5 Φ0.8χ0.7 3.0 1.5 100 1.5 90 80 6 2.0 1.5 100 1.0 95 85 7 Φ1. 7x1.0 1.2 1.5 100 0.01 99 91 8 Φ 1.7x1.0 9.5 1.5 41 9.8 90 65 Comparative Example Φ1.7x1.0 12.4 1.5 11 13.4 89 31 -35- 201031032 From the results shown in Table 1, it can be seen that the use of Candela is not good. In the case of a substrate having an area ratio of 1% or less (Examples 1 to 8), a special effect that the overall yield of the LED wafer exceeds 65% can be obtained. Also, Candela's substrate with a poor area ratio of 0% cannot be used. Further, in the substrate having the convex portions having the same shape (Examples 1 to 4, Example 7, and Example 8), the smaller the GBIR値 is, the higher the SBIR yield is, and the higher the overall yield of the wafer tends to be. In particular, it is understood that when the GBIR 値 is 5 μm or less (Examples 3 to 6, and @7), the remarkable effect that the overall yield of the wafer exceeds 80% is exhibited. On the other hand, in the case of using a substrate having a Candela ratio of more than 10% (Comparative Example), it is understood that the overall yield of the subsequent LED chips is extremely as low as 31%. Therefore, when the shape of the convex portion is uneven and the low-order portion is formed, when the long-side bismuth nitride semiconductor layer (lower bottom layer) 13 is formed, the influence of the step of the convex portion cannot be uniformly flattened, so it should be Dislocations or pits are likely to occur near the boundary of the step, resulting in an increase in the rate of poor electrical characteristics due to low current leakage (leak @ current) in addition to a decrease in ESD yield. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an example of a template substrate for a semiconductor light-emitting device to which the present embodiment is applied. Fig. 2 is a view showing a substrate on which a plurality of convex portions are formed. Fig. 3 is a view showing a manufacturing step of a template substrate for a semiconductor light-emitting device. -36- 201031032 Fig. 4 is a cross-sectional view showing an example of a group III nitride semiconductor light-emitting device. [Description of main component symbols] 1 : Group III nitride semiconductor light-emitting device 1 1 , 1 0 1 : Substrate 12 : Buffer layer ❹ 13 · 'Group III nitride semiconductor layer (lower bottom layer) 14 : η-type semiconductor layer 1 5 : Light-emitting layer 16 : p-type semiconductor layer 17 : transparent electrode 18 : positive electrode pad 1 9 : negative electrode 20 : LED structure 10 102 : convex portion 1 : template substrate for semiconductor light-emitting element - 37 -