TW201029118A - Chip layout for reducing warpage and method thereof - Google Patents

Chip layout for reducing warpage and method thereof Download PDF

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Publication number
TW201029118A
TW201029118A TW98102932A TW98102932A TW201029118A TW 201029118 A TW201029118 A TW 201029118A TW 98102932 A TW98102932 A TW 98102932A TW 98102932 A TW98102932 A TW 98102932A TW 201029118 A TW201029118 A TW 201029118A
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TW
Taiwan
Prior art keywords
bumps
wafer
bump pitch
plurality
layout
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Application number
TW98102932A
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Chinese (zh)
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TWI409917B (en
Inventor
Chiu-Shun Lin
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Himax Tech Ltd
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Priority to TW98102932A priority Critical patent/TWI409917B/en
Publication of TW201029118A publication Critical patent/TW201029118A/en
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Publication of TWI409917B publication Critical patent/TWI409917B/en

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Abstract

A chip layout and a method thereof, suitable for a chip package process, are provided. The chip layout includes an application circuit and a plurality of first bumps. The application circuit is disposed on an area of the chip, and the pluralities of first bumps are disposed on a first side of the chip. A max gap between the first bumps is smaller than 1.1 multiple of a wide of the chip. Therefore, a warpage effect occurring in the chip package process can be reduced.

Description

201029118 HM-20〇8-〇〇65-Xw 29279twf.doc/d VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a wafer layout and method thereof, and more particularly to a reduction in warpage (Warpage) wafer layout and method. [Prior Art] In the semiconductor industry, the production of integrated circuits (also known as 1C, microcircuits, or wafers) consists of three phases: edge-forming wafers, integrated circuits on the wafer, and packaged bodies. Circuit. The integrated circuit is mass-produced on a single wafer through a semiconductor process such as a lithography process. The wafer can be cut into a plurality of sheets, and each sheet can be referred to as a die, on which a functional circuit is fabricated. The die is electrically connected to the carrier through a pad on the die to form a wafer package structure. In the wafer packaging process, bumps are usually formed on the pads to electrically connect them to the carrier, thereby reducing signal noise, increasing pad electrode density, and obtaining a thin package outline. The chip packaging process ❹ mainly includes Tape Automated Bonding (TAB), chip on film (COF) and chip on glass (COG) processes, which are commonly used for mounting liquid crystal displays. (Crystal Crystal Display, LCD) and plasma display (piasma Display) and other flat panel display driver chips. The wafer glass bonding process is to interface the glass with bumps on the drive wafer as joints. The wafer glass bonding process is carried out by attaching an anisotropic conductive film (ACF) to the glass. 3 201029118 ΗΜ-ζουκ-0065-TW 29279twf.doc/d. After the alignment of the driving wafer and the glass through the alignment of the imaging system, the driving wafer is directly pre-compressed with the conductive terminals on the glass and subjected to a thermocompression pressing operation to complete the bonding. Since the wafer glass bonding process directly mounts the driver wafer on the glass, the use of the tape and the internal and external pin bonding processes are reduced, so that the cost is low and the process is easy. However, due to the difference in the coefficient of expansion between the wafer and the glass and the geometric asymmetry of the structure, when the two are subjected to thermocompression bonding, the wafer is easily bent, and the bump electrodes arranged in the array are connected to the lower glass. It is difficult to close the foot, which in turn reduces the overall yield. SUMMARY OF THE INVENTION In view of the above, the present invention provides a wafer layout and a method thereof that can reduce the phenomenon of fascination caused by a wafer packaging process. The present invention proposes a wafer layout suitable for a wafer packaging process. The crystal layout includes an application circuit and a plurality of first bumps. The application circuit is disposed in one of the regions of the wafer, and the plurality of first bumps are disposed on the first side of the wafer. The maximum bump pitch between the first bumps is less than twice the width of the wafer. In the embodiment of the present invention, the above wafer layout further includes a plurality of dummy bumps, which are placed in the maximum bump pitch. (4) In the present invention, the m♦ board further includes a plurality of (four) bumps disposed on the first side of the wafer and parallel to the bump spacing between the first bumps of the first and the bumps. Less than the maximum bump pitch, and a plurality of dummy bumps are disposed within the bump pitch. 201029118 HM-2OU8-0065-TW 29279twf.doc/d The present invention proposes a wafer layout method suitable for a wafer packaging process. First, a wafer is provided in which an application circuit is disposed in an area of the wafer. Then, a plurality of first bumps are formed on the first side of the wafer, wherein the maximum bump pitch between the first bumps is less than a multiple of the width of the wafer. In an embodiment of the invention, the wafer layout method further includes forming a plurality of dummy bumps within a maximum bump pitch. In an embodiment of the invention, the wafer layout further includes forming a plurality of second bumps on the first side of the wafer, wherein the second bumps are parallel to the bumps, and the bumps between the first bumps are The pitch is less than the maximum bump pitch. Based on the above, the wafer layout of the present invention allows the maximum bump pitch of the first bumps to be less than 1.1 times the wafer width and/or the dummy bumps to be added to increase the joint, thereby improving the warpage of the wafer during the packaging process. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. Embodiments Fig. 1 is a plan view showing a layout of a wafer according to an embodiment of the present invention. The wafer 100 includes an application circuit 110, a first bump B1, and a second bump B2, wherein the first bump B1 and the second bump B2 are, for example, high-conductivity and good solder (five) or Made of noodles. The circuit 110 should be disposed in one area of the wafer 1 , which may be a logic circuit or an analog circuit for data processing or #_换 U block m 2 second bump B2 is disposed on the first side of the wafer 1 Touching a to electrically connect the wafer 1〇0 to the carrier, and the second bump is loosely parallel to the first bump 201029118 HM-2008-0065-TW 29279twf.doc/d B1, wherein the carrier is, for example, a flexible printed circuit Flexible printed circuit. In general, the application circuit 110 can be disposed in the central region of the wafer 100 to smooth the routing of signal transmission. Moreover, the block of the application circuit 110 disposed on the wafer can change its shape to fill the layout space on the wafer 100, for example, the first bump B1 and/or the second bump B2 are in the gap between the central regions of the wafer 100. Formed area A. Wherein, the bump pitch Lmax between the first bumps B1 is the maximum pitch between the bumps formed on the wafer 1 , and the bump pitch L between the second bumps B2 is smaller than the first bump B1 The maximum bump spacing Lmax between. In the wafer packaging process, the stress distribution of the wafer 1 is affected by the number of bumps and the position of the bumps, and uneven force is generated. For example, when the first bump B1 and the pins on the glass substrate are subjected to a semiconductor bonding process (for example, a wafer glass bonding process), the first bumps Bla and Blb located at both ends of the maximum bump pitch Lmax have a larger The bump spacing causes the stresses here to differ from the other locations, and β produces a so-called Warpage phenomenon. At this time, the first bump and the Bib cannot be closely engaged with the pins on the glass substrate, and there is a possibility that the transmission signal is broken. Therefore, in this embodiment, the maximum bump pitch Lmax between the first bumps is designed to be less than 宽度 times the width of the wafer to ensure the bumps on the wafer 100 (including the first bump B1 and the second bump B2) and The pins on the glass substrate can be tightly joined, wherein the width of the wafer 100 is the length of the second side 100b of the wafer 1 and the second side 1b is the adjacent side of the first side 100a. 6 201029118 mvi-zuuo-0065-TW 29279twf.doc/d Figure 2 is a top plan view of a wafer layout in accordance with another embodiment of the present invention. Referring to FIG. 2, the wafer 200 is different from the wafer 1 of the embodiment of FIG. 1 in that the wafer 200 further includes a plurality of dummy bumps D1 and 〇2 (only two are schematically shown here), and is virtualized. The bumps D1 and D2 are disposed in the maximum bump pitch Lmax and the bump pitch L respectively shown in FIG. 1 of the embodiment. The dummy bumps D1 and D2 do not have the function of transferring data between the chip 200 and an external circuit. Due to the greater difference in the spacing between the bumps, the stresses that the bumps are subjected to during bonding are less uniform and the warpage is more severe. In this embodiment, the manner of configuring the dummy bumps D1 and D2 can reduce the spacing between the bumps. For example, the distance between the large bumps Lmax and the bump pitch L of the example 1 is reduced to the embodiment FIG. The maximum bump pitch Lmax and the bump pitch L' are shown, thereby making the maximum bump pitch Lmax less than 1.1 times the width of the wafer 200. Thereby, the two bumps Bla and Blb at the two ends of the maximum bump pitch Lmax and the bump pitch; the second bumps B2a and B2b at both ends of the L are uniformly stressed during bonding, so that they can be bonded to the glass substrate. The tight joint of the pins. • In addition, the application circuit 210 can be disposed in the central area of the wafer 200 to smooth the signal transmission. The application circuit 21 can change the shape of the block on the wafer to fill the layout space on the wafer 200, for example, the area formed by the gap between the virtual bump D1 and/or the dummy bump D2 in the central area of the wafer 200. B. It should be noted that the present embodiment only schematically shows two columns of bumps arranged along the first side 200a (ie, the first bump B1 and the second bump B2), but in other embodiments, the convex The number of columns of a block is not limited to this. As long as the maximum bump pitch Lmax 201029118 x^-^wwo-0065-TW 29279twf.doc/d on the wafer 200 is less than U times the crystal width, it is the spirit of the present invention. 3 is a top plan view of a wafer layout in accordance with another embodiment of the present invention. Please note that the wafer 3 is different from the wafer of the embodiment of FIG. 1 in that the wafer 300 further includes a plurality of dummy bumps.

❿ There are two in each place). The dummy bumps 01 respectively replace the first bumps B1 on both sides of the Lmax (for example, the first bumps Bla and Bib shown in the embodiment of FIG. 3, and the number of the first bumps m is not limited thereto). And the dummy bumps D2 respectively replace the second bumps B2 near the two sides of the bump pitch L (for example, the first bumps B2a shown in FIG. 1 of the embodiment and the second bumps B2 are not limited thereto). number). Among them, the dummy bumps m and D2 do not have the function of transferring data between the chip 200 and an external circuit. Under the constraint that the maximum bump pitch Lmax is less than U times the width of the wafer 200, it is ensured that the stress applied to the bump during bonding is uniform and warpage is avoided. According to the description of the above embodiments, the following method flow can be summarized. 4 is a flow chart of a wafer layout method according to an embodiment of the present invention. Referring to Figures 2 and 4', a wafer 200 is first provided, and an application area 110 is disposed in a region of the wafer (step S401). Next, the first bump B1 is formed on the first side 100a of the wafer 2, and the maximum bump pitch Lmax between the first bumps Bi is less than 11 times the width of the wafer 200, wherein the application circuit 110 The configured area may be within a range formed by the maximum bump pitch Lmax (step S403). In addition, a plurality of dummy bumps χ) 1 may be formed within the maximum bump pitch Lmax between the first bumps bi (step S405) or the virtual bumps D1 may be substituted for the largest bumps as shown in FIG. 3 of the embodiment. The first bumps B1 on both sides of the pitch ensure the correct bonding of the wafer 1 and the glass substrate, and avoid the occurrence of warpage. In summary, the wafer layout of the above embodiment is such that the maximum value of the design bump pitch must be less than 1.1 times the width of the wafer, so that the bumps on the wafer can be bonded to the glass substrate during the packaging process. The pins are tightly joined. In addition, dummy bumps can be formed in the bump pitch to keep the stresses of the bumps uniform during bonding. In this way, the warpage caused by the wafer in the packaging process can be reduced, and the integrity of the signal transmission can be ensured. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a plan view of a wafer layout in accordance with one embodiment of the present invention. 2 is a top plan view of a wafer layout in accordance with another embodiment of the present invention. 3 is a top plan view of a wafer layout in accordance with another embodiment of the present invention. Figure 4 is a flow diagram of a wafer layout method in accordance with one embodiment of the present invention. [Description of main component symbols] 100, 200, 300: Wafer 110: Application circuits 100a, 200a: First side 100b, 200b: Second side A, B: Area 201029118 HM-2008-0065-TW 29279twf.doc/ d B1, Bla, Bib: first bumps B2, B2a, B2b: second bumps Db D2: dummy bumps L, L,: bump pitch

Lmax, Lmax': maximum bump pitch S401 to S405: steps of the wafer layout method of the embodiment of the present invention

10

Claims (1)

  1. 201029118 Γχινχ-ζ.υυο-0065-TW 29279twf.doc/d VII. Patent Application Range: 1. A wafer layout suitable for a chip packaging process, comprising: an application circuit disposed in an area of the wafer; A plurality of first bumps are disposed on a first side of the wafer, wherein a maximum bump pitch between the first bumps is less than 1.1 times a width of one of the wafers. 2. The wafer layout of claim 1, further comprising: a plurality of dummy bumps ′ disposed respectively within the maximum bump pitch. 3. The wafer layout of claim 1, further comprising: a plurality of dummy bumps respectively replacing the first bumps near the two ends of the maximum bump pitch. 4. The wafer layout of claim 1, further comprising: a plurality of second bumps respectively disposed on the first side of the wafer and parallel to the first bumps, wherein the A bump spacing between the second bumps is less than the maximum bump pitch; and a plurality of dummy bumps are respectively disposed within the bump pitch. 5. The wafer layout of claim 1, further comprising: a plurality of second bumps respectively disposed on the first side of the wafer and parallel to the first bumps, wherein the A bump spacing between the second bumps is less than the maximum bump pitch; and a plurality of dummy bumps respectively replace the two bumps near the ends of the bump pitch. 6. The wafer layout of claim 1, wherein the wafer packaging process is a chip 〇n glass (COG) process. 7. The wafer layout of claim 1, wherein the application circuit is a logic circuit or an analog circuit, and the region is located in the wafer layout. central. θ θ 8. The wafer layout of claim 1, wherein the region is within a range formed by the maximum bump pitch. 9. A wafer layout method suitable for a wafer packaging process, comprising: providing a wafer, wherein an application circuit is disposed in a region of the wafer; and
    Forming a plurality of first bumps on a first side of the wafer, wherein (a) a maximum bump pitch between the first bumps is less than a width of the wafer = 1. 1 times, and the region includes the maximum The range formed by the bump pitch. The wafer layout method of claim 9, wherein the rule comprises: forming a plurality of dummy bumps within the maximum bump pitch. 11. The wafer layout method as described in claim 9
    12. The method of forming a plurality of second bumps on the wafer by the w-handle of the ninth job of the application of the ninth job: the first bumps, wherein the second bumps are between the bumps The maximum bump pitch is performed; and the distance 1 is smaller than the plurality of dummy bumps are formed within the bump pitch. I3. The wafer layout as described in claim 9 of the patent application, further comprising: 12 201029118, HM-2008-0065-TW 29279twf.doc/d ' forming a plurality of second bumps on the first side of the wafer And parallel to the first bumps of the S, wherein a bump pitch between the second bumps is smaller than the maximum bump pitch; and the second bumps respectively replacing the two ends of the bump pitch are plural Virtual bumps. 14. The wafer layout method of claim 9, wherein the wafer packaging process is a chip 接合n yass (c〇G) process. 15. The wafer layout method of claim 9, wherein the application circuit is a logic circuit or an analog circuit, and the region is located in the center of the s-chip layout. 16. The wafer layout method of claim 9, wherein the region is within a range formed by the maximum bump pitch. 13
TW98102932A 2009-01-23 2009-01-23 Chip layout for reducing warpage and method thereof TWI409917B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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TWI409917B TWI409917B (en) 2013-09-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI662633B (en) * 2017-07-03 2019-06-11 南茂科技股份有限公司 Bumping process and flip chip structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7202556B2 (en) * 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
TWM305962U (en) * 2006-04-21 2007-02-01 Powertech Technology Inc Ball grid array package structure
US20080099890A1 (en) * 2006-10-30 2008-05-01 Powertech Technology Inc. Ball grid array package structure
JP2008166373A (en) * 2006-12-27 2008-07-17 Nec Electronics Corp Semiconductor device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI662633B (en) * 2017-07-03 2019-06-11 南茂科技股份有限公司 Bumping process and flip chip structure

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