TW200901442A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

Provided is a semiconductor device manufacturing method comprising a first step of forming a first wiring line over a semiconductor substrate, a second step of forming storage elements over the first wiring line, a third step of so forming a first insulating film over the semiconductor substrate as to bury the storage elements, a fourth step of forming such a second insulating film over the first insulating film and the storage elements as has etching characteristics different from those of the first insulating film, a fifth step of etching the second insulating film by using the first insulating film as an etching stopper, thereby to form such grooves in the second insulating film as to expose the upper portions of the storage elements, and a sixth step of burying second wiring lines in the grooves.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a memory device and a method of fabricating the same. [Prior Art 1] Recently, a semiconductor device in which a memory element is provided at a intersection of a wiring on the lower layer side and a wiring on the upper layer side has been proposed. 10 Figure 27 is a perspective view showing the proposed semiconductor device. As shown in Fig. 27, the plurality of wires 128 are formed in parallel with each other on a semiconductor device (not shown). The plurality of wires 132 are formed above the wires 128 in parallel with each other in such a manner as to intersect the wires 128. A memory element (resistance memory element 15) 130 is provided at a portion where the wiring 128 on the lower layer side and the wiring 132 on the upper layer side intersect each other. The wiring 128 on the lower layer side is connected to the lower electrode of the memory element 130 (not shown), and the wiring 132 on the upper layer side is connected to the upper electrode of the memory element 13 (not shown). Since the memory element 130 is provided at the intersection of the wiring 128 on the lower layer side and the wiring 132 on the upper layer side, the semiconductor device shown in Fig. 27 is called an intersection type memory element. The resistive memory element 130 is a resistor that sandwiches a pair of electrodes by a resistor that changes the state of the resistor by applying a voltage. Once the resistance memory element 13 施 applied to the high resistance state is slowly raised, when the voltage exceeds a certain value, the resistance value sharply decreases, and the resistance memory element 13 〇 shifts to the low resistance state. On the other hand, when the voltage applied to the resistance memory element 200901442 of the low resistance state is gradually increased in the opposite direction to the low resistance state, when the voltage exceeds a certain value, the resistance value is sharply Increasing, the resistive memory element 130 transitions to a high resistance state. The high-resistance state and the low-resistance state of the associated memory element 130 are assigned, for example, to the corresponding "0" and "1" of the information, and can be utilized as a memory element. As described above, the proposed semiconductor device can write data to the resistive memory element by simply applying a voltage to the resistive memory element. Further, when a predetermined read current is supplied to the resistance memory element, the state of the current value flowing through the resistance memory element is measured, and the data can be read. The proposed semiconductor 10 device can achieve high speed, large capacity, low power consumption, etc., and thus can be expected to have a future. Further, the background of the present invention is as follows. Patent Document 1: JP-A-2002-530850 15 Patent Document 2: US Patent No. 7020012 Specification Patent Document 3: Patent No. 3449998

Patent Document 4: Japanese Laid-Open Patent Publication No. Hei No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. Japanese Unexamined Patent Publication No. Hei No. Hei. No. Hei. No. Hei. No. Hei. No. 2006-108. The semiconductor device proposed in Fig. 27 is formed on the interlayer insulating film by connecting the wiring 132 on the upper layer side to the upper electrode of the memory element 89 (not shown in the drawing). In the figure, when the pattern position shift of the via hole occurs, the female interlayer insulating film on the side of the memory element (10) is turned off, and the via hole reaches the wiring 128 on the lower layer side. In the case where a conductor socket (not shown) is embedded in such a via hole, the wiring 132 on the upper layer side of the connection conductor socket and the wiring (2) on the lower layer side are in a new way. The edge of the positional displacement of the via hole becomes smaller as the semiconductor device is miniaturized. Therefore, it is expected that the wiring on the upper layer side is not reliably connected to the upper electrode of the memory element 130 as compared with the wiring on the lower layer side than the wiring m on the lower layer side. The purpose of the present invention is to provide a semiconductor device in which the wiring of the upper layer (four) wiring 132 on the lower layer 15 side is not short-circuited, and the wiring on the upper layer side is connected to the upper electrode of the memory element 130, and a method of manufacturing the same. Means for Solving the Problems According to the present invention, there is provided a method of manufacturing a semiconductor device, the material (4) of the material device comprising: an i-th step of forming a (4) 2 turn line on a semiconductor substrate; a second step of forming a memory element on the first wiring; a third step of forming an ith insulating film on the semiconductor substrate for entering the memory 7L; on the first insulating film and on the memory element Forming a second insulating lining step different from the etch characteristic of the first insulating film; using the red insulating film as the (four) blocking layer, 200901442, and etching the second insulating film to expose the upper portion of the memory element The fifth step of forming the second insulating film and the sixth step of embedding the second wiring in the trench. Moreover, according to another aspect of the present invention, a method of manufacturing a semiconductor device 5 comprising: a first step of forming a first wiring on a semiconductor substrate; and a memory element formed in the semiconductor device 5 a second step of the first wiring; a third step of forming a first insulating film on the semiconductor substrate to be embedded in the memory element; and forming the first insulating film on the first insulating film and the memory element a fourth step of etching the second insulating film having different properties; a fifth step of forming a third insulating film different from the etching property of the second insulating film on the second insulating film; and the second insulating film a sixth step of forming a trench in the third insulating film by etching the third insulating film as an etching stopper; and etching the second insulating film exposed to the trench by using the first insulating film as an etching stopper film The seventh step of forming a groove for exposing the upper portion of the memory element is formed at 15; and the eighth step of embedding the second wire in the groove is performed. According to still another aspect of the present invention, a semiconductor device including: a first wiring formed on a semiconductor substrate; a memory element formed on the first wiring; and the semiconductor 20 substrate a first insulating film formed by embedding the memory element; a second insulating film formed on the first insulating film and having different etching characteristics from the first insulating film; and being embedded in the second insulating film The trench is connected to the second wiring of the memory element. According to still another aspect of the present invention, a semiconductor device is provided, which includes: a fourth line formed on a semiconductor substrate; a memory element formed on the first wiring; "on the semiconductor substrate a second insulating film formed on the memory element; a second insulating film formed on the first insulating film and having different etching characteristics from the first insulating film; and the second insulating film formed on the second insulating film a third insulating film having a different etching property from the second insulating film is embedded in the trench formed in the second insulating film and the third insulating film, and is connected to the second wiring of the memory element. The effect of the invention is as follows: (1) The first insulating film of the second wiring groove of the human (10) is used to form a first insulating film having different surname characteristics in advance of the memory element. When the groove for inserting the second wiring is formed on the second insulating film, the groove phase is prevented, and the lower electrode and the first line of the element are formed. Thus, according to the present invention, the second wiring and the memory element can be reliably prevented. Lower electrode And the second wiring is short-circuited, and the second wiring can be connected to the upper electrode of the memory element 15. Further, according to the present invention, the first insulating film is formed to be embedded in the memory element, and has a different name relative to the first insulating film. The second insulating film having characteristics is formed on the first insulating film and the memory element, and the third insulating film having etching characteristics different from those of the second insulating film is formed on the second insulating film, and the second insulating film is used as the silver engraving 20 The third insulating film is formed in the third insulating film to form a trench in the third insulating film, and the second insulating film exposed in the trench is removed by contact to form a surface on which the memory element is exposed. The trench of the germanium electrode is exposed by etching. When the second insulating film in the trench has a function as an etching stopper layer, the trench does not reach the lower electrode of the memory element and the first wiring. Therefore, according to the present invention, 200901442 can also prevent the second. The wiring and the lower electrode of the memory element and the second wiring are short-circuited, and the second wiring is connected to the upper electrode of the memory element. Brief Description of the Drawings Fig. 1 shows a semiconductor 5 constructed according to the third embodiment of the present invention. Figure 2 is a perspective view showing a portion of a semiconductor device constructed in accordance with an ith embodiment of the present invention. Fig. 3 is a view showing a method of fabricating a semiconductor device constructed in accordance with a third embodiment of the present invention. FIG. 4 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 4 is not based on the third embodiment of the present invention. FIG. 6 is a cross-sectional view showing a step of manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view showing a step of manufacturing a semiconductor device according to a third embodiment of the present invention. 7 is a cross-sectional view (fifth) of a method of manufacturing a semiconductor device constructed in accordance with a first embodiment of the present invention. The eighth chart is not based on the manufacture of a semiconductor device constructed in accordance with a third embodiment of the present invention. A cross-sectional view of the method (sixth). (2) Step 9 of the method of manufacturing a semiconductor device according to the first embodiment of the present invention (the seventh). Fig. 10 is a cross-sectional view showing the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention (part 8). The eleventh diagram is a cross-sectional view (ninth) of the method of manufacturing the semiconductor device according to the first embodiment of the present invention. Figure 12 is a cross-sectional view showing a semiconductor device constructed in accordance with a second embodiment of the present invention. Figure 13 is a cross-sectional view (part 1) showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Figure 14 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Fig. 15 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Fig. 16 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Fig. 17 is a plan view showing the steps of the method of manufacturing the semiconductor device according to the second embodiment of the present invention (the fifth). Figure 18 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. Fig. 19 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Figure 20 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Fig. 21 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Fig. 2 is a cross-sectional view showing the steps of the method of manufacturing the semiconductor device according to the third embodiment of the present invention. Figure 23 is a cross-sectional view (fifth) showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Figure 24 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Figure 25 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention (the seventh). Figure 26 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Fig. 27 is a perspective view showing a semiconductor device of the prior art. Fig. 28 (a) and (b) are cross-sectional views showing the steps of a manufacturing method in which a conventional semiconductor device is applied to a conventional semiconductor device. Fig. 29 (a) and (b) are sectional views (part 1) showing a method of manufacturing an etching stopper film for a conventional semiconductor device. Figure 30 is a cross-sectional view showing the steps of a method of manufacturing an etching stopper film for a semiconductor device of the prior art. [Embodiment] BEST MODE FOR CARRYING OUT THE INVENTION Fig. 28 is a cross-sectional view showing the steps of a manufacturing method in which a conventionally proposed method is applied to a conventional semiconductor device. First, an interlayer insulating film 120 composed of, for example, a tantalum oxide film is formed on a semiconductor substrate 20 110 on which a transistor (not shown) is formed. Next, the conductor socket 122 and the wiring 128 are embedded in the interlayer insulating film 120. The longitudinal direction of the wiring 128 forms a plurality of memory elements 130 having the left-right direction of the paper surface of Fig. 28. The memory element 130 is formed in a matrix as shown in Fig. 27. Next, an interlayer insulating film 144 is formed. Next, the photoresist film 154 is entirely formed. Next, an opening portion 156 for forming the via hole 146 is formed on the photoresist crucible 154 by 12 200901442 photolithography. Next, the interlayer insulating film is etched by using the photoresist film 154 as a mask, whereby the via hole 146 exposing the upper electrode of the memory element 13 is formed. In the case where the pattern position of the opening portion 156 for forming the via hole 146 is shifted, as shown in Fig. 28 (4), the via hole 146 reaches the wiring 128 of the lower electrode 134 and the lower layer side of the memory element 130. Hey. In the case where the conductor socket 132 is embedded in such a guide hole 146, as shown in Fig. (b), the upper electrode and the lower electrode of the 5 memory element 13 are connected. That is, in this case, the wiring (not shown in the figure) connected to the upper layer side of the conductor receptacle 132 is short-circuited with the wiring 128 on the lower layer side, and the normal operation cannot be performed. Further, a case where the via hole is formed in the interlayer insulating film 120 by using the rhyme blocking film can also be considered. Fig. 29 and Fig. 3 are sectional views showing the steps of a manufacturing method in which a conventional semiconductor device is used to improve the above-described defects and the residual film is used. The step of forming the memory element 13 from the semiconductor substrate in which the transistor (which is not shown) has been formed to form the memory device 13 is the same as the method of manufacturing the semiconductor device described above with reference to FIG. 28 (8). The process 20 is omitted. Then, the (four) blocking film 140 composed of, for example, a stone nitride film is formed in an all-round manner. Next, an interlayer insulating film M4 composed of, for example, a cut oxide film is formed in an all-round manner. The receiver fully forms the photo-resistance film 154. An opening portion 156 for forming the via hole 146 is then formed on the photoresist film 154 using photolithography technology 13 200901442. Next, a via hole 146 for exposing the upper electrode 128 of the memory element 130 is formed by using the photoresist film 154 as a mask and etching the interlayer insulating film 144. In the case where the pattern of the opening portion 156 for forming the via hole 146 is shifted more than the film thickness of the etching stopper film 5 I40, as shown in Fig. 29 (a), the via hole 146 is present in the lower layer. The etch on the side wiring 128 blocks the film 140. Once the film 14 is exposed to the inside of the via hole 146, the film 14 is removed, and as shown in Fig. 29(b), the via hole 146 reaches the line 10 of the lower layer side. In the case where the conductor socket 132 is intended to be inserted into such a guide hole 146, as shown in Fig. 30, the upper electrode 138 and the lower electrode 134 of the memory element 13 are short-circuited. That is, in this case, the wiring (not shown) connected to the upper layer side of the conductor receptacle 132 is short-circuited with the wiring 128 on the lower layer side, and cannot be normally operated. As described above, the short circuit of the wiring 132 on the upper layer side and the wiring 128 on the lower layer side is not established, and the wiring 132 on the upper layer side is surely connected to the upper electrode 138 of the memory element 130. [First Embodiment] 20 A semiconductor device constructed in accordance with a first embodiment of the present invention and a method of manufacturing the same will be described with reference to Figs. 1 to 11 . (Semiconductor device) First, the structure of a semiconductor device constructed in accordance with the first embodiment of the present invention will be described using Figs. 1 and 2 . Fig. 1 is a cross-sectional view showing a semiconductor device constructed in accordance with the state of the present embodiment 200901442. Fig. 2 is a perspective view showing a part of a semiconductor device constructed in accordance with the present embodiment. The field 2 on the right side of the paper surface of Fig. 1 indicates the field in which the plurality of memory elements are arranged in a matrix, that is, the field of the memory cell, and the field 4 5 on the left side of the paper on the first drawing indicates the field separated from the memory cell field 2. As shown in Fig. 1, an element isolation region 12 defining the element regions 13a' 13b is formed on the semiconductor substrate 10. The transistor i8a having the gate electrode 14a and the source/drain diffusion layers 16a and 16b is formed by the element region 13a established by the element isolation region 12. Further, a transistor having a gate electrode 14b and source/dot diffusion layers 16c and 16d is formed by the element region 13b established by the element isolation region 12. An interlayer insulating film 20 made of, for example, a stone oxide film is formed on the semiconductor substrate 10 on which the transistors 18a and 18b are formed. The interlayer insulating film 20 is formed with a via hole 22a which can reach the source 15 / the gate diffusion layer 16a on one side of the transistor 18a, and a trench 24a which is connected to the via hole 22a. The plurality of grooves 24a are formed in parallel on the interlayer insulating film 20. The longitudinal direction of the groove 24a is the left-right direction of the paper surface of Fig. 1. Further, the interlayer insulating film 20 is formed with a via hole 22b which can reach the source/polar diffusion layer 16d on one side of the transistor 18b, and a trench 20 24a which is connected to the via hole 22b. The via hole 22b and the trench 24b are formed in the field 2 separated from the memory cell domain. A conductor socket 26a and a wiring 28a made of, for example, Cu (copper), W (tungsten) or the like are embedded in the via hole 22a in which the interlayer insulating film 20 is formed and in the trench 24a. The wiring 28a of this embodiment is integrally formed with the conductor socket 26a. Alternatively, the conductor socket 26a may be formed by W, and the wiring 28a may be formed of Cu. The plurality of wires 28a respectively embedded in the plurality of grooves 15a are formed in parallel with each other. The longitudinal direction of the wiring 28a is the left-right direction of the paper surface of Fig. 1. The wiring 28a is connected to the source/drain diffusion layer 16a on one side of the transistor 18a via the conductor socket 26a. A conductor socket 26b and a wiring 28b made of, for example, Cu, W or the like are embedded in the via hole 22b and the trench 24b formed in the interlayer insulating film 20. In the present embodiment, the wiring 28b is integrally formed with the conductor socket 26b, but the conductor socket 26b may be formed by w, and the wiring 28b may be formed by Cu. The wiring 28b is connected to the source/drain diffusion layer 16d on one side of the transistor 18b via the conductor socket 26b. On the wiring 28a embedded in the interlayer insulating film 20, a plurality of memory elements 10 are formed, and more specifically, a resistance memory element is formed. The memory element 3 is disposed at the intersection of the wiring 28a on the lower layer side and the wiring 32a on the upper layer side as shown in Fig. 2, respectively. Therefore, the plurality of memory elements are integrally arranged in a matrix. The resistive memory element 3G memorizes a high resistance state and a low resistance state, and is a memory element that switches between a high resistance state and a low resistance state in accordance with an applied voltage. 15 & tree 3 () includes a lower electrode 34, a resistive memory layer 36 formed on the lower electrode 34, and an upper electrode 38 formed on the resistive memory layer %. The already-made It3G is a resistor memory layer 36 by the lower electrode 34 and the upper electrode %. The material of the lower electrode 34 is, for example, a smear. The material of the layer 36 is made of, for example, a composite metal oxide (cM〇:c〇m coffee)

Metal 2〇 〇娜. The composite metal oxide contains an oxide of two or more kinds of metals. Examples of the metal contained in the composite metal oxide include a transition metal alkaline earth metal, a rare earth metal, and the like. The material used for the resistive memory layer 36 is, for example, 3. The resistive memory layer may be composed of a single layer film or a laminated film formed by sequentially laminating films of mutually different materials. Upper electric 16 200901442 The material of the pole 38 is used, for example, pt or the like. Once the resistance of the resistive element 30 in the high-resistance state is gradually increased, the electric dust exceeds a certain value (the set voltage Vs is sharply reduced, and the resistive memory element is transferred to the low-resistance state. Such 5 The action is generally referred to as "setting." In contrast, the voltage is applied to the resistive memory element 30 in the high resistance state in the opposite direction to the low resistance state, and the voltage exceeds a certain value (set voltage Vr^). The resistance value increases sharply by 10: the hidden element shifts to the high resistance state. Such an action is generally referred to as "reset according to such an action, and simply applying a voltage to the memory piece 30 can control the resistance memory element. The resistance state. Further, when a predetermined read current flows through the resistive memory element 3, the current value flowing through the resistive memory element 30 can be read by the data 疋15 on the semiconductor substrate 10 on which the memory element 30 is formed. On the other hand, an insulating film (protective film) 4{) made of, for example, an oxide film is formed to cover the memory element %. The core film 40 will be described later, and the insulating film made of the (tetra) film is used for polishing. Therefore, it is a function of the polishing stopper layer. Therefore, a material having a very slow polishing rate with respect to the insulating film 42 formed of the stone gasification film can be used as a material of the insulating film. Further, the insulating film composed of the oxide film has The function of preventing hydrogen, moisture, and the like from reaching the barrier film of the resistive memory layer 36. Since hydrogen and moisture can be prevented from reaching the resistive memory layer 36, it is possible to prevent the electric resistance = the memristive layer 36 from being reduced, and a memory having good electrical characteristics can be obtained. When the element 5 is formed to be embedded in the wiring 3 2 a, the trench 46 is formed on the insulating layer 4 4 and the insulating film 17 200901442 40. When the insulating film is excessively etched, the trench 46 reaches the lower electrode 34. The wiring 28a of the lower layer. In this case, the lower electrode 34 of the memory element 30 is short-circuited with the upper electrode 38, so that the memory element 30 cannot operate normally. The etching speed of the insulating film 4 formed by the oxidized chain film is relative to that of the germanium oxide film. The etching rate of the insulating film 44 is slower. Therefore, when the trench 46 is formed in the insulating film 44, the insulating film 40 is not excessively etched. The semiconductor formed with the insulating film 40 made of an aluminum oxide film is formed. The board 1 is formed with an insulating film 42 made of, for example, a tantalum nitride film 4 to embed the memory 30. In other words, a plurality of memory elements formed on the side 1 side of the insulating layer 4 made of an aluminum oxide film. An insulating film 42 made of a tantalum nitride film is filled between the layers 30. The upper portion of the insulating layer 42 made of a tantalum nitride film is polished using the insulating film 40 made of an aluminum oxide film as a polishing stopper layer. There is no insulating film made of tantalum nitride on the memory element 30. The height of the upper surface of the insulating film 4 made of an aluminum oxide film on the memory element 30 and the insulating film made of a 15 stone nitride film The upper surface 42 has the same height. When the groove 46 for the wiring 32a is formed on the insulating film made of the tantalum oxide film, the insulating film 42 made of the tantalum nitride film has a function as an etching stopper. An insulating film made of, for example, a ridge oxide film is formed on the insulating film 40 made of an oxidized film and the insulating film 42 made of a cerium nitride. 2〇 The insulating film composed of the oxide film and the insulating film 42 made of the Shihua nitride film are formed to be used for the purpose of the wiring. The plurality of trenches 46 formed in the insulating layer '44 are parallel to each other. The longitudinal direction of the groove 46 is the vertical direction of the paper surface of the first drawing. The groove 46 is formed in a state in which the upper surface of the memory element 3 is exposed. As the first! In the case where the pattern of the groove 46 is shifted in the left-right direction of the paper surface, it is known that the insulating film 4 不仅 not only on the memory element 3 but also the insulating film covering the side of the memory element 30 is known. A portion of the 40, even a portion of the insulating film 42 formed to embed the memory element 30, is also engraved. However, the etching rate of the insulating film 40 made of an aluminum oxide film is, for example, about one third of the etching rate of the insulating film 42 made of a tantalum nitride film. Further, the etching rate of the insulating film 42 composed of the tantalum nitride film is, for example, about one-fifth of the etching rate of the insulating film 44 composed of the tantalum oxide film. Therefore, when the trench 46 for embedding the wiring 32a is formed on the insulating films 4, 44, the insulating film 40 composed of the aluminum telluride film and the insulating film 42 composed of the tantalum nitride film are not excessively etched. engraved. According to this embodiment, when the grooves 46 for embedding the wirings 32a are formed on the insulating films 40 and 44, the grooves 46 can be surely prevented from reaching the lower electrodes 34 and the wirings 28a, and the wirings 28a and the lower portions can be surely prevented. The electrode 34 and the wiring 28a on the lower layer side are short-circuited. Further, in the field 4 separated from the memory cell region, the via holes reaching the wiring 28b are formed in the insulating films 44, 42, 40. A wiring line 32a such as cu or w is embedded in the groove 46 formed in the memory cell region 2. The plurality of wires 32a are formed in parallel with each other. The length direction of the wiring 32a is the vertical direction of the paper. In other words, the longitudinal direction of the wiring 32a on the upper layer side and the longitudinal direction of the wiring 28a on the lower layer side are orthogonal to each other (see Fig. 2).

Jc\ Also, in the field 4 separated from the memory cell field, a conductor socket 32b composed of, for example, Cu, W, or the like is contiguous in the via hole 48. Further, a wiring (not shown) similar to the above wiring and a memory element (not shown) similar to the above-described memory element 3 are formed in the upper portion of the wiring 32a. Further, the conductor socket 32b is electrically connected to the wiring provided in the upper portion (not shown) through a conductor socket or the like which is not shown in Fig. 2, 200901442. In this way, the semiconductor device constructed in the present embodiment is constructed. As described above, according to the present embodiment, the insulating film 42 having a very slow etching speed with respect to the insulating film 44' forming the trench 46 for embedding the 5 wiring 32a is formed to be embedded in the memory element 30, and thus is to be embedded. When the groove 46 of the wiring 32a is formed in the insulating film 44, the groove 46 can be surely prevented from reaching the wiring element lower portion 34 and the lower layer side wiring 28a. Therefore, according to the present embodiment, the upper layer side wiring 32a can be surely prevented from being The memory element 3 has a short circuit between the lower electric 10 and the lower side of the wiring 28a, and the wiring 仏 on the upper side can be connected to the upper electrode % of the memory element 30. (Manufacturing Method of Semiconductor Device) A method of manufacturing a semiconductor device constructed in accordance with the present embodiment will be described below using Figs. 3 to _. 3 to _ are sectional views showing the steps of a method of manufacturing a semiconductor device constructed in accordance with the present embodiment. First, as shown in Fig. 3, the element isolation region 12 for determining the element regions 13a, 13b is formed on the semiconductor substrate 1A. A transistor 18a having a gate electrode 14& and a source/drain diffusion layer 16a, 16b is formed on the element region 13a. Further, a mesa electrode 14b and a source electrode and a pole diffusion layer UN crystal 18b are formed on the second surface. Next, an interlayer insulating film 2 of, for example, a tantalum oxide film is formed on the semiconductor substrate 1 on which the transistors 18a and 18b are formed. Then, using the photolithography technique, the via hole 22a of the source 20 200901442 / drain diffusion layer 16a reaching one side of the transistor and the source/' and the polar diffusion layer 16d reaching one side of the transistor 8b are used. The via hole 22b is formed in the interlayer insulating film 2''. Next, a groove 24a connected to the guide hole 22a and a groove 24b connected to the guide hole 22b are formed by photolithography. In the field including the memory cell field 2, the plurality of complex grooves 24a are formed in parallel with each other. The longitudinal direction of the groove 24a is the left-right direction of the paper surface of Fig. 3. Next, for example, a film thickness of 2〇nmiTi film and a film thickness of 50 nm of a TiN film are sequentially formed by, for example, a sputtering method. Next, for example, a W film is formed by, for example, a CVD method. The film thickness of the W film is set to be more than half of the width of the grooves 24a and 24b. Further, an example in which W is used as the material of the conductor socket 26a' 26b and the wirings 28a and 28b has been described. It is also possible to use cu as the material of the conductor sockets 26a and 26b and the wiring 28a' 28b. In the case where Cu is used as the material of the conductor receptacles 26a and 26b and the wirings 28a and 28b, a Ta (钽) film is formed by, for example, sputtering. This Ta film has a function as a barrier metal. Next, a Cu film is formed by, for example, sputtering 15 plating and plating. In this way, Cu can also be used as the material of the conductor sockets 26a, 26b and the wirings 28a, 28b. Then, a conductive film made of W or Cu or the like is polished by CMP (Chemical Mechanical Polishing) to expose the surface of the interlayer insulating film 20. Thereby, the conductor socket 26a and the wiring 28a which consist of a conductive film 20 can be inserted in the inside of the guide hole 22a and the groove|channel 24a. Further, a conductor receptacle 26b and a wiring 28b made of a conductive film can be embedded in the via hole 22b and the trench 24b (see Fig. 4). Next, a conductive film 34 composed of, for example, a pt film having a film thickness of 25 nrn is formed in a total of, for example, a sputtering method. The conductive film 34 constitutes the electrode of the lower portion 21 200901442 of the memory element 3 . Next, a composite metal oxide layer 36 having a film thickness of 25 nm is formed entirely by, for example, sputtering. The composite metal oxide layer 36 constitutes a resistive memory layer of the memory element 3A. The composite metal oxide layer 36 is composed of two or more types of gold. The metal contained in the composite metal oxide layer 36 may, for example, be a transition metal, a soil-checking metal, a rare earth metal or the like. The description herein uses, for example, as the composite metal oxide layer 36. Next, a conductive film 38 made of, for example, a Pt film having a film thickness of 25 nm is formed entirely by sputtering, for example. The conductive film 38 constitutes an electrode of the upper portion 10 of the memory element 3A. As a result, a laminated film composed of the conductive film 34, the composite metal oxide layer 36, and the conductive film 38 can be formed. Next, the laminated film is patterned into the shape of the memory element 30. In this manner, the memory element 30 having the lower electrode 34, the resistive memory layer 36, and the upper electrode 15 38 can be formed (see Fig. 5). Further, the case where the lower electrode 34, the resistive memory layer 36, and the upper electrode 38 constitute the structure of the memory element 30 has been described by way of example, but the configuration of the memory element 30 is not limited thereto. For example, a 20-layer laminate in which the resistive memory layer 36 and the diode are laminated may be provided between the lower electrode 34 and the upper electrode 38. The present invention is not dependent on the particular constructor of memory element 30. Next, as shown in Fig. 6, an insulating film (protective film) made of, for example, an aluminum oxide film having a film thickness of 10 to 20 nm is integrally formed by, for example, a CVD method. The insulating film 40 composed of the oxide film has a function as a polishing stopper layer when the insulating film 42 made of a silicon nitride film is polished in the step described later, 22 200901442. Further, the insulating film 40 made of an aluminum oxide film has a function of preventing hydrogen, moisture, or the like from reaching the memory element 30 as a barrier film. Next, an insulating film 42 made of, for example, a ruthenium nitride film having a film thickness of 2?1111 is formed entirely by, for example, a CVD method. 5 Next, the surface of the insulating film 42 made of a ruthenium nitride film is polished by, for example, a CMP method to the surface of the insulating film 4 made of a oxidized film. The abrasive is used, for example, as an abrasive containing abrasive particles composed of a planer (oxidized planer). When the insulating film 42 made of a tantalum nitride film is polished, the insulating film 4A made of an aluminum oxide film functions as a polishing stopper layer. As a result, the memory element 3 is in a state of being embedded by the insulating film 42 made of the Shihua 10 nitride film. In other words, a state in which the insulating film 42 made of a tantalum nitride film is filled between the plurality of memory elements 30 is formed. On the element 30, the insulating film 4 made of an aluminum oxide film is exposed. The height of the upper surface of the insulating film 4 made of an aluminum oxide film existing on the memory element 3 is equal to the height of the upper surface of the insulating film 42 made of the tantalum nitride film (see Fig. 7). Next, the photoresist film 50 is entirely formed by spin coating. Next, the opening portion 52 for forming the via hole 48 is formed by the photolithography technique on the photo-reactive film 5'. Next, 'the photoresist film 5 is used as a mask, and the insulating film 40 composed of the aluminum oxide film 20 is used as an etching stopper film, and is formed by an insulating film 42 made of a tantalum nitride film by, for example, plasma etching. Hole 48 (refer to Figure 7). For example, CF4 gas and helium 2 gas are used as the etching gas. Thereafter, the photoresist film 5 is peeled off. Next, as shown in Fig. 9, an insulating film 44 made of, for example, a ruthenium oxide film having a film thickness of 100 rnn is formed, for example, by a CVD method. Further, as the material β of the insulating film 44, a carbon oxide film (SiOC film) or the like can be used. Next, the photoresist film 54 is entirely formed by a spin coating method. Next, the opening portion 56 for forming the groove 46 and the opening portion 58 for forming the via hole 48 are formed on the photoresist film 54 by photolithography. 5 Next, the photoresist film 54 is used as a mask, and the insulating film 42 made of a tantalum nitride film is used as an etching stopper film, and the trench 46 is formed in the insulating film 44 made of a tantalum oxide film by, for example, plasma etching. (Refer to Figure 1). The length direction of the groove is the vertical direction of the paper of Fig. 10. For example, CF4 gas, CHF3 gas, and helium 2 gas are used as the engraving gas. As shown in Fig. 1, when the pattern of the opening portion 56 for forming the groove 10 46 is displaced in the left-right direction of the paper surface, there is an insulating film 40 which is present not only on the memory element 30 but also covers the memory element 3〇. A part of the side insulating film 40, even a portion of the insulating film 42 formed to be embedded in the memory element 3, is removed. However, the etching rate of the insulating film 4A made of an aluminum oxide film is, for example, about one third of the etching rate of the insulating film 44 made of a tantalum oxide film. Further, the etching rate of the insulating film 42 composed of the tantalum nitride film is, for example, about one-fifth of the speed of the insulating film 44 composed of the tantalum oxide film. Therefore, the insulating film 4A made of an aluminum oxide film and the insulating film 42 made of a tantalum nitride film are not excessively etched in portions other than the memory element 3''. As a result, according to the present embodiment, when the groove 46 for embedding the wiring 32a is formed on the insulating film 44'40, the groove 46 can be surely prevented from reaching the lower electrode 34 and the wiring 28a. Therefore, according to the present embodiment, it is possible to reliably prevent the wiring 32a on the upper layer side from being short-circuited with the lower electrode 34 and the wiring 28a on the lower layer side. Next, for example, a Ti 24 200901442 film having a film thickness of 20 nm and a film having a film thickness of 5 〇 11111 are sequentially formed by, for example, a ruthenium plating method. Next, for example, a w film is formed by, for example, a CVD method. The film thickness of the W film is set to be more than half of the width of the groove 46. Further, an example in which W is used as the material of the wiring 32a and the conductor receptacle 32b has been described, and (10) may be used as the material of the wiring 32a and the conductor socket milk. In the case of using a material as the wiring 32a and the conductor receptacle 32b, a Ta (group) film is formed by, for example, a Wei method. Next, a CU film is formed using, for example, a _^ electric ore method. In this way, it is also possible to use a material called a wiring raft and a conductor socket 32b. Next, the conductive film 10 made of W, Cu or the like is polished by, for example, a CMP method to expose the surface of the insulating film 44. Thereby, the wiring 32a can be embedded in the groove 46. Further, the conductor socket 32b is fitted into the guide hole 48. As described above, according to the present embodiment, with respect to the insulating film 44 forming the trench 46 for embedding the wiring 32a, the insulating film 42 having a very slow etching speed can be formed to be embedded in the memory element 3, and thus When the groove 46 for embedding the wiring 15 32a is formed in the insulating film 44, the groove 46 can be surely prevented from reaching the wiring 34a of the lower electrode 34 and the lower layer side of the memory element 30. Therefore, according to the actual situation, it can be reliably prevented. The wiring 32a on the upper layer side is short-circuited with the lower electrode 34 of the memory element 3A and the wiring 28a of the lower layer side, and the wiring 32a of the upper layer side can be connected to the upper electrode 38 of the memory element 3A. [2nd Embodiment] A semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to Figs. 12 to 17 . Fig. 12 is a cross-sectional view showing the semiconductor device constructed in accordance with the present embodiment. The components that are the same as those of the semiconductor device according to the first embodiment shown in the first to eleventh embodiments, and the method of manufacturing the same, will be denoted by the same reference numerals and will not be described or simplified. According to the embodiment of the present invention, the semiconductor device and the method for fabricating the same are provided in the field of separation from the memory cell region by polishing to remove the insulating film 42a formed of the Shihic nitride film in the field of memory cells. The field* forms a guide hole 4 which reaches the wiring 28a, and the residual (10) is mainly characterized by the magnetic film forming the insulating film 42a. (Semiconductor device) The first half of the conductor device constructed in accordance with the present embodiment will be described using Fig. 12 . As shown in Fig. 12, in the semiconductor substrate region 2, an insulating film 42a made of, for example, a stone nitride film is formed on the semiconductor substrate 10 on which the insulating film 40 made of the oxide film is formed to be embedded in the memory. Element 3〇. In other words, in the memory cell region 2, an insulating film 42& which is composed of a stone nitride film is filled between the plurality of I5 memory cells 30 which are formed on the side surface by an insulating film 4? The surface height of the insulating film 423 composed of the tantalum nitride film becomes lower as it leaves the memory cell region 2. In the field 4 separated from the memory cell region, there is no insulating film 42a composed of a stone nitride film. In other words, in the region other than the memory cell region 2, the insulating film 42a made of a tantalum nitride film is formed with a dish-shaped recess 6?. Since the dishing 6 〇 is formed to be very deep, in the field 4 separated from the memory cell region, the insulating film 42a composed of the ruthenium nitride film does not exist. On the semiconductor substrate 10 on which the insulating film 42a made of a tantalum nitride film or the like is formed, an insulating film made of a ruthenium oxide film is formed. The insulating film 40 made of an oxide film and the insulating film 44 made of a tantalum oxide film are formed with grooves 46 for embedding the wiring 32a. In the field 4 separated from the memory cell region, the via holes 48 reaching the wiring 28b are formed on the insulating films 44, 40. In the memory cell region 2, a 5 wiring 32a made of, for example, Cu, W, or the like is buried in the trench 46. In the field 4 separated from the memory cell region and in the via hole 48, a conductor socket 32b made of, for example, Cu, W or the like is buried. In this way, the semiconductor device constructed in the present embodiment is constructed. As described above, according to the present embodiment, the insulating film 42a composed of the tantalum nitride film is removed in the 10 field 4 which is separated from the memory cell region, and thus the field 4 which is separated from the memory cell domain as will be described later. When the via hole 48 reaching the wiring 28b is formed, it is not necessary to etch the insulating film 42a made of a tantalum nitride film. Therefore, according to the present embodiment, the step of etching the insulating film 42a made of the tantalum nitride film (refer to Fig. 8) can be eliminated, and the cost reduction of the semiconductor device can be improved. (Manufacturing Method of Semiconductor Device) A method of manufacturing a semiconductor device constructed in accordance with the present embodiment will be described below using Figs. 13 to 17 . Fig. 13 through Fig. 17 are sectional views showing the steps of a method of manufacturing a semiconductor device constructed in accordance with the present embodiment. 20 First, from the step of forming the element isolation region 12 of the semiconductor substrate 10 to the step of forming the insulating film 40 made of an aluminum oxide film covering the memory element 30 and the first embodiment shown in the third to sixth figures Since the manufacturing method of the semiconductor device is the same, the description is omitted (see FIG. 13). 8. For example, the CVD method integrally forms, for example, a film thickness of 2 〇〇 nm. 27 200901442 An insulating film 42a composed of a stone nitride film. Next, an insulating film 42a made of a tantalum nitride film is polished by, for example, a C Μ P method and an insulating film 4 made of an aluminum oxide film as a polishing stopper. At this time, in the field 4 separated from the memory cell region, a very deep dish-shaped recess 60 is formed in the insulating film 5a composed of the tantalum nitride film to expose the upper surface of the wiring 28b (refer to Fig. 14). As the abrasive, an abrasive containing, for example, abrasive grains composed of cerium oxide (cerium oxide) is used. When the abrasive is used, the dishing 6 〇 can be formed on the insulating film 42a made of a tantalum nitride film as compared with the case of using the abrasive grains including the planer. Since the dish-shaped recess 6 is formed to be extremely deep, the field 4 separated from the memory cell region is in a state in which the insulating film 42a composed of the tantalum nitride film is not present. Further, even if the polishing pressure is set to be very high, the dishing 6 形成 can be formed to be very deep. Next, as shown in Fig. 15, an insulating film 44 composed of a tantalum oxide film having a film thickness of 100 nm is integrally formed by, for example, a plasma CVD method. Further, as the material of the insulating film 44, a tantalum oxide film (SiOC film) containing carbon may be used. Next, the photoresist film 54 is entirely formed by spin coating. Next, an opening portion 58 for forming the groove 46 and an opening portion 58 for forming the via hole 48 are formed on the photoresist film 54 by photolithography. 20 纟 ' 以 光 以 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖46 (refer to Figure 16). Further, via holes are formed in the insulating films 44 and 4 to reach the wiring. For example, CF4 gas, CHf3 gas, and helium 2 gas are used as the residual gas. In the field separated from the memory cell field 4 28 200901442 There is no insulating film 42a made of a tantalum nitride film, so there is no need to etch the insulating film 42a made of a silicon nitride film (refer to Fig. 8). A via hole 48 reaching the wiring 28b is formed. According to this embodiment, the step of etching the insulating film made of the tantalum nitride film can be saved (see Fig. 8), so that the manufacturing cost of the semiconductor crack can be reduced. Next, for example, a Ti film having a film thickness of 20 nm and a TiN film having a film thickness of 50 nm are sequentially formed by, for example, a ruthenium plating method. Next, for example, a w film is formed by, for example, a CVD method. The film thickness of the W film is set to be more than half of the width of the groove 46. Further, an example in which W is used as the material of the wiring 32a and the conductor socket 32b has been described above, but Cu may be used as the material of the wiring 32a and the conductor socket 32b. When Cu is used as the material of the wiring 32a and the conductor receptacle 32b, a Ta (钽) film is formed by, for example, a bismuth ore method. Next, a Cu film is formed by, for example, a sputtering method and an electroplating method. In this way, cu can also be used as the material of the wiring 32a and the conductor socket 32b. The contactor grinds the conductive film made of W or C^u or the like to the surface of the exposed insulating film 44 by the CMP method. Thereby, the wiring 32a can be embedded in the groove 46. Further, the conductor socket 32b can be embedded in the guide hole 48. As a result, a semiconductor device constructed in accordance with the present embodiment can be manufactured (see Fig. 17). 2. As described above, according to the present embodiment, in the field 4 separated from the memory cell region, it is not necessary to remove the insulating film 4 2 a formed of the tantalum nitride film by polishing, so that it is not necessary to (4) cut nitride. The step (> ', and FIG. 8) of the insulating film 4 2 a forms a via hole correction for reaching the wiring (4). According to the present embodiment, the step of saving the insulating film composed of the film of money ( Referring to FIG. 29 200901442 (Fig. 8), the manufacturing cost of the semiconductor device can be reduced. [Third embodiment] A semiconductor device constructed in accordance with a third embodiment of the present invention will be described with reference to Figs. 18 to 26 Fig. 18 is a cross-sectional view showing a semiconductor device constructed in accordance with the fifth embodiment, and a semiconductor device according to the first or second embodiment shown in Figs. 1 to 17 and The same components as those in the manufacturing method are denoted by the same reference numerals, and the description thereof or the simplification thereof will be omitted. According to the semiconductor device and the method of manufacturing the same according to the embodiment, the insulating film 62 made of a tantalum oxide film is formed and embedded. Memory element 30, due to 矽An insulating film 64 made of a silicon nitride film is formed on the insulating film 62 made of an oxide film, and an insulating film 64 made of a stone oxide film is formed on the memory film 64, and an insulating film made of a stone oxide film is formed on the insulating film 64 made of a silicon nitride film. An insulating film 64 made of a stone-like nitride film is used as a surname blocking layer, and an insulating film 4 composed of a ruthenium oxide film is formed by forming an insulating film 62 made of a ruthenium oxide film to form a trench, and is further removed by etching. The main feature of the trench exposed to the upper electrode 38 of the memory element 3 is exposed in the silicon nitride film in the trench 46. (Semiconductor device) According to the embodiment, the first half of the configuration is described using FIG. According to Fig. 18, an insulating film made of an oxidized film for covering the memory element 30 is formed on the semiconductor substrate 10 on which the memory element 30 is formed, and is formed of an oxidized film. The insulating film semiconductor substrate 1〇30 200901442 is used to embed the memory element 30 to form an insulating film 62 made of, for example, a stone oxide film. In other words, the insulating film 4 made of an aluminum oxide film is formed on the side surface. Memory element 30 An insulating film 62 made of a tantalum oxide film is filled between the upper portion of the insulating film 62 made of a tantalum oxide film, and the insulating film 40 made of an oxide film is used as the polishing stopper layer for polishing. There is no insulating film 62 composed of a tantalum oxide film on the memory element 30. The height of the upper surface of the insulating film 4 formed of an aluminum oxide film on the memory element 30 is on the upper surface of the insulating film 62 composed of a smectite film. When the insulating film 64 made of a tantalum nitride film is etched, the insulating film 62 composed of a tantalum oxide film has a function of 10 as an etching stopper layer. The insulating film 40 made of an aluminum oxide film is oxidized by germanium. An insulating film 64 made of, for example, a stone nitride film is formed on the insulating film 62 made of a film. The insulating film 64 composed of the ruthenium nitride film has a function as a resist layer when etching the insulating film 44 composed of a tantalum oxide film. The insulating film 40 made of an aluminum oxide film, the insulating film 64 made of a tantalum nitride film, and the insulating film 44 made of a tantalum oxide film form a trench 46 for embedding the wiring 32a. As shown in Fig. 18, in the case where the pattern for forming the groove 46 is displaced in the left-right direction of the paper surface, it is known that the insulating film 40 not only exists on the memory element 30 but also covers the insulating film on the side of the memory element 3 A portion 20 of the crucible, even a portion of the insulating film 62 formed to embed the memory element 30, is also etched away. However, the etching rate of the insulating film 62 composed of the tantalum oxide film with respect to the "inscription speed of the insulating film 40 composed of the oxide film" is not significantly faster. Therefore, when the insulating film 40 composed of the oxide film in the trench 46 is etched, the insulating film 62 composed of the iridium oxide film is not etched by the excess 31 200901442. According to this embodiment, when the groove 46 for inserting the wiring 32a is formed, the groove 46 can be surely prevented from reaching the lower electrode 34 and the wiring 28a, and the wiring 32a and the lower electrode 34 and the wiring 28a of the lower layer side can be reliably prevented from being short-circuited. . In the field 4 separated from the memory cell region, the via holes 48 5 reaching the wiring 28b are formed on the insulating films 44, 64, 62, 40. In the groove 46 in which the memory cell region 2 is formed, a wiring 32a composed of, for example, cu, w, or the like is embedded. The plurality of wires 32a are parallel to each other. The length of the wiring 32a is the vertical direction of the paper. In other words, the longitudinal direction of the wiring 32a on the upper layer side and the longitudinal direction of the wiring 28a on the lower layer side are orthogonal to each other (see Fig. 2). Further, in the field 4 separated from the memory cell region, a conductor socket 32b made of, for example, Cu, W or the like is embedded in the via hole 48. Further, a wiring (not shown) and a memory element (not shown) similar to the above-described memory element 3 are formed in the upper portion of the wiring 32a. Further, the conductor receptacle 32b is electrically connected to the wiring provided in the upper layer portion (not shown) through a conductor socket or the like which is not shown in the figure. In this way, the semiconductor device constructed in the present embodiment is constructed. As described above, according to the present embodiment, the insulating film 62 composed of the tantalum oxide film is formed to be embedded in the memory element 30, formed on the insulating film 2 formed of the tantalum oxide film, and formed on the A memory element 30 by the second gas. An insulating film 64 made of a film, an insulating film 44 made of a tantalum oxide film, and an insulating film 64 made of a tantalum nitride film as an etching stopper layer are formed on the insulating film 64 made of a tantalum nitride film. The insulating film 44 made of a tantalum oxide film forms a groove in the insulating film 62 made of a tantalum oxide film, and further removes the film of the upper surface of the exposed memory element 30 by etching the film of the germanium nitride 32 which is exposed in the trench 46. 38 groove 46. When the insulating film 64 made of a tantalum nitride film having the trench 46 is removed by etching, the insulating film 62 composed of the tantalum oxide film has a function as an etching stopper layer, so that the groove 46 does not reach the lower electrode 34 of the memory element 30. Wiring 5 28a with the lower layer side. As described above, according to this embodiment, the wiring 32a on the upper layer side can be prevented from being short-circuited with the wiring 34a on the lower surface of the memory element 30 and the wiring 28a on the lower layer side, and the wiring 32a on the upper layer side can be connected to the upper electrode 38 of the memory element 30. (Manufacturing Method of Semiconductor Device) Next, a method of manufacturing a semiconductor device constructed in accordance with the present embodiment will be described using Figs. 19 to 26 . Fig. 19 through Fig. 26 are sectional views showing the steps of a method of manufacturing a semiconductor device constructed in accordance with the present embodiment. First, from the step of forming the element isolation region 12 of the semiconductor substrate 10 to the step of forming the insulating film 40 made of an aluminum oxide film to cover the memory element 30, the first or second step shown in Figs. 1 to Π Since the manufacturing method of the semiconductor device configured as described above is the same, the description is omitted (see FIG. 19). Next, for example, an insulating film 62 made of a tantalum oxide film having a film thickness of 200 nm is integrally formed by, for example, a plasma CVD method. Next, the insulating film 62 made of a tantalum oxide film is polished by, for example, a C Μ P method to chrome out the surface of the insulating film 40 made of an oxide film. An abrasive containing, for example, abrasive grains composed of cerium (yttria) is used as the abrasive. When the insulating film 62 composed of a ruthenium film is polished, the insulating film 40 composed of an aluminum oxide film has a function as a polishing stopper. As a result, the memory element 3 is formed in an embedded state by the insulating film 62 made of a tantalum oxide film. In other words, a state in which the insulating film 62 made of a tantalum oxide film is filled between the plurality of memory elements 30 is formed. On the other hand, the memory element 30 is in a state in which the insulating film 40 made of an aluminum oxide film is exposed. The height of the upper surface of the insulating film 40 made of alumina crucible on the memory element 3 is equal to the height of the upper surface of the insulating film 62 made of the tantalum oxide film (see Fig. 20). Next, for example, an insulating film 64 made of, for example, a film thickness of 2 〇 nm; Next, the photoresist film 5 is formed entirely by spin coating. The opening portion 58 for forming the via hole 48 is formed in the photoresist film 50 by photolithography. Next, the photoresist film 50 is used as a mask and the insulating film 62 composed of a tantalum oxide film is used as an etching stopper film, and a via hole is formed on the insulating film 64 composed of a tantalum nitride film by, for example, plasma etching ( Refer to Figure 21). For example, CF4 gas and ο? gas are used as the etching gas. Thereafter, the photoresist film is peeled off. Then, as shown in Fig. 22, an insulating film 44 made of, for example, a tantalum oxide film having a film thickness of 100 nm is integrally formed by, for example, a CVD method. Further, as the material of the insulating film 44, a tantalum oxide film (SiOC film) containing carbon or the like can be used. Next, the photoresist film 54 is entirely formed by spin coating. Next, an opening portion 56 for forming the groove 46 and an opening portion 58 for forming the via hole 48 are formed on the photoresist film 54 by photolithography. Next, the photoresist film 54 is used as a mask, and the insulating film 40 made of an aluminum oxide film and the insulating film 42 made of a tantalum nitride film are used as an etching stopper film, and are formed of a tantalum oxide film by, for example, plasma etching. The insulating film 62 made of the insulating film 44 and the tantalum oxide film forms the groove 46 (see FIG. 23). Further, a via hole 48 which reaches the insulating film 4 of the oxidized film of 34 200901442 is formed. For example, CF4 gas, C3 gas, and ο: gas are used as the money engraving gas. In the case where the gas is electrically engraved using the gas of the surname, the insufficiency of the insulating film composed of the oxide film is, for example, 5/3 of the speed of the insulating film 62 composed of the stone oxide film. . Further, the (four) speed of the insulating film 64 composed of the wafer film is, for example, fifteen minutes to the speed of the insulating film 44 composed of the stone oxide film. Therefore, the insulating film 4A composed of the aluminum oxide film and the insulating film 64 composed of the tantalum nitride film are not excessively etched. Next, the photoresist film 54 is used as a mask, and an insulating film 40 composed of an aluminum oxide film 10 and an insulating film 62 composed of a tantalum oxide film are used as an etching stopper layer, and are etched by tantalum nitride by, for example, plasma etching. An insulating film 64 made of a film. Thereby, the tantalum nitride film 64 exposed in the trench 46 can be removed by etching (see the first drawing). CF4 gas and helium 2 gas were used as the etching gas. In the case where plasma etching is performed using the etching gas, the etching rate of the insulating film 40 composed of an aluminum oxide film and the insulating film composed of the tantalum oxide film are formed with respect to the etching rate of the insulating film made of tantalum tantalum nitride. The etching speed of the film 62 is very slow. Therefore, the insulating film 40 composed of the aluminum oxide film and the insulating film 64 composed of the tantalum nitride film are not excessively etched. Next, the photoresist film 54 is used as a mask, and the insulating film 40 made of an aluminum oxide film is etched by, for example, plasma etching. As shown in Fig. 25, in the case where the pattern of the opening portion 56 for forming the groove 46 is shifted in the left-right direction of the paper surface, the insulating film 40 not only existing on the memory element 30 but also the side of the memory element 30 can be known. A portion of the insulating film 4'' or even a part of the insulating film 62 formed to be embedded in the memory element 30 is also inscribed. However, the insulating film 40 composed of the aluminum foil film of 35 200901442 has a thin film thickness, and the etching time can be set to be short, so that the insulating film 4 覆盖 covering the side of the memory element 3 〇 and the memory element 30 are embedded. The formed insulating film 62 is not excessively etched. As described above, according to the present embodiment, when the groove 46 for embedding the wiring 32a is formed, it is possible to surely prevent the groove 46 from reaching the lower electrode 34 and the wiring 28a on the lower layer side. Therefore, according to this embodiment, it is possible to reliably prevent the wiring 32a of the upper layer from being short-circuited with the lower electrode 34 and the wiring 28a of the lower layer side. Thereafter, the photoresist film 54 is punctured. Next, for example, a Ti film having a film thickness of 20 nm and a TiN film having a film thickness of 50 nm are sequentially formed by sputtering, for example. Next, for example, a W 10 film is formed by, for example, a CVD method. The film thickness of the W film is set to be more than half of the width of the groove 46. Further, an example in which W is used as the material of the wiring 32a and the conductor socket 32b has been described above, but Cu may be used as the material of the wiring 32a and the conductor socket 32b. When Cu is used as the material of the wiring 32a and the conductor receptacle 32b, a Ta (钽) film is formed by sputtering, for example. Next, a Cu film is formed using, for example, a sputtering method and a 15 plating method. In this way, Cu can also be used as the material of the wiring 32a and the conductor socket 32b. Next, the conductive film is polished by the CMP method to expose the surface of the insulating film 44. Thereby, the wiring 32a can be embedded in the groove 46 (refer to Fig. 26). Further, the conductor socket 32b can be embedded in the guide hole 48. 20 Thus, the semiconductor device constructed in the present embodiment is constructed. As described above, according to the present embodiment, the insulating film 62 composed of the tantalum oxide film is formed to be embedded in the memory element 30, and the tantalum nitride is formed on the insulating film 62 composed of the tantalum oxide film and the memory element 3? An insulating film 64 made of a film, an insulating film 44 made of a tantalum oxide film 36 200901442, and an insulating film 64 made of a tantalum nitride film as an etching stopper layer are etched on the insulating film 64 made of a tantalum nitride film. The insulating film 44 made of a tantalum oxide film forms a groove in the insulating film 46 made of a tantalum oxide film, and further removes the insulating film 64 made of a stone nitride film exposed in the trench 46 to form an exposed memory. A groove 46 of the upper electrode 5 of the element 30. When the insulating film 64 made of a tantalum nitride film having the trench 46 is removed by etching, the insulating film 62 composed of the tantalum oxide film has a function as an etching stopper layer, so that the trench 46 does not reach the lower electrode of the memory element 3 34 and the wiring 28a on the lower layer side. According to this embodiment, it is possible to prevent the wiring 32a on the upper layer side from being short-circuited with the lower electrode 34 of the memory element 30 and the wiring 10a on the lower layer side, and the wiring 32a on the upper layer side can be connected to the upper portion of the memory element 3 Electrode 38. [Modification embodiment] The present invention is not limited to the above embodiment, and may be various morphological changes. For example, the above-described embodiment has been described using an example in which a stone etching film is used as the material of the insulating film, and a stone oxide film is used as the material of the insulating film 44. However, the material and insulating film of the insulating film 42 are called The materials are not limited to these films. It is possible to appropriately use materials having different characteristics of the surname as the materials of the insulating crucible 42 and the insulating film 44. 2 〇 film. It can be used as a material for insulating and cutting materials which can be used as a function of the anti-blocking layer when the insulation is squashed. That is, it is possible to use the insulating lining w_# material 37 200901442, and the above-described embodiment using the yttrium oxide material as the insulating film 4 as the insulating material 64, and the insulating (four) material and The insulating film 44 is described as an example, but it is. It is possible to appropriately (b) the characteristics of each other without being limited to the materials of the films 5 and 44. The material is used as the insulating film 64. In the above embodiment, an example of using a material of the stone oxide film ::=_ is ??? It is the village material of these films H) and 62 which are different from each other by the silking characteristics.材 材 材 作为 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 However, since the lower H-side upper electrode 38 of the phylum is formed as a polishing stopper layer, when the insulating film 42 is polished, the upper portion (4) of the memory element 3G is significantly removed by polishing. Further, the insulating film 4 made of an aluminum oxide film has a function as a barrier film to prevent diffusion of hydrogen and moisture. When the insulating film 40 having a function as a barrier film is not formed, the oxide of the resistive memory layer 36 constituting the memory element 30 is reduced by hydrogen or the like to deteriorate the electrical characteristics. Therefore, it is preferable to form the insulating film 40 from the viewpoint of providing a semiconductor device 20 having high reliability. Industrial Applicability The semiconductor device and the method of manufacturing the same according to the present invention are useful for a semiconductor device having a memory element and a method of manufacturing the same.

Brief Description of Cag Type 3 38 200901442 The first diagram is a cross-sectional view of a semiconductor device constructed not according to the first embodiment of the present invention. The second diagram is a perspective view of a portion of a semiconductor device constructed not according to the third embodiment of the present invention. 5 is a cross-sectional view (No. 1) of a method of manufacturing a semiconductor device according to the first embodiment of the present invention. Fig. 4 is a cross-sectional view (second part) of a method of manufacturing a semiconductor device constructed in accordance with a first embodiment of the present invention. Fig. 5 is a cross-sectional view (third) of a method of manufacturing a semiconductor device 10 constructed in accordance with a third embodiment of the present invention. Figure 6 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device constructed in accordance with a first embodiment of the present invention. Fig. 7 is a cross-sectional view (fifth) of a method of manufacturing a semiconductor device constructed in accordance with a first embodiment of the present invention. Fig. 8 is a cross-sectional view showing the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention (the sixth). Fig. 9 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device constructed in accordance with a third embodiment of the present invention. Fig. 10 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention (the eighth). Fig. 11 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device constructed in accordance with a third embodiment of the present invention. Figure 12 is a cross-sectional view showing a semiconductor device constructed in accordance with a second embodiment of the present invention. 39 200901442 Fig. 13 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Fig. 14 is a cross-sectional view showing the steps of the method of manufacturing the body device according to the second embodiment of the present invention. Fig. 15 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. A cross-sectional view (fourth) of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Figure 17 is a cross-sectional view (fifth) of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Figure 18 is a cross-sectional view showing a semiconductor device constructed in accordance with a third embodiment of the present invention. Fig. 19 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Fig. 2 is a cross-sectional view showing the steps of the manufacturing method of the semiconductor I according to the third embodiment of the present invention. Figure 21 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Figure 22 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention (fourth). Figure 23 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Figure 24 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. 40 200901442 Fig. 25 is a cross-sectional view showing the steps of the method of manufacturing the semiconductor device according to the third embodiment of the present invention (the seventh). Figure 26 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. 5 Fig. 27 is a perspective view showing a semiconductor device of the prior art. Fig. 28 (a) and (b) are cross-sectional views showing the steps of a manufacturing method in which a conventionally proposed method is applied to a conventional semiconductor device. Fig. 29 (a) and (b) are sectional views (part 1) showing a method of manufacturing an etching stopper film for a conventional semiconductor device. 10 Fig. 30 is a cross-sectional view showing the steps of a method of manufacturing an etching stopper film for a semiconductor device of the prior art. [Description of main component symbols] 2: Memory cell area 26a, 26b... Conductor socket 4... Fields 28a, 28b from the memory cell field pitch... Wiring 10... Semiconductor substrate 30···Memory element, resistive memory element 12... Separation field 32a... Wiring 13a, 13b... Element field 32b... Conductor socket 14a, 14b... Gate electrode 34. Lower electrode 16a to 16d... Source/polar diffusion layer 36... Resistive memory layer 18a, 18b... 38: upper electrode 20: interlayer insulating film 40: insulating film, aluminum oxide film 22a, 22b, ..., via hole 42, 42a, insulating film, germanium nitride film 24a, 24b, trench 44, insulating film,矽Oxide film 41 200901442 46...groove 128...wiring 48...via 130···memory element, resistive memory element 50...light anti-reagent film 132...wiring 52...opening 134...lower electrode 54...light anti-money film 136...Resistive memory layer 56... Opening portion 138: Upper electrode 58... Opening portion 140: Insulating film, Alumina film 60... Disc-shaped recess 144... Insulating film, germanium oxide film 62... Insulating film, germanium oxide film 146... Ditch 64···Insulating film, niobium nitrogen 154 ... optical film anti-Syrian film semiconductor substrate 156 ... 110 ... 120 ... opening 126 ... interlayer insulating film conductor of the receptacle 42

Claims (1)

200901442 X. Patent Application Range: 1. A method of manufacturing a semiconductor device, comprising: a first step of forming a first wiring on a semiconductor substrate; and a second step of forming a memory element on the first wiring; a third step of forming a first insulating film for embedding the memory element on the semiconductor substrate; and a fourth step of forming a difference from the first insulating film on the first insulating film and the memory element a second insulating film having etching characteristics; and a fifth step of forming the first insulating film as an etching stopper layer, and forming a trench for exposing the upper portion of the memory element on the second insulating film by etching the second insulating film And in the sixth step, the second wiring is embedded in the groove. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the third step further comprises the step of forming the first insulating film covering the memory element of the first fifteenth memory on the semiconductor substrate, and polishing the foregoing 1 Step of insulating film surface layer portion. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: forming, on the semiconductor substrate in a field separate from a predetermined field in which the memory element is formed, in the first step, In the third step, the third wiring is formed of the same conductive film, and the first insulating film is polished to remove the first insulating film on the third wiring, and the second insulating film is formed in the fourth step. The third wiring of the first 43 200901442 is also covered. In the fifth step, the via hole reaching the third wiring is formed in the second insulating film, and the via hole is inserted into the conductor socket in the sixth step. 5. The method of manufacturing the semiconductor device of claim 1, further comprising: after the second step and before the third step, further comprising forming the first insulating film to cover the memory element The third insulating film having different polishing characteristics, the third step further includes a step of forming the first insulating film on the third insulating film, and polishing the first insulating film by using the third insulating film as a polishing stopper layer a step of exposing the insulating film to the upper surface of the third insulating film on the memory element, and forming a trench for exposing the upper portion of the memory element by etching the second insulating film and the third insulating film in the sixth step The second insulating film and the third insulating film. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the first insulating film is a tantalum nitride film, and the second insulating film is a tantalum oxide film. The method of manufacturing a semiconductor device according to claim 4, wherein the third insulating film is an aluminum oxide film. 7. A method of manufacturing a semiconductor device, comprising: a first step of forming a first wiring on a semiconductor substrate; and a second step of forming a memory element on the first wiring; 44 200901442 third step Forming a first insulating film for embedding the memory element on the semiconductor substrate; and fourth step of forming a second insulating film having different etching characteristics from the first insulating film on the first insulating film and the memory element [5] The fifth step is to form a third insulating film having different etching characteristics from the second insulating film on the second insulating film; and in the sixth step, the second insulating film is used as an etching stopper layer, and the etching is performed by etching The third insulating film forms a groove in the third insulating film. In the seventh step, the first insulating film is etched as an etching stopper film and exposed to the second insulating film of the groove to form the exposed memory. The groove in the upper portion of the element; and the eighth step is to insert the second wire into the groove. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising: 15 after the second step and before the third step, further comprising forming the first insulating film to cover the memory element In the step of forming the fourth insulating film having different polishing characteristics, the third step further includes a step of forming the first insulating film on the fourth insulating film, and polishing the first one by using the fourth insulating film as a polishing stopper layer a step of exposing the insulating film to the upper surface of the fourth insulating film on the memory element, and sequentially etching the second insulating film and the fourth insulating film in the seventh step to form the exposed upper portion of the memory element ditch. 9. The method of manufacturing a semiconductor device according to claim 7 or 8, wherein the first insulating film is a tantalum oxide film, the second insulating film is a tantalum nitride film, and the third insulating film is tantalum. Oxide film. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the fourth insulating film is an aluminum oxide film. The method of manufacturing a semiconductor device according to the first or seventh aspect of the invention, wherein the length direction of the second wiring is orthogonal to a direction of a length direction of the first wiring. 12. The method of manufacturing a semiconductor device according to claim 1 or 7, wherein the memory element is a memory layer of the lower electrode and the upper electrode. 13. A semiconductor device comprising: a first wiring formed on a semiconductor substrate; a memory element formed on the first wiring; and a first insulating film formed by embedding the memory element a semiconductor substrate; the second insulating film is formed on the first insulating film and has different etching characteristics from the first insulating film; and the second wiring is embedded in a trench formed in the second insulating film, And connected to the aforementioned memory element. The semiconductor device of claim 13, further comprising: the third wiring formed on the semiconductor substrate in a field separate from the field of forming the memory element, and having the same conductive film as the first wiring The first insulating film is not present on the third wiring, and the second insulating film is also present on the third wiring, and the semiconductor device further includes the second insulating film and is connected to the first 3 wiring conductor socket. 15. The semiconductor device of claim 13 or 14, further comprising a fifth insulating film formed to cover the memory element and having different polishing characteristics from the first insulating film. 16. The semiconductor device of claim 15, wherein the third insulating film is made of a material that prevents hydrogen or moisture from diffusing. 17. A semiconductor device comprising: 10 a first wiring formed on a semiconductor substrate; a memory element formed on the first wiring; and a first insulating film formed by embedding the memory element In the semiconductor substrate, the second insulating film is formed on the first insulating film and has different etching characteristics from the first insulating film; and the third insulating film is formed on the second insulating film, and The second insulating film has different etching characteristics; and the second wiring is embedded in a groove formed in the second insulating film and the third insulating film, and is connected to the memory element. The semiconductor device of claim 17, further comprising a fourth insulating film formed to cover the memory element and having different polishing characteristics from the first insulating film. 19. The semiconductor device of claim 18, wherein the fourth insulating film is made of a material that prevents diffusion of hydrogen or moisture. The semiconductor device according to claim 13 or 17, wherein the longitudinal direction of the second wiring is orthogonal to a direction of a longitudinal direction of the first wiring. 48