TW200837898A - Methods of forming spacer patterns using assist layer for high density semiconductor devices - Google Patents

Abstract

High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Description

200837898 IX. Description of the Invention: TECHNICAL FIELD Embodiments of the present disclosure are directed to a high density semiconductor device such as a non-volatile memory, and a method of forming the same. Cross-reference the following application and incorporate it in its entirety by reference:

U.S. Patent Application No. _______ [Agency File Number" by James Kai et al., "Spacer Patterns Using Assist Layer for _ High Density Semiconductor Devices" SAND-01187US1], the case was applied on the same day. [Prior Art] In most integrated circuit applications, there is a constant pressure to shrink the substrate area required to perform various integrated circuit functions. For example, semiconductor memory devices and fabrication processes have thus evolved continuously to meet the need to increase the amount of digital data that can be stored in a given area of a germanium substrate. These φ requirements stem from the need to increase the storage capacity of a given size memory card and other types of packages, or to increase both capacity and size. Electrically erasable programmable read only memory (EEPROM) (including flash-EEPROM) and electrically programmable read-only memory (EPROM) are among the most popular non-volatile semiconductor memories. A popular flash EEPROM architecture utilizes an N AND array having a plurality of memory cell strings connected between individual bit lines and a common source line via one or more select transistors. Figure 1 is a top view showing a single NAND string, and Figure 2 is its equivalent circuit. The NAND string depicted in Figures 1 and 2 includes four transistors 100, 102, 104, and 106 sandwiched between a first select gate 120 and a second select gate 122 in series 128354.doc 200837898. Select gate 120 connects the NAND string to the bit line via bit line contact 126. The select gate 122 connects the NAND string to the common source line via the source line contact 128. Each of the transistors 100, 102, 104, and 106 includes a control gate and a floating gate. For example, the transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. It should be noted that although Figures 1 and 2 show four memory cells in a NAND string, the use of four transistors is only provided as an example. A NAND string can have fewer than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, or more. The charge storage elements of current flash EEPROM arrays are the most common conductive floating gates typically formed of doped polysilicon materials. Another type of memory cell that can be used in a flash EEPROM system utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. This unit is described in the paper by Chan et al., HA True Single-Transistor Oxide-Nitride in IEEE Electron Device Lettei*s (European March 3rd, EDL-8, pp. 93-95). -Oxide EEPROM Device". Three layers of yttrium oxide, tantalum nitride and yttrium oxide ("ONO") 128354.doc 200837898 The dielectric is sandwiched between the conductive control gate and the semiconducting substrate above the memory cell channel. Between the surfaces. The cells are programmed by injecting electrons from the cell channels into the nitride, where the electrons are trapped and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a determinable manner. The cell is erased by injecting a thermal hole into the nitride. See also EEE J〇urnal 〇f (5) (4) April, 4th issue, Vol. 26, pp. 497 5〇i). Also in the version of "A 1-Mb EEPROM With M〇N〇s Mem〇ry CeU Such as

Semiconductor Disk ADDlicati^«»» 砝^ , PPiiCatlon , which describes a similar unit configured in a split gate configuration in which a doped polysilicon gate extends over a portion of the memory cell channel An independent selection transistor is formed. A typical non-volatile flash matrix is divided into discrete cell blocks that are removed by the cell. That is, the block contains a minimum number of cells that can be erased as an erase unit, but can be divided by a block of 16 or more in a single-erase operation. Each _ block usually stores one or more data pages, one of which includes the minimum number of units that are subject to basic stylization and reading units while being subjected to data stylization and read operations, but may be in a single or one fall. Stylize or read one - ', _ _ _, sector size cut: the parent page usually stores one or more sizes defined by the host system. An example is a user of a 512-bit group that follows a fe soap built with a disk drive plus a certain number of bits of the user's resource block and "has the location of the user data" The sector of the additional information of the group. The demand for the relative density of the φ > tn heart has been increased, and the manufacturing table 枉匕>Beinjin is reduced. Thunder ~ Zone 娀) Widgets (such as the gate and channel minimum feature size of the transistor. For example, Eliyahou PWi's title 128354.doc 200837898 is "Flash Memory Cell Arrays Having Dual Control Gates"

U.S. Patent No. 6,8 8, 8, 5 5, to Per Memory Cell Charge Storage Element, describes a process for utilizing spacing to achieve a corresponding length of component length and less than the minimum boundable lithography feature size. Such reductions and other considerations increase the need for precision in the manufacturing process and the integrity of the resulting material. SUMMARY OF THE INVENTION [0001] A high density semiconductor device and method of fabricating the same are provided in accordance with one or more embodiments. For forming circuit elements having reduced feature sizes, which in some cases are smaller than the minimum lithographically resolvable element size of the process used. Forming intervals that serve as one for use at the intervals An etchant that etches one or more layers to form one or more circuit elements. An intervening layer having a material composition substantially similar to the spacer material is provided over a dielectric layer and an insulating sacrificial layer such as tantalum nitride When etching the sacrificial layer, the intervening layer acts as an etch stop layer to avoid damage and reduce the size of the underlying dielectric layer. Matching material compositions provide improved adhesion to the spacing, thereby improving the rigidity and integrity of the gap. Other features, aspects, and objectives of the disclosed techniques are available from the review of the book, the patents, and the scope of the patent application. Embodiments The embodiments according to the present disclosure can be used for the formation of many types of high density semiconductor devices. Space and corresponding formation techniques are provided to reduce the size of the fabricated components. Although not so limited, the described techniques can be achieved A feature size smaller than the minimum lithography of the process used to resolve the size of the component. This can be used to facilitate the high density formation of many types of components in the fabrication of integrated semiconductor devices. Various types of NAND flash memory architectures are presented. Features and Techniques It should be understood from the disclosure provided that the implementation of the disclosed technology is not so limited. By way of non-limiting example, embodiments in accordance with the present disclosure may provide for the fabrication of a wide range of semiconductor devices, including But not limited to) logic arrays, volatile memory arrays including SRAM and DRAM, and packages Non-volatile memory arrays including NOR and NAND architectures.

3 is a three-dimensional block diagram of two exemplary NAND strings 302 and 304 that can be fabricated as part of a larger flash memory array. Although Figure 3 depicts four memory cells on string 3〇2 and string 304, more than four or fewer than four memory cells can be used. Figure 3 further depicts the well 326 below the p-well 32, the direction of the NAND string, and the direction of the word line perpendicular to the nand string or bit line direction. The p-type substrate below the well 336 is not shown in FIG. In one embodiment, the control gate forms a word line. A continuous layer of conductive layer 336 is formed that is uniform across the word lines to provide a common word line or control gate for each device on the word line. The individual control gate layers 336 that form a single word line in a plurality of memory cells in a column are depicted in FIG. In this case I, it can be considered that this layer forms a control gate for the parent eta-hidden unit at the point where the layer overlaps the corresponding floating gate layer 332. In other embodiments, individual control gates can be formed and then interconnected by independently formed word lines. When fabricating NAND-based non-volatile memory systems (including NAND strings as depicted in Figure 3), it is important in the direction of the word line between adjacent strings (such as the string 302 and 304). Provide electrical isolation. In the example depicted in Figure 3, the 〇 string 〇2 is separated from the NAND string 304 by the open region or gap 3〇6. In a typical NAND configuration, the dielectric material is formed at 128354.doc -11 - 200837898 = 4: between hard strings and possibly at the location of the open region 306. 1, a second plan view to illustrate a NAND array that can be fabricated in accordance with an embodiment. . one eight. The main component of the body is 7 years old. It consists of five NAND strings 21·25 that are connected in series, and three floating gates are displayed in the string. String 21 includes floating gates 27, 28, 29, string 22 includes net moving gates 30, 31, 32 'string 23 includes floating gates 33, %, %, string 24 includes floating gates 36, %, and strings 25 Includes floating gates (4), 40 and 41. For the sake of easy explanation, only the small rectangles of 15 memory cells are illustrated.

Array: The actual implementation of this array typically involves forming millions of these s-resonant units of thousands of NAND strings, each string typically having "one," or more memory cells. It should be understood that the memory array is positioned over - or a plurality of well regions contained within the common substrate to allow the local substrate potential of the memory array to be electrically controlled independently of the common substrate potential. The use of the substrate for a memory array of electrical Ba bodies may include the examination of such well regions. Each of the NAND strings 21-25 includes two select transistors (one at each end of the string) to controllably connect the strings to different bits in the global bit line BL0_BL4 The line is between the reference potential Vs that is typically provided at the common source line. Vs is typically grounded during reading, but a small positive value can be used during programming to assist in minimizing leakage across the source selection transistor. Voltage VssL is applied to respective source select gates 43-47 to control the connection of one of its respective memory cell strings 21_25 to the common source line. The other ends of the strings 2 1 - 25 are connected to the respective bit lines BL0 - BL4 via respective dipole selection transistors by a voltage vDSL applied to the drain selection gate 49 · 53. The row control circuit described below applies a voltage to each bit line representing the particular material to be written, or to 128354.doc -12-200837898 to sense the corresponding string or memory during the item fetch or setup operation The electrical current of the body unit. The selection transistor includes a respective source region 55_64 and a drain region 65_74 at the surface of the semiconductor substrate during surgery. The St. NAND array includes a control gate (word) line extending across a plurality of strings over a column of floating gates with a suitable insulating dielectric layer therebetween. The tight coupling between the control gate and the floating gate is required to minimize the control gate required to raise the coupled floating gate to the voltage level necessary to program and read its state. Electric. A control gate (word) line is used for each column of the floating gate. In order to fabricate an array having floating gates and control gates that are self-aligned in the y-direction (long along the length of the string), the control gate is typically used as a mask to form a floating gate, which then has The same size as the control gate in the y direction. In the NAND array presented below, the control gate (word) lines 81_84 are placed between the floating gates rather than on top of them. Each control gate line extends across a plurality of memory cell strings and is capacitively capacitively on both sides via a suitable insulating dielectric such as a multilayer oxide-nitride oxide (〇N〇) Face to the floating gate. The external coupling region of the jaw is known by using the side wall regions on both sides of the floating interpole. The floating gate can be made thicker (higher) than usual to increase the coupling area and then the control gate between them is at least as thick as the floating gate to utilize the additional coupling area. The advantage is that the handle a region can be controlled independently of the coupling region of the floating gate and the substrate with a large degree of weight, and even when the coupling region of the n-word moving idle electrode and the substrate is reduced in the future reduction period of the device size Lead to the high coupling ratio required. The principles, devices, and techniques disclosed below may also be used with more conventional NAND architectures having word lines positioned above the floating gates 128354.doc • 13-200837898. In the examples described below, the two control gate lines replace a single sub-line of a conventional NAND array. For example, a word line that may extend across the columns of floating gates 27, 30, 33, 36, and 39 in a conventional array is replaced by two control gate lines 81 and 82 (WL0 and WL1). Similarly, a word line that may typically extend across the columns of floating gates 28, 31, 34, 37, and 40 is replaced by two control gate lines 82 and 83 (WL1 and WL2). The control line 81_84 is elongated in the X direction across the array and separated in the 7 direction by the length of the floating gate and the thickness of the dielectric layer therebetween. Although the size of the memory floating gate is usually as small as the size allowed by photolithography in the X and y dimensions, the channel length (y size) of the selected transistors 43·47 and 49-53 is usually slightly larger than the minimum. The feature size is such that it ensures effective blocking of all conduction including leakage when a maximum voltage is applied across it. 5 and FIGS. 6A-6I depict the fabrication of a sigma knives of an exemplary nand memory according to an embodiment of the present invention, which includes two words in each column of the floating gate = ° depicting memory at various steps of the fabrication process A small portion of the array is selected as part of the larger process. The explanation of the principles disclosed is concise and omitted for various other steps known to those skilled in the art. It should be understood that - he can make revisions to the disclosed process. Figure 5 depicts an orthogonal cross-sectional view taken along line Β in the X direction of a memory cell column extending across a plurality of strings as depicted in Figure 4. Figure 7 depicts the orthogonal cross-section of the memory cell string along the line Α.Α in the 丫 direction. It should be noted that in the tree of Figure 6A, the substrate and well regions are not illustrated. Depending on the particular implementation of the ash V, I, one or more wells (e.g., Mitsui) are typically shaped as 128354.doc • 14-200837898 in the substrate 402. After implanting and associated annealing of the well for doping the substrate, a tunneling dielectric material layer 602 is formed on the surface 4 of the substrate. Different materials can be used for layer 6〇2, but oxygen cut (Si〇2)f is often grown on surface 4〇1 to form a tunneling oxide having a thickness of about 8 nm. Also used in known chemical vapor deposition (CVD) processes, metal organic CVD processes, physical vapor phase • M (PVD) processes, atomic layer deposition (ALD) processes, thermal, oxidation processes, or another suitable The process is to form a dielectric layer. Next, the first layer 604 of doped polysilicon is typically formed over at least the area of the array by low pressure chemical vapor deposition (LPCVD), but its subtraction can be used. The floating gate will be formed by this first polycrystalline layer. Different thicknesses of the first polycrystalline layer can be formed. For example, a thickness in the range of 5 〇 nm to 20 〇 nm can be used in one embodiment. In many NAND devices, this thickness is thicker than the usual poly-polycrystalline layer, and thus the floating gate formed later is thicker than the floating closed-pole of many conventional devices. Other Embodiments Other materials may be utilized to form the charge storage region. • A thin liner 606 of ruthenium dioxide is then formed on top of the polysilicon layer: according to various embodiments, different thicknesses can be used for the oxide profile. In a real case, the oxidized stone is deposited to form a high temperature oxide, (H: 0: thin liner. Other materials can be used in other implementations. Formed on the layer 7 The oxide or other (d) uses the money as a mask when forming individual floating gates or other charge storage regions. The sacrificial layer of nitride (8_4) is then deposited to a thickness generally between _(iv) and m. A cap is formed on top of the nitride layer for the remaining exposed nitride, oxide lining, polycrystalline stone, and etched 128354.doc -15-200837898 ^ two stacked strips in the π direction It spans the substrate (4) and is separated at a: usually, the separation in the χ direction is a small pitch size by the reticle forming. It is also preferable to make the width of the strip equal to: distance. (4) Anisotropic The surface 401 of the substrate 402 between the strips is exposed.

The next series of steps provides electrical isolation between the resulting rows of floating gates. Shallow trench isolation (STI) is used in one embodiment by anisotropically (d) exposed substrate surfaces to form trenches 97·1〇〇 (Fig. 5) that are elongated in the x-direction and Positioned in the 乂 direction between the polysilicon/dielectric stacking strips. These trenches can be left to the depth of the concealed nm. A lightly applied dose can be used to implant the exposed 7 surface area to locally increase the field oxide threshold voltage as needed. A thick oxide layer is then deposited over the entire formation to completely fill the space between the trenches and the polysilicon/dielectric stacked strips. Chemical impurities (CMP) are used to remove excess oxide over the stacked strips. The relatively flat surface then exists across the thick oxide (10) and oxide liner strips 606. As is well known in the art, high temperature annealing can be employed to mitigate the mechanical stresses in the germanium isolation trenches and to densify the thick oxides in such trenches. The trench isolates adjacent rows of memory cells from their respective active regions of the substrate to define individual NAND strings. Various techniques for forming isolation trenches can be used. It is possible to form an array without using shallow trench isolation, for example, by forming a thick dielectric isolation over the germanium surface rather than forming a thick dielectric isolation in the trenches etched into it. The LOCOS or SWAMI technique as previously described can be used in the embodiment. In the case of the babe, the isolation trench can be formed before the floating gate and/or the dielectric compliant 128354.doc -16-200837898. In one embodiment, a deep self-aligned trench is formed, as described in the following patent application: Jack H. Yuan filed on November 23, 2004, titled "SELF-ALIGNED TRENCH FILLING WITH HIGH COUPLING RATIO&quot U.S. Patent Application Serial No. 10/996,030; and U.S. Patent Application Serial No. 1/, filed on Oct. 14, 2005, the entire disclosure of which is incorporated herein by reference. 25, 3, 86, the entire disclosure of which is hereby incorporated by reference in its entirety, the entire entire entire entire entire entire entire entire entire portion A second sacrificial layer 610 of tantalum nitride (Si3N4) is formed on the undoped polysilicon layer 608. Different thicknesses of the nitride layer 610 can be used. For example, in one embodiment, the nitride is deposited to a thickness between 80 nm and 110 nm. FIG. 6A depicts portions of a memory array after formation of intervening layer 608 and nitride layer 610. In one embodiment, the undoped polysilicon layer 608 and the nitride layer 610 are formed prior to etching the surface of the substrate to form a shallow isolation trench, rather than after etching the surface of the substrate as described above. The undoped polysilicon layer 608 can serve as an etch stop layer during a later fabrication step. In addition, the undoped polysilicon will provide a stable basis for the subsequent formation of polysilicon spacers for forming individual floating gate regions. The material composition of layer 608 is selected to provide sufficient adhesion for such thinly formed spaces. The use of matching materials for the spacers and layers 608 provides a dual function: providing an etch stop as part of the spacer formation and providing a matching surface to promote adhesion of the spacers. Providing sufficient spacing between the spacer and the underlying layer 128354.doc -17-200837898 Adhesion is of increasing importance because the spacing is continuously created with a thinner size and an increased aspect ratio. In addition, the use of the same or similar materials for the spacing and intervening layers can contribute to the stress between the different membranes. If layers of different materials are used, the different materials will have different coefficients of thermal expansion. Different thermal coefficients can cause stress at the interface of different materials. When the same or similar materials are used in accordance with one or more embodiments as provided herein, matching the thermal coefficient can reduce stress at the interface of the material. In conventional trench fabrication processes, no additional etch stop layer gates have been provided that are formed directly on the surface temperature oxide layer 606 or on other dielectric layers provided over the conductive gate regions 604. Simply forming a polysilicon on the oxide layer 6〇6 may not provide sufficient adhesion to support the subsequently formed spacer. These thin spaces may substantially fall or fail after the formation and removal of the directional support (e.g., nitride 61()) as part of the manufacturing process. Other combinations of materials may also have insufficient adhesive properties and, therefore, do not provide adequate rigidity and integrity for manufacture. Moreover, when the additional polysilicon layer 608 is not used, the photoresist process may not terminate exactly at the upper surface of the oxide layer 606 when the oxide layer is exposed during subsequent etching of the nitride layer 61. This can damage the oxide such that unwanted growth can occur during subsequent manufacturing steps. In addition, a memory singularity change can also occur when the unintentional etch of the oxide liner 606 ultimately results in a poor change in the thickness of the tunnel oxide layer 602. For example, variations in thickness can affect the thresholding of the resulting memory cells. The characterization, erasing, and reading of memory cells can all be affected by changes in the characteristics of individual memory cells.

128354.doc -18- 200837898 In Fig. A·61, the 'intervention layer 608 and the spacer layer... are all formed of undoped polycrystalline glaze. Different materials may be used in other embodiments. By way of example, a nitride intervening layer 6〇8 is used in a case having a nitrogen (tetra) spacer layer 618: for example. In this embodiment, the sacrificial nitride layer 610 can be replaced by a dioxide dioxide 〇

A mask is formed over the nitride layer 61G to begin forming individual floating gate regions 4 for the array. The reticle may be formed by a photoresist strip 615 formed over the bottom & reflective coating (BARC) 616, the strip being formed: extending in the X direction and having a minimum resolvable element size by lithography in the y direction The determined width and spacing. FIG. 6B depicts a portion of the memory array along line A-A after formation of photoresist strip 615 and BARC 616. In one embodiment, the photoresist has a thickness of about 210 nm and the BARC has a thickness of about 9 Å nm2. The nitride layer 6 is etched by using a photoresist as a mask, resulting in an array having nitride strips 611, 612, 613 and 614 as shown in Fig. 6C. The polysilicon layer 608 acts as a surname termination layer when the nitride layer 610 is etched as described above. This is different from the more conventional manufacturing processes that do not use the intervening layer 608 that provides termination for the nitride remnant process. Since the etching is inherently uncontrollable to some extent, inadvertent surnames and damage to the HTO layer 606 can occur in such cases, thereby having the deleterious effects previously described. In the present disclosure, polysilicon 608 is highly resistant to nitride etching processes. A suitable process for etching the nitride layer 610 can be used to abruptly terminate the etch when the polysilicon layer 608 is reached. The selectivity to nitride will be terminated after the polycrystalline stone is reached, thereby reducing or eliminating the thickness variation of layer 606 128354.doc •19-200837898, which can ultimately result in tunneling oxide layer 6〇 2 thickness changes. In addition, damage to the HT layer 6 〇 6 and/or size reduction of the ht 〇 layer 6 〇 6 can be avoided. The integrity of the oxide layer can be maintained throughout the formation of the floating gate as described below by providing a ><1> entry between the oxide layer 6?6 and the sacrificial nitride. The photoresist layer 615 and the BARC layer 616 are removed in a subsequent embodiment using a combination of 〇2 plasma ashing followed by a wet chemical etch. Piranha oxidation or other cleaning processes can be used to remove residual photoresist and other organic materials from the wafer surface. Figure 6D shows a portion of the memory array after the photoresist is removed to expose the upper surface of the nitride layer 61. The width of the resulting strip can be made smaller than the width of the reticle strip by lateral undercutting or overetching. The resulting relatively thick nitride strip 610 extends in the x-direction across the polysilicon layer 6〇8 and the isolation oxide formed in the trenches 97-100. The etching step is further controlled so as not to remove excess isolating oxide between the polysilicon strips 604 (regions 97-100 in Figure 5) extending in the y-direction. The next series of steps form an interval that is later used as a reticle to form individual charge storage regions. An isotopic deposition process, such as low pressure chemical vapor deposition (LPCVD), is used to form a polycrystalline germanium isoform 618. The isomorphous deposition process forms a polysilicon layer having a substantially uniform thickness on both the side portions and the top portions of the nitride strips 611-614. Figure 6E depicts a portion of the memory array after deposition of the polysilicon layer 61 8 . Figure 6F depicts the memory array after etching the polysilicon layer to form individual polysilicon spacers 62 〇 634. A dry etch process (e.g., reactive ion etch) is used in an embodiment to etch 128354.doc -20-200837898 polycrystalline spine before the nitride strip 611_614 is reached. The deposited polycrystalline τ τ # is used to determine the length L of the interval, which in turn determines the length of the singular gate as described later, which is significantly smaller than the small width of the field used to form the structure. The width W of the nitride strip and the length L of the spacer are smaller than the spacing of the 多 、 登 登 登 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿 沿The spacing of the resulting floating gates in the y direction. The optional μ annealing process can be performed after the interval of the polycrystalline stone. A reactive ion etch that can be used to open the > p-bend = virtual u state open y can damage the polycrystalline sidewalls. This can result in a backup for this & this

The unwanted etching of the damaged polysilicon during the π double 隹 subsequent chaotic removal step. Annealing the exposed polysilicon prevents undesirable defects. Wet etching is used to remove the nitride strips 611-614 after forming the individual spaces 616. The wet etch will leave the polysilicon spacers above the polysilicon etch stop layer 608. As previously described, the etch stop layer provides adhesion and support for the narrow and yet spaced spacing created by previous processes. The figure depicts a portion of the memory array after etching to remove the nitride strip. After removing the nitride strips 6 11 - 614, the combined pass process is used to form individual floating gate regions. Chemical non-selective etching is first used to remove portions of intervening layer 608 and oxide liner layer 606 between and outside of spaces 620-634. Non-selective etching also removes the polysilicon spacer. After passing through the thin oxide layer 606 and completely remnant, the selective etching for the polycrystalline spine is used to etch the polycrystalline fracture layer 6 04. Figure 6A depicts individual floating gate regions resulting from the applied combination etch, wherein polysilicon spacers 620-634 are formed over the polysilicon etch stop layer. The profile of 128354.doc -21 - 200837898 is achieved relative to the unused matching (relative to the spacer composition). The vertical profile of the floating gate regions 640, 642, 644, 646, 648, 650, 652 and 654 is improved. . Conventional processes for forming spacers on top of the oxide liner tend to have the spacers taper inwardly away from the surface of the substrate. In addition to providing adhesion and bucking for the spaces 620-634, the intervening layer can act as an etch stop to reduce the etching of the HTO liner layer 606, thus providing a more vertical profile for the spacing. As illustrated in Figure 6H, portions of the thin oxide liner layer 606 over each floating gate region have substantially the same thickness as the thickness of the original HT layer. In conventional processes, it is possible that the thickness of the oxide liner may be poorly reduced by etching the nitride layer 61 0 . After the polycrystalline spine is formed to form a floating gate region, source and drain ion implantation can be performed using a floating gate and an oxide liner as a mask, as shown in FIG. Various ranges of n+ ion implant doses can be used, for example, from 5E13 to 1E15. The implanted region 660-672 between the floating gates 640-654 is the result of ion implantation. The inter-gate dielectric 660 is then deposited and etched. The dielectric between the gates is often 0N0, but other materials can be used. The iso-form process can be used to provide a substantially constant thickness of the inter-gate dielectric relative to the upper surface and sidewalls of the floating gate regions 640-654. A second doped polysilicon layer is then deposited over the array by LPCVD to contact the dielectric layer 660 to fill the gap between the floating gates. Excess polycrystalline germanium is removed to the top oxide layer of tantalum or to the upper surface of thin oxide liner layer 606 by CMp or anisotropic etch back. An additional polysilicon etch step can be performed to ensure that the polysilicon is not shorted between word lines and sufficiently separated to form individual word lines 680-692, as illustrated in FIG. Individual word lines 680-692 form a control gate for the memory cell. As described in the earlier description of 128,354. doc -22-200837898, the specific embodiment of the towel described in Figures 6A-6I provides two control gates at each side of the floating pole, rather than as in the traditional wealth Provided above in the memory array. Various post-processes can be performed to end the fabrication of the array. For example, a passivation dielectric layer can be deposited, followed by metal conductive lines and vias along the length to connect the line and source regions and the drain regions at the ends of the memory strings, and form control along the length Gate line. As mentioned first, the formation of shallow trenches or other isolated regions can be performed at different stages of the fabrication process. In one embodiment, the control gate layer is deposited and etched to form a word line prior to etching the previously formed floating gate layer. The floating gate layer is then etched to form individual floating gates. After patterning and forming the control gate and floating gate, an isolation trench can be formed at the end of the process. FIG. 7 depicts an illustrative structure of a five-body array 702 that can be fabricated using one or more embodiments of the disclosed technology. As an example, a NAND flash EEPR0M that is divided into 1,024 blocks is described. The data stored in each block can be erased at the same time. In one embodiment, the block is the smallest unit of cells that are simultaneously erased. In this example, there are 8, 5 12 rows in each block' which are divided into even rows and odd rows. The bit lines are also divided into even bit lines (BLE) and odd bit lines (BL0). Figure 7 shows four memory cells connected in series to form a NAND string. Although four cells are not included in each NAND string, more than four or less than four (e.g., 16, 32, or another number) may be used. One terminal of the NAND string is connected to the phase 128354.doc -23-200837898 via bit line via a first select transistor (also referred to as select gate) SGd, and the other terminal is connected via a second select transistor SGS To 0 source. During the reading and stylizing operations of the memory cells of one embodiment, 4,256 memory cells are simultaneously selected. The selected memory cells have the same word line (e.g., WL2-i) and the same type of bit line (e.g., even bit lines). Therefore, the 532-bit data can be read or programmed simultaneously. The data of these 532-bit tuples that are simultaneously read or programmed form a logical page. Thus, in this example, one block can store at least eight pages. When each memory unit stores two bits of data (e.g., multi-level cells), one block stores 16 pages. In another embodiment, a memory array is formed that utilizes all bit line architectures such that each bit line within the block (including bit lines adjacent in the X direction) is simultaneously selected. Figure 8 is a block diagram of one embodiment of a flash memory system that can be used to implement one or more embodiments of the present disclosure. Other systems and implementations are also available. The memory cell array 802 is controlled by a row control circuit 804, a column control circuit 806, a c source control circuit 81A, and a p-well control circuit 808. The row control circuit 8〇4 is connected to the bit line of the memory cell array 802 for reading data stored in the memory cell, for determining the state of the memory cell during the stylizing operation' and for controlling the bit The potential level of the line is to promote or inhibit stylization and erasure. Column control circuit 806 is coupled to the word line to select one of the word lines, apply a read voltage, apply a program voltage in combination with a bit line potential level controlled by row control circuit 8, and apply an erase voltage. The c source control circuit 810 controls a common source line (labeled "C source) in Figure 7). The P well control circuit 808 controls the p-well voltage. 128354.doc -24- 200837898 The data stored in the brother memory unit is read by the row control circuit 8G4 and output to the external I/O line via the data wheel input/output buffer 812. The program data to be stored in the memory unit is via external I/O. The line is input to the data input/output buffer 8 i 2 and transferred to the row control 1 channel 8 〇 4. The external j / 〇 line is connected to the controller 81 8. The instruction data for controlling the flash memory device is input. To the controller 818. The instruction data informs the flash memory what operation is requested. The input finger 7 is transferred to the state machine 81 that is part of the control circuit 815. The state machine 8 16 controls the row control circuit 8〇4, the column control circuit (9) $, ^ source control 810 well control circuit 808 and data input/output buffer 812. State machine 816 can also output status data of flash memory, such as READY/BUSY or PASS/FAIL. To the host system or can be connected to the host system , for example, a personal computer, a digital camera, or a personal digital assistant, etc., which communicates with a host computer, such as a host device for storing data to the memory array 8〇2 or the self-recording k-body array 802. The data is provided or received. Controller 818 converts the instructions into command signals that can be interpreted and executed by instruction circuitry 814 as part of control circuitry 8.5. Instruction circuitry 814 is in communication with state machine 816. Controller 818 Typically, a buffer memory is provided for user data that is written to or read from the memory array. An exemplary memory system includes an integrated circuit including controllers 8 and 8 and respective One or more integrated circuit chips including a memory array and associated control, input/output, and state machine circuits. There is a system for integrating the tracking and controller circuits of the system 128354.doc -25-200837898 into one or A plurality of integrated circuit wafers. The memory system can be embedded as part of the host (4), or can be included in a memory card that is removably inserted into the host system (or

He encapsulates). # + _ ^ t T ^ , including the entire memory system (for example, including the controller) ^ only includes a memory array having a peripheral circuit (having a control device or control power scattered into the host). Because &, the controller can be embedded in the host or included in the removable memory system.

The above detailed description is presented for the purpose of A and the description. It is not intended to be exhaustive or to limit the scope of the subject matter claimed herein. The described examples of the conjugate are chosen to best explain the principles of the disclosed technology and its practical applications in order to enable those skilled in the art to <RTIgt; Use this technology. It is intended that the scope of the invention be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a NAND string. 2 is an equivalent circuit diagram of the NAND string depicted in FIG. 1. 3 is a three-dimensional illustration of one of four NAND strings that can be fabricated in accordance with an embodiment. 4 is a plan view of a portion of a NAND flash memory array in accordance with an embodiment. Figure 5 is an orthogonal cross-sectional view taken along line β·β of a portion of the flash memory array depicted in Figure 4. Figures 6A-6I depict a portion of the memory array of Figure 4 at various steps of 128354.doc -26-200837898 during a fabrication process, in accordance with an embodiment. FIG. 7 depicts an exemplary organization of a memory array in accordance with an embodiment. 8 is a block diagram of an exemplary memory system that can be used to implement one embodiment of the disclosed technology.

[Main component symbol description] 21 NAND string 22 NAND string 23 NAND string 24 NAND string 25 NAND string 27 floating gate 28 floating gate 29 floating gate 30 floating gate 31 floating gate 32 floating gate 33 floating gate 34 Floating Gate 35 Floating Gate 36 Floating Gate 37 Floating Gate 38 Floating Gate 39 Floating Gate 40 Floating Gate 128354.doc -27- 200837898 41 Floating Gate 43 Source Select Gate 44 Source Select Gate 45 Source Select Gate 46 Source Select Gate 47 Source Select Gate 55 Source Region 56 Source Region 57 Source Region 5 8 Source Region 59 Source Region 60 Source Region 61 Source Region 62 Source Region 63 Source region 64 Source region 65 Datum region 66 Well region 67 Bungee region 68 Bungee region 69 Bungee region 70 Bungee region 71 Bungee region 72 Bungee region 128354.doc ^ 28 - 200837898 73 &gt ; and the polar region 74 &gt; and the polar region 82 control gate line 83 control gate line 84 control gate line - 97 trench 98 trench 99 trench 100 trench / transistor 100C G control gate 100FG floating gate 102 transistor 102CG control gate 102FG floating gate 104 transistor • 104CG control gate 104FG floating gate 106 transistor « 106CG control gate 106FG floating gate 120 first selection gate 122 Second selection gate 126 bit line contact 128 source line contact 128354.doc •29- 200837898

302 NAND string 3 04 NAND string 3 06 gap 320 P well 326 N well 332 floating gate layer 336 control gate layer 702 memory cell array 802 memory cell array 804 row control circuit 806 column control circuit 808 P well control circuit 810 c source control circuit 812 data input/output buffer 814 instruction circuit 815 control circuit 816 state machine 818 controller BLO bit line BL1 bit line BL2 bit line BL3 bit line BL4 bit line BLE 〇 even bit line 128354.doc -30- 200837898

BLEi even bit line ble2 even bit line BLE4255 even bit line BLO 〇 odd bit line BL〇! odd bit line blo2 odd bit line BLO4255 odd bit line SGD first select transistor SGD-i select transistor SGS second select transistor SGS_i select transistor WLO word line WL1 word line WL2 word line WL3 word line WL0_i word line WL1 one i word line WL2_i word line WL3 i word line 128354.doc -31 -

Claims (1)

200837898 Patent Application Range: 1. A method of forming an integrated semiconductor device, comprising: providing a first dielectric layer over a substrate; providing a first conductive layer over the first dielectric layer; Providing an intervening layer over a conductive layer; providing a spacer having a set of sacrificial material strips extending in a -first direction; and a sidewall of the sacrificial material strip forming a space above the :: a material composition substantially similar to the intervening layer; and etching the strips, the intervening layer and the plurality of electrically conductive gate regions of the first conductive layer. θ ^ 2· The method of claim 1, wherein: (d) comprises a material composition of one of the strips of the sacrificial material, wherein the material composition of the strips is substantially different. The material layer of the interposer layer, the interposer layer provides a momentary termination for the selective money engraving; and the surname includes using the spacers as a mask for the first conductive layer At least one additional etching process. 3. The method of claim 1, wherein: the integrated semiconductor device comprises a non-volatile memory array; the plurality of conductive gate regions are floating gates of the memory array; and the method further comprises: Providing a second dielectric layer over the floating gate, and providing a single-control open-pole for each of the floating gates, 128354.doc 200837898 dielectric layer and a corresponding floating gate The control gate is separated by the first upper surface of the first. 4. The method of claim 1, wherein: the integrated semiconductor device comprises a -&amp; i ^ non-volatile memory array; the plurality of conductive gate regions are externally π X 〇 The gate, the (four) interpole has a substantially vertical extension in the first direction: and is spaced apart from the adjacent floating closed-pole knife at a distance therebetween in a second direction, and The method further includes: providing a second dielectric layer along the sidewalls of the floating gates, and providing the at least partially occupying between the adjacent floating gates; the interval f controlling the gates of the control gates The poles are separated from the sidewalls of the floating gates by the second dielectric layer. 5. The method of claim 4, wherein the non-volatile memory is listed as one of the flash memory cells. 6. The method of claim 4, wherein providing the second dielectric layer comprises depositing three layers of oxides, nitrides, and oxides. 7. The method of claim 4, further comprising: forming a liner layer over the first conductive layer prior to providing the intervening layer, wherein the intervening layer is formed over the liner layer. 8. The method of claim 7, wherein: the spacers are formed of polysilicon; the intervening layer is formed of polysilicon; the liner layer is formed of an oxide dielectric; and 128354.doc 200837898 the sacrificial material is A nitride dielectric. 9. The method of claim 8, wherein: the first conductive layer is formed of doped polysilicon; the spacers are formed of undoped polysilicon; and the intervening layer is formed of undoped polysilicon. 10. The method of claim 1, wherein: the intervening layer has a substantially similar coefficient of thermal expansion as the intervals. 128354.doc