TW200745945A - Processor core and method for managing branch misprediction in an out-order processor pipeline - Google Patents

Processor core and method for managing branch misprediction in an out-order processor pipeline

Info

Publication number
TW200745945A
TW200745945A TW095140051A TW95140051A TW200745945A TW 200745945 A TW200745945 A TW 200745945A TW 095140051 A TW095140051 A TW 095140051A TW 95140051 A TW95140051 A TW 95140051A TW 200745945 A TW200745945 A TW 200745945A
Authority
TW
Taiwan
Prior art keywords
instruction
pipeline
processor
misprediction
processor core
Prior art date
Application number
TW095140051A
Other languages
English (en)
Chinese (zh)
Inventor
Karagada Ramarao Kishore
Kjeld Svendsen
Vidya Rajagopalan
Maria Ukanwa
Original Assignee
Mips Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/261,655 external-priority patent/US7734901B2/en
Priority claimed from US11/261,654 external-priority patent/US7711934B2/en
Application filed by Mips Tech Inc filed Critical Mips Tech Inc
Publication of TW200745945A publication Critical patent/TW200745945A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
TW095140051A 2005-10-31 2006-10-30 Processor core and method for managing branch misprediction in an out-order processor pipeline TW200745945A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/261,655 US7734901B2 (en) 2005-10-31 2005-10-31 Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US11/261,654 US7711934B2 (en) 2005-10-31 2005-10-31 Processor core and method for managing branch misprediction in an out-of-order processor pipeline

Publications (1)

Publication Number Publication Date
TW200745945A true TW200745945A (en) 2007-12-16

Family

ID=38267515

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095140051A TW200745945A (en) 2005-10-31 2006-10-30 Processor core and method for managing branch misprediction in an out-order processor pipeline

Country Status (2)

Country Link
TW (1) TW200745945A (fr)
WO (1) WO2007084202A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI470546B (zh) * 2009-02-12 2015-01-21 Via Tech Inc 微處理器、管線式微處理器、快速執行條件分支指令之方法、以及解析第一或第二類別條件分支指令之方法
TWI549054B (zh) * 2011-12-28 2016-09-11 英特爾股份有限公司 用於分支預測錯誤之賦能及去能第二跳越執行單元之技術
CN115617402A (zh) * 2022-11-18 2023-01-17 北京数渡信息科技有限公司 一种适用于通用处理器的解耦合分支预测方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6079014A (en) * 1993-12-02 2000-06-20 Intel Corporation Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US6108769A (en) * 1996-05-17 2000-08-22 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US6760835B1 (en) * 2000-11-22 2004-07-06 Lsi Logic Corporation Instruction branch mispredict streaming

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI470546B (zh) * 2009-02-12 2015-01-21 Via Tech Inc 微處理器、管線式微處理器、快速執行條件分支指令之方法、以及解析第一或第二類別條件分支指令之方法
TWI549054B (zh) * 2011-12-28 2016-09-11 英特爾股份有限公司 用於分支預測錯誤之賦能及去能第二跳越執行單元之技術
CN115617402A (zh) * 2022-11-18 2023-01-17 北京数渡信息科技有限公司 一种适用于通用处理器的解耦合分支预测方法及装置

Also Published As

Publication number Publication date
WO2007084202A2 (fr) 2007-07-26
WO2007084202A3 (fr) 2007-10-04

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