TW200715491A - The arrangement of conductive pads on grid array package and on circuit board - Google Patents

The arrangement of conductive pads on grid array package and on circuit board

Info

Publication number
TW200715491A
TW200715491A TW095108773A TW95108773A TW200715491A TW 200715491 A TW200715491 A TW 200715491A TW 095108773 A TW095108773 A TW 095108773A TW 95108773 A TW95108773 A TW 95108773A TW 200715491 A TW200715491 A TW 200715491A
Authority
TW
Taiwan
Prior art keywords
conductive pads
grid array
pitch
array package
circuit board
Prior art date
Application number
TW095108773A
Other languages
English (en)
Other versions
TWI309455B (en
Inventor
Wen-Yuan Chang
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW200715491A publication Critical patent/TW200715491A/zh
Application granted granted Critical
Publication of TWI309455B publication Critical patent/TWI309455B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114Pad being close to via, but not surrounding the via
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09218Conductive traces
    • H05K2201/09227Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/094Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
TW095108773A 2005-10-11 2006-03-15 The arrangement of conductive pads on grid array package and on circuit board TWI309455B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/246,281 US7372169B2 (en) 2005-10-11 2005-10-11 Arrangement of conductive pads on grid array package and on circuit board

Publications (2)

Publication Number Publication Date
TW200715491A true TW200715491A (en) 2007-04-16
TWI309455B TWI309455B (en) 2009-05-01

Family

ID=37861842

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095108773A TWI309455B (en) 2005-10-11 2006-03-15 The arrangement of conductive pads on grid array package and on circuit board

Country Status (3)

Country Link
US (1) US7372169B2 (zh)
CN (1) CN2879422Y (zh)
TW (1) TWI309455B (zh)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098531A (ja) * 2006-10-14 2008-04-24 Funai Electric Co Ltd 半導体集積回路装置
JP4474431B2 (ja) * 2007-03-26 2010-06-02 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージおよび該製造方法
CN101515018B (zh) * 2008-02-22 2011-09-21 纬创资通股份有限公司 电路检测回路及制造使用方法
JP2010123602A (ja) * 2008-11-17 2010-06-03 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
EP2503594A1 (en) * 2011-03-21 2012-09-26 Dialog Semiconductor GmbH Signal routing optimized IC package ball/pad layout
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8659140B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
WO2013052080A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Stub minimization for multi-die wirebond assemblies with orthogonal windows
US8610260B2 (en) 2011-10-03 2013-12-17 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
KR101945334B1 (ko) 2011-10-03 2019-02-07 인벤사스 코포레이션 창이 없는 와이어 본드 어셈블리를 위한 스터브 최소화
US8436457B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8441111B2 (en) 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
EP2764544A1 (en) 2011-10-03 2014-08-13 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8513813B2 (en) 2011-10-03 2013-08-20 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8659143B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
WO2013052544A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Stub minimization with terminal grids offset from center of package
CN103117260A (zh) * 2011-11-16 2013-05-22 复旦大学 一种焊点结构
US8674505B2 (en) * 2012-01-05 2014-03-18 Texas Instruments Incorporated Integrated circuit packaging with ball grid array having differential pitch to enhance thermal performance
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US9425139B2 (en) * 2012-09-12 2016-08-23 Marvell World Trade Ltd. Dual row quad flat no-lead semiconductor package
DE102012222679A1 (de) * 2012-12-10 2014-06-12 Robert Bosch Gmbh Verfahren zur Herstellung eines Schaltmoduls und eines zugehörigen Gittermoduls sowie ein zugehöriges Gittermodul und korrespondierende elektronische Baugruppe
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
KR20160000953A (ko) 2014-06-25 2016-01-06 삼성전자주식회사 기판 및 반도체 패키지의 제조방법
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9633965B2 (en) 2014-08-08 2017-04-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method of the same
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US10177107B2 (en) * 2016-08-01 2019-01-08 Xilinx, Inc. Heterogeneous ball pattern package
US20180375239A1 (en) * 2017-06-23 2018-12-27 Microsoft Technology Licensing, Llc Liquid metal circuit element connector
CN109509737B (zh) * 2017-09-15 2020-09-08 瑞昱半导体股份有限公司 电子封装构件以及电路布局结构
DE102017218273B4 (de) * 2017-10-12 2022-05-12 Vitesco Technologies GmbH Halbleiterbaugruppe
KR102269743B1 (ko) * 2019-03-05 2021-06-25 매그나칩 반도체 유한회사 이너 리드 패턴 그룹을 포함하는 반도체 패키지 및 그 방법
US11508683B2 (en) * 2019-06-17 2022-11-22 Western Digital Technologies, Inc. Semiconductor device with die bumps aligned with substrate balls
TWI736979B (zh) * 2019-09-12 2021-08-21 啓碁科技股份有限公司 電子裝置及其主機板以及封裝系統模組
CN112638034B (zh) * 2019-09-24 2022-05-27 启碁科技股份有限公司 电子装置及其主机板以及封装系统模块
KR20210108583A (ko) 2020-02-26 2021-09-03 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US20230063343A1 (en) * 2021-08-24 2023-03-02 Texas Instruments Incorporated Multilevel package substrate device with bga pin out and coaxial signal connections
CN114464585B (zh) * 2022-04-12 2022-07-12 飞腾信息技术有限公司 一种半导体基板、半导体器件、集成电路系统和电子设备

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US6858941B2 (en) * 2000-12-07 2005-02-22 International Business Machines Corporation Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array

Also Published As

Publication number Publication date
US20070080456A1 (en) 2007-04-12
TWI309455B (en) 2009-05-01
US7372169B2 (en) 2008-05-13
CN2879422Y (zh) 2007-03-14

Similar Documents

Publication Publication Date Title
TW200715491A (en) The arrangement of conductive pads on grid array package and on circuit board
TW200725824A (en) A package structure with a plurality of chips stacked each other
TW200644187A (en) Semiconductor device and method for manufacturing semiconductor device
TW200723463A (en) Chip package and coreless package substrate thereof
TW200629434A (en) Module structure having an embedded chip
TW200737536A (en) Bendable solid state planar light source, a flexible substrate therefor, and a manufacturing method therewith
TW200640325A (en) Wiring board manufacturing method
TW200627653A (en) Interconnection structure through passive component
TW200627562A (en) Chip electrical connection structure and fabrication method thereof
TW200742004A (en) A method for manufacturing a coreless package substrate
TW200703528A (en) Semiconductor device
WO2008102326A3 (en) In-grid decoupling for ball grid array (bga) devices
TW200731477A (en) Semiconductor package including a semiconductor die having redistributed pads
TW200701436A (en) Semiconductor integrated circuit including a power supply, semiconductor system including a semiconductor integrated circuit, and method of forming a semiconductor integrated circuit
TW200802708A (en) Semiconductor device having carbon nanotube interconnects and method of fabrication
TW200627561A (en) Chip package
TW200744180A (en) Stack structure of circuit board having embedded with semiconductor component
TW200742003A (en) A method for manufacturing a coreless package substrate
TW200743194A (en) Package structure
TW200629997A (en) Thin circuit board
TW200737455A (en) Method for fabricating a metal protecting layer on electrically connecting pad of circuit board
TW200620366A (en) Electronic device having a plurality of conductive beams
TWI263318B (en) An electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts
TW200943518A (en) Systems and methods for ball grid array (BGA) escape routing
TW200723972A (en) Circuit board module and forming method thereof