TW200715106A - Method and electronic device of packet error detection on PCI express bus link - Google Patents

Method and electronic device of packet error detection on PCI express bus link

Info

Publication number
TW200715106A
TW200715106A TW094135678A TW94135678A TW200715106A TW 200715106 A TW200715106 A TW 200715106A TW 094135678 A TW094135678 A TW 094135678A TW 94135678 A TW94135678 A TW 94135678A TW 200715106 A TW200715106 A TW 200715106A
Authority
TW
Taiwan
Prior art keywords
pci express
express bus
electronic device
error detection
bus link
Prior art date
Application number
TW094135678A
Other languages
English (en)
Other versions
TWI290284B (en
Inventor
Tina Hsiao
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW094135678A priority Critical patent/TWI290284B/zh
Priority to US11/382,719 priority patent/US7596155B2/en
Publication of TW200715106A publication Critical patent/TW200715106A/zh
Application granted granted Critical
Publication of TWI290284B publication Critical patent/TWI290284B/zh
Priority to US12/538,322 priority patent/US7929577B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
TW094135678A 2005-10-13 2005-10-13 Method and electronic device of packet error detection on PCI express bus link TWI290284B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW094135678A TWI290284B (en) 2005-10-13 2005-10-13 Method and electronic device of packet error detection on PCI express bus link
US11/382,719 US7596155B2 (en) 2005-10-13 2006-05-11 Method and apparatus for packet error detection
US12/538,322 US7929577B2 (en) 2005-10-13 2009-08-10 Method and apparatus for packet error detection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094135678A TWI290284B (en) 2005-10-13 2005-10-13 Method and electronic device of packet error detection on PCI express bus link

Publications (2)

Publication Number Publication Date
TW200715106A true TW200715106A (en) 2007-04-16
TWI290284B TWI290284B (en) 2007-11-21

Family

ID=38053465

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094135678A TWI290284B (en) 2005-10-13 2005-10-13 Method and electronic device of packet error detection on PCI express bus link

Country Status (2)

Country Link
US (1) US7596155B2 (zh)
TW (1) TWI290284B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7929577B2 (en) * 2005-10-13 2011-04-19 Via Technologies, Inc. Method and apparatus for packet error detection
TWI384810B (zh) * 2009-05-07 2013-02-01 Etron Technology Inc 可節省通用串列匯流排協定中用來儲存封包之記憶體之資料傳輸方法及其裝置
US8832331B2 (en) 2011-08-29 2014-09-09 Ati Technologies Ulc Data modification for device communication channel packets
CN109213102B (zh) * 2018-09-11 2022-01-18 深圳众城卓越科技有限公司 多命令监测方法、装置、计算机设备及存储介质

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761707A (en) * 1996-02-28 1998-06-02 Sun Microsystems, Inc. High speed flexible slave interface for parallel common bus to local cache buffer
US6691192B2 (en) * 2001-08-24 2004-02-10 Intel Corporation Enhanced general input/output architecture and related methods for establishing virtual channels therein
US7246303B2 (en) * 2002-03-25 2007-07-17 Intel Corporation Error detection and recovery of data in striped channels
US7631118B2 (en) * 2003-12-31 2009-12-08 Intel Corporation Lane to lane deskewing via non-data symbol processing for a serial point to point link

Also Published As

Publication number Publication date
US20070116066A1 (en) 2007-05-24
US7596155B2 (en) 2009-09-29
TWI290284B (en) 2007-11-21

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