TW200703013A - Target readiness protocol for contiguous writes - Google Patents
Target readiness protocol for contiguous writesInfo
- Publication number
- TW200703013A TW200703013A TW095124437A TW95124437A TW200703013A TW 200703013 A TW200703013 A TW 200703013A TW 095124437 A TW095124437 A TW 095124437A TW 95124437 A TW95124437 A TW 95124437A TW 200703013 A TW200703013 A TW 200703013A
- Authority
- TW
- Taiwan
- Prior art keywords
- cycle
- asserting
- write
- clock cycle
- asserted
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US69706305P | 2005-07-05 | 2005-07-05 | |
| US11/358,464 US7543094B2 (en) | 2005-07-05 | 2006-02-21 | Target readiness protocol for contiguous write |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200703013A true TW200703013A (en) | 2007-01-16 |
| TWI325539B TWI325539B (en) | 2010-06-01 |
Family
ID=37619538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095124437A TWI325539B (en) | 2005-07-05 | 2006-07-05 | Method for executing contiguous writes, processor and processor bus system |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7543094B2 (zh) |
| EP (1) | EP1760601B1 (zh) |
| CN (1) | CN100403286C (zh) |
| TW (1) | TWI325539B (zh) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9263106B2 (en) * | 2011-10-21 | 2016-02-16 | Nvidia Corporation | Efficient command mapping scheme for short data burst length memory devices |
| WO2014176775A1 (zh) | 2013-05-02 | 2014-11-06 | 华为技术有限公司 | 一种计算机系统、高速外围组件互联端点设备的访问方法、和装置 |
| CN105938461B (zh) * | 2015-07-31 | 2019-02-19 | 杭州迪普科技股份有限公司 | 一种dma数据传输方法、装置以及网络设备 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5237670A (en) * | 1989-01-30 | 1993-08-17 | Alantec, Inc. | Method and apparatus for data transfer between source and destination modules |
| US5426739A (en) * | 1992-03-16 | 1995-06-20 | Opti, Inc. | Local bus - I/O Bus Computer Architecture |
| US5790811A (en) * | 1996-05-17 | 1998-08-04 | Advanced Micro Devices, Inc. | System and method for performing data transfers during PCI idle clock cycles |
| US6336159B1 (en) * | 1997-06-25 | 2002-01-01 | Intel Corporation | Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system |
| US6311245B1 (en) * | 1998-06-05 | 2001-10-30 | Micron Technology, Inc. | Method for time multiplexing a low-speed and a high-speed bus over shared signal lines of a physical bus |
| US6609171B1 (en) * | 1999-12-29 | 2003-08-19 | Intel Corporation | Quad pumped bus architecture and protocol |
-
2006
- 2006-02-21 US US11/358,464 patent/US7543094B2/en active Active
- 2006-03-03 EP EP06251163A patent/EP1760601B1/en active Active
- 2006-07-05 CN CNB2006101013536A patent/CN100403286C/zh active Active
- 2006-07-05 TW TW095124437A patent/TWI325539B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| EP1760601A3 (en) | 2009-09-16 |
| CN100403286C (zh) | 2008-07-16 |
| TWI325539B (en) | 2010-06-01 |
| US7543094B2 (en) | 2009-06-02 |
| EP1760601B1 (en) | 2011-07-06 |
| CN1881193A (zh) | 2006-12-20 |
| EP1760601A2 (en) | 2007-03-07 |
| US20070011376A1 (en) | 2007-01-11 |
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