TW200632658A - High-speed transmission memory module and method - Google Patents

High-speed transmission memory module and method

Info

Publication number
TW200632658A
TW200632658A TW094106572A TW94106572A TW200632658A TW 200632658 A TW200632658 A TW 200632658A TW 094106572 A TW094106572 A TW 094106572A TW 94106572 A TW94106572 A TW 94106572A TW 200632658 A TW200632658 A TW 200632658A
Authority
TW
Taiwan
Prior art keywords
error correction
memory access
speed transmission
direct memory
high
Prior art date
Application number
TW094106572A
Inventor
zheng-min Jiang
li-wei Zhu
Yi-Cheng Hu
Original Assignee
Jtek Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jtek Technology Corp filed Critical Jtek Technology Corp
Priority to TW094106572A priority Critical patent/TW200632658A/en
Publication of TW200632658A publication Critical patent/TW200632658A/en

Links

Abstract

The present invention discloses a high-speed transmission memory module and method. The high-speed transmission method of the present invention is executed between a static memory and a flash memory for transmitting data from the static memory to the flash memory by means of a plurality of buffers so as to achieve a bi-directional high speed transmission mode. The method comprises: setting automatic direct memory access actions of the buffers; activating a direct memory access transmission mode; obtaining an error correction code from an error correction module; completing the direct memory access actions; placing the error correction code in the flash memory; and completing the automatic direct memory access actions of the buffers. The present invention also provides a high speed transmission memory module, which comprises a first buffer, a second buffer, an error correction circuit, a direct memory access unit and a microprocessor. The error correction circuit is electrically connected to the first buffer. The direct memory access unit is electrically connected to the second buffer. The microprocessor is electrically connected to the error correction circuit and the direct memory access unit.
TW094106572A 2005-03-04 2005-03-04 High-speed transmission memory module and method TW200632658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094106572A TW200632658A (en) 2005-03-04 2005-03-04 High-speed transmission memory module and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094106572A TW200632658A (en) 2005-03-04 2005-03-04 High-speed transmission memory module and method

Publications (1)

Publication Number Publication Date
TW200632658A true TW200632658A (en) 2006-09-16

Family

ID=57809233

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094106572A TW200632658A (en) 2005-03-04 2005-03-04 High-speed transmission memory module and method

Country Status (1)

Country Link
TW (1) TW200632658A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI476778B (en) * 2007-08-21 2015-03-11 Samsung Electronics Co Ltd Ecc control circuits, multi-channel memory systems including the same, and related methods of operation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI476778B (en) * 2007-08-21 2015-03-11 Samsung Electronics Co Ltd Ecc control circuits, multi-channel memory systems including the same, and related methods of operation

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