TW200619936A - An apparatus and method for an address generation circuit - Google Patents
An apparatus and method for an address generation circuitInfo
- Publication number
- TW200619936A TW200619936A TW094134057A TW94134057A TW200619936A TW 200619936 A TW200619936 A TW 200619936A TW 094134057 A TW094134057 A TW 094134057A TW 94134057 A TW94134057 A TW 94134057A TW 200619936 A TW200619936 A TW 200619936A
- Authority
- TW
- Taiwan
- Prior art keywords
- carry
- generation circuit
- address generation
- address
- logic
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Complex Calculations (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/956,164 US7380099B2 (en) | 2004-09-30 | 2004-09-30 | Apparatus and method for an address generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200619936A true TW200619936A (en) | 2006-06-16 |
TWI315822B TWI315822B (en) | 2009-10-11 |
Family
ID=35515646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094134057A TWI315822B (en) | 2004-09-30 | 2005-09-29 | An apparatus and method for an address generation circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US7380099B2 (zh) |
CN (1) | CN101027633B (zh) |
TW (1) | TWI315822B (zh) |
WO (1) | WO2006039610A1 (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8078662B2 (en) * | 2006-09-29 | 2011-12-13 | Intel Corporation | Multiplier product generation based on encoded data from addressable location |
US8285971B2 (en) * | 2008-12-16 | 2012-10-09 | International Business Machines Corporation | Block driven computation with an address generation accelerator |
US8327345B2 (en) * | 2008-12-16 | 2012-12-04 | International Business Machines Corporation | Computation table for block computation |
US8407680B2 (en) * | 2008-12-16 | 2013-03-26 | International Business Machines Corporation | Operand data structure for block computation |
US8281106B2 (en) * | 2008-12-16 | 2012-10-02 | International Business Machines Corporation | Specifying an addressing relationship in an operand data structure |
US8458439B2 (en) * | 2008-12-16 | 2013-06-04 | International Business Machines Corporation | Block driven computation using a caching policy specified in an operand data structure |
CN104579363A (zh) * | 2014-12-26 | 2015-04-29 | 复旦大学 | 一种用于Turbo码和LDPC码译码器的地址生成器 |
US20160224319A1 (en) * | 2015-01-30 | 2016-08-04 | Huong Ho | High-speed three-operand n-bit adder |
CN104915177A (zh) * | 2015-05-22 | 2015-09-16 | 浪潮(北京)电子信息产业有限公司 | 一种混合型加法器和高效混合型加法器 |
US9825649B1 (en) | 2016-09-29 | 2017-11-21 | Intel Corporation | Efficient huffman decoder improvements |
US10157277B2 (en) | 2016-10-01 | 2018-12-18 | Intel Corporation | Technologies for object-oriented memory management with extended segmentation |
CN108958703B (zh) * | 2017-05-18 | 2020-11-06 | 龙芯中科技术有限公司 | 加法器 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5508952A (en) | 1993-10-19 | 1996-04-16 | Kantabutra; Vitit | Carry-lookahead/carry-select binary adder |
US5860154A (en) * | 1994-08-02 | 1999-01-12 | Intel Corporation | Method and apparatus for calculating effective memory addresses |
US5898596A (en) | 1996-01-24 | 1999-04-27 | Synopsys, Inc. | Adder which employs both carry look-ahead and carry select techniques |
AU3884100A (en) * | 1999-03-23 | 2000-10-09 | Sony Electronics Inc. | Adder circuit |
US7103863B2 (en) * | 2001-06-08 | 2006-09-05 | Magma Design Automation, Inc. | Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system |
US6807616B1 (en) * | 2001-08-09 | 2004-10-19 | Advanced Micro Devices, Inc. | Memory address checking in a proccesor that support both a segmented and a unsegmented address space |
US7188134B2 (en) * | 2001-09-28 | 2007-03-06 | Intel Corporation | High-performance adder |
US6957245B2 (en) | 2002-01-31 | 2005-10-18 | Sun Microsystems, Inc. | Ultra-fast adder |
US6735682B2 (en) | 2002-03-28 | 2004-05-11 | Intel Corporation | Apparatus and method for address calculation |
-
2004
- 2004-09-30 US US10/956,164 patent/US7380099B2/en not_active Expired - Fee Related
-
2005
- 2005-09-29 TW TW094134057A patent/TWI315822B/zh not_active IP Right Cessation
- 2005-09-30 CN CN200580032351XA patent/CN101027633B/zh not_active Expired - Fee Related
- 2005-09-30 WO PCT/US2005/035401 patent/WO2006039610A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
TWI315822B (en) | 2009-10-11 |
US20060069901A1 (en) | 2006-03-30 |
CN101027633A (zh) | 2007-08-29 |
WO2006039610A1 (en) | 2006-04-13 |
CN101027633B (zh) | 2010-09-29 |
US7380099B2 (en) | 2008-05-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200619936A (en) | An apparatus and method for an address generation circuit | |
Pihl et al. | A multiplier and squarer generator for high performance DSP applications | |
Anitha et al. | A new hybrid multiplieusing Dadda and Wallace method | |
Talsania et al. | A comparative analysis of parallel prefix adders | |
Yagain et al. | Design of high-speed adders for efficient digital design blocks | |
Kandula et al. | Area efficient vlsi architecture for square root carry select adder using zero finding logic | |
Priya et al. | Implementation and comparison of effective area efficient architectures for CSLA | |
Kumawat et al. | Design and comparison of 8× 8 Wallace Tree Multiplier using CMOS and GDI technology | |
Nithya et al. | Design of Delay Efficient Hybrid Adder for High Speed Applications | |
Baba et al. | Design and implementation of advanced modified booth encoding multiplier | |
Sari et al. | Fully combinational 8× 8 bits multiplier using 130 nm technology | |
Narendra et al. | Low power MAC architecture for DSP applications | |
Narendra et al. | Low power compressor based MAC architecture for DSP applications | |
Reddy et al. | Implementation of low power 8-Bit multiplier using gate diffusion input logic | |
Kumar et al. | Comparative research for managing delay in signal processing via multipliers | |
US20070299902A1 (en) | Sparse tree adder | |
Samundiswary et al. | Design and Analysis of CMOS Based DADDA Multiplier | |
US8868634B2 (en) | Method and apparatus for performing multiplication in a processor | |
Kaur et al. | Implementation of modified booth multiplier using pipeline technique on FPGA | |
Hasan et al. | Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator | |
Garg et al. | Area efficient modified booth adder based on sklansky adder | |
Soni et al. | An Enhanced Two-Speed, Radix-4 Multiplier using Spurious Power Suppression Technique | |
Bonatto et al. | Evaluation of Booth's algorithm for implementation in parallel multipliers | |
De Angel et al. | Switching activity in parallel multipliers | |
Bhusare et al. | Fixed-width multiplier with simple compensation bias |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |