TW200307353A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device Download PDF

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Publication number
TW200307353A
TW200307353A TW092100510A TW92100510A TW200307353A TW 200307353 A TW200307353 A TW 200307353A TW 092100510 A TW092100510 A TW 092100510A TW 92100510 A TW92100510 A TW 92100510A TW 200307353 A TW200307353 A TW 200307353A
Authority
TW
Taiwan
Prior art keywords
connecting rod
lead frame
package
cut
light
Prior art date
Application number
TW092100510A
Other languages
English (en)
Other versions
TWI228803B (en
Inventor
Yoshiki Yasuda
Hideya Takakura
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200307353A publication Critical patent/TW200307353A/zh
Application granted granted Critical
Publication of TWI228803B publication Critical patent/TWI228803B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/16Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
    • H01L31/167Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

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200307353 玖、發明說明: 發明背景 [發明所屬之技術領域] 本發明係有關一種用於製造樹脂封裝型半導體裝置之半 、豆用導、泉采,尤指藉由傳遞模塑法形成之半導體裝置及 光結合元件的半導體用導線架。 [先前技術] 一般而言’樹脂封裝型半導體裝置之製程係具備以下步驟 丄將晶片搭載於導線架之步驟;將所搭載的晶片與導線部 電性連接之金屬線接合步驟;金屬線接合後將晶片樹脂封 =傳遞模塑步驟;於傳遞模塑步驟時,將有效防止樹脂 流出的聯結桿部切斷之聯結桿切斷步驟。 力聯結桿切斷步驟中’係以聯結桿切斷模具按壓並固定導線 架’且使用穿孔機將(積存於樹脂封裝與聯結桿部間的空隙 (殘留樹脂)厚毛邊與聯結桿㈣穿(例如,參考 7-221245號公報)。 〒]卞 :::孔考機塑封裝(以下稱作樹脂封裝)造成龜裂等影 機的磨損等’故聯結桿部的形成位置必須離樹脂 六裝.随〜〇.2mm以上。此係考量模塑模具的不吻合或 谷限,而該空隙部分由穿孔機鑿穿。 〆 此外’傳遞模塑步驟中,以模塑模具爽入導 樹脂。此時,為使模塑模具成型+木、、无 聯結桿部間的距離增加而降低 ^封^與 流出,必須對模塑模具施加高壓。不會從聯結桿部 飯而1,需大約數百 82511 200307353 嘴的能量。 雙重傳遞模塑型光結合元件的情況中,由於一次模 塑後將—次聯結桿部切斷,接著,二次模塑後將二次聯社 才于邵切斷’故必須有進行二次聯結桿士刀斷的設備。當炊, 聯結桿邵必須有兩行-次聯結桿部與二次聯結桿部,且各 需有空隙。 圖9為以往之雙重傳遞模塑型处人、, 、偎2 土尤、、、口 口兀件〈楱塑步驟完成 時的構造平面圖,圖1 〇为 ;& 口 ιυ為已凡成 <相對型光結合元件的構 造(代表性構造)縱剖面圖。 換言之,將具有:搭載發光元件17或受光元件18的架頭ua Mlb(圖9未圖示);按固定間隔配置於架頭周邊的複數内部 導線12a、12b ’·對應該等内部導線12a、12b的外部導線"a 、13b;及連接各内部導線12a、12b與各外部導線ua、丄扑 的聯結桿部14a、14b之發光元件側導線架1〇〇a與受光元件側 導線架io〇b重疊配置,以使發光元件17與受光元件18上下 相對。此外,藉由將架頭lla、Ub及配置於架頭周邊之内部 導線12a、12b樹脂模塑,形成樹脂封裝體15。 另外,圖9中的符號3 1係作為重疊兩導線架丨〇〇a、丨〇〇b時 毛位基準的基準孔,其亦是模具内進行安裝時的基準孔。 以往之構造中,考量以穿孔機鑿穿聯結桿部14a、14b時所 4成龜裂等影響或穿孔機的磨損等,故在樹脂封裝體丨5與 各聯結桿部14a、14b間必須確保充分的空隙P1丨㈧丨5 mm〜 〇·2 mm以上)。 此外,由於上下重疊發光元件側導線架丨〇〇a與受光元件側 82511 200307353 導線架100b而使發光元件17與受光元件ι8相對,故如圖9所 示,為使發光元件側導線架l〇〇a的外部導線Ua與受光元件 側導線架l〇〇b的外部導線13b不重疊,而朝水平方向交錯配 置。且為提升實裝密度,形成以相互交錯方式組裝外部導 線13a、13b的狀態。 又’在各外部導線1 3a、1 3b前端及與其相對的各聯結桿部 14a、14b間,必須有防止干擾的空隙p 12。 如此,以往之傳遞模塑步驟中,模塑後以穿孔機將厚毛邊 與聯結桿部鑿穿時,由於必須排除對樹脂封裝造成龜裂等 的影響,故樹脂封裝體15與各聯結桿部14a、14b之間必須確 保无分的空隙P11,此外,由於在各外部導線Ua、i3b前端 及與其相對的各聯結桿部14a、14b間亦必須有防止干擾的空 隙P12,故產生無法提升導線架實裝密度的問題。換言之, 產生平均一個導線架的光結合元件可減少數不多之問題。 此時,只將聯結桿部的成形位置靠近樹脂封裝側時,由於 模塑模具的不吻合或穿孔機的磨損所產生的誤差等,而導 致無法切斷聯結桿部,且聯結桿部產生大毛邊等問題。 又,進行傳遞模塑時,為防止樹脂漏戍等,以高壓加壓機 對模塑模具施加壓力以夾入導線架,並填充樹脂,但高恩 加壓機昂貴,設備t高,0致製造成本增加。 [發明内容] 、本發明係為解決上述問題而提案者,其目的在於提供一牙 :導體用導線架,藉由改變聯結捍部形狀,使聯結桿^ 靠近封裝樹脂,且使用㈣加m機也不會引起樹脂漏戍。 82511 200307353 本發明之半導體用導線架,具有:半導體晶片搭載部、 數内部導線,其按固定間隔配置於半導體晶片搭载^ 、複 邊、外部導線,其對應該等内部導線、及聯結桿部u,並周 接各内邵導線與各外部導線間;該半導體用導線架中直 特徵在於前述聯結桿部係靠近前述模塑封裝側而嗖置,其 使導線架樹脂模塑時,前述聯結桿部與模塑封装(樹又听以 間的空隙為0·07酿〜〇·1贿。此時,與前述聯結=部:裝前) 述模塑封裝側相對的側緣部,於聯結桿切斷時以穿孔2 所穿孔邵分形成缺口部。 根據具有上述特徵之本發明,由於在聯結桿部形成缺 ,故即使聯結㈣靠近樹脂封裝,也可將聯結桿切斷^匕 外,精由聯結桿部靠近樹脂封裝,可提升導線架的實裝参 =再者,藉由聯結桿部靠近樹脂封裝’可 : 的成型壓。如此,由於使 旦 楔八 降低製造成本。 …便宜的加壓機,故可 二’在與則迷聯結桿部的前述模塑封裝則目反側的 更加提升導線架的;=需空_所示空叫而能 有η述:缺口部也可形成俯視半圓弧形。如此,缺口部 此二二少作為導線架鏨穿模具之穿孔機的磨損。 部份,^Γ/切斷時由穿孔機所鑒穿前述聯結桿部的馨穿 形成ν型:部孔可Τ穿方向也 '形成ν型溝部。如此,藉由 ""加減少聯結桿切斷時的毛邊殘留或穿孔 82511 200307353 機的磨損。 再者,取代前述v型溝部,也葬 椁切m“、· 也了藉由共合的貫施,將聯結 杯切辦時抵接穿孔機之前 j述和結样邵的抵接邵分形成比m 、、泉部分薄。如此’可減少 的磨損。 咸^、、“干切㈣毛邊殘留或穿孔機 又,也可將對應於任意模塑封裝的聯結桿部與對應於 該模塑封裝的其他模塑封裝之外料線前端部—體連接。 如此’與相對型之二件導線架重疊的情況相比 升導線架的實裝密度。 知 另外,上述聯結桿部的構造,可使料—次模塑用與二次 模塑用之雙重聯結桿部構造的任一聯結桿部。 入 實施方式 以下參照圖面說明本發明之實施形態。 (實施形態一) 圖1及圖2為本發明之半導體用導線架的實施形態一平面 圖’圖1係顯示發光側導線架與受光側導線架重疊之狀態, 圖2⑷係顯示受光側導線架,圖2(b)係顯示發光側導線架。 以又重傳遞模塑方式製造相對型光結合裝置之方法,係與 圖10所示以往技術的製造方法完全相同。此外,由於其構 造與圖9所示構造相同’故以下之說明中,使用與圖9和圖 10相同的符號進行說明。 在此,簡單說明雙重傳遞模塑方式之相對型光結合裝置的 製造方法。 首先,以銀塗漿等連接發光元件17與受光元件18(參考圖 82511 -10- 200307353 9) ’並將其分別搭載於發光元件側導線架1 〇〇a的架頭11 &與 文光元件侧導線架l〇〇b的架頭m後,以金屬線1〇a、1〇b (參考圖10)連接金屬線部。其次,對發光元件17施以預敷等 後,以上下相對方式配置兩導線架1〇〇a、1〇〇b,並以透光性 樹脂實施一次傳遞模塑。之後,先將一次聯結桿部4al、4Μ 切斷。而圖1中,以虛線表示一次聯結桿部4al、4bl,並顯 示未切斷之狀態。 聯結桿切斷步驟中,一般係以未圖示的聯結桿切斷模具按 壓並固定兩導線架100a、100b,且打下未圖示的穿孔機將樹 脂造成的厚毛邊與聯結桿部4al、4bl鑿穿。之後,同樣地實 施二次傳遞模塑而形成樹脂封裝體15,並切斷二次聯結桿 部4a2、4b2以進行組裝。 本貫施形態一中,係主要說明二次聯結桿部4a2、4b2,但 當然也可使用於一次聯結桿部4al、4bl。 圖1中,靠近樹脂封裝體15形成二次聯結桿部4a2、4b2。 本實施形態一中,考量未圖示的模具不吻合和容限,故靠 近二次聯結桿部4a2、4b2大約〇·07 mm左右。如此 圖9所示空隙pii由以往的〇15 mm〜〇·2 大約縮小一半 為〇·〇7 mm〜〇·;[ mm左右,故可提升發光元件側導線架 及受光元件側導線架1 〇0b的實裝密度。 如此’為了防止二次聯結桿部4a2、4b2靠近樹脂封裝體i 5 而造成聯結桿切斷時的故障,於二次聯結桿部4a2、4b2 一邊 的側緣部,亦即與樹脂封裝體丨5相對的側緣部,在聯結桿 切斷時由穿孔機所鑿穿部分(亦即内部導線丨以、12b的兩側) 82511 -11 - 200307353 形成第一缺口部1。 此外’發光元件側導線架1 〇 〇 a的外部導線1 3 a與受光元件 側導線架l〇〇b的外部導線13b係以為重疊方式朝水平方向 交錯配置,且形成以相互交錯方式組裝的狀態。 因此,本實施形態一中,在第二聯結桿部4a2另一邊的侧 緣部,亦即與樹脂封裝體15相反側的側緣部,分別形成用 以嵌入從鄰接之樹脂封裝體15所延伸出導線架1〇〇|}的各外 部導線13b前端部之第二缺口部2。同樣地,在第二聯結桿 部4b2另一邊的側緣部,亦即與樹脂封裝體15相反側的侧緣 部’分別形成用以嵌入從鄰接之樹脂封裝體丨5所延伸出導 線架100a的各外部導線13a前端部之第二缺口部2。 如此’不需圖9所示的空隙P12,而可提升發光元件側導 線架100a及受光元件側導線架100b的實裝密度。換言之,因 為平均一導線架的光結合元件可減少數增加,故可降低製 造成本。 圖3至圖5顯示第一缺口部1的各種形狀,圖3係缺口形狀為 俯視四角形之例,圖4係俯視半圓弧形之例,圖5係俯視三 角形(V字形)之例。在此,第一缺口部}的形狀為圖4所示俯 視半圓弧形,藉由其具有弧度,可減少作為導線架鑿穿模 具之穿孔機的磨損。 上述實施形態一中,係說明相對型光結合元件的製造方法 ,而下述的實施形態二係說明平面搭載型光結合元件。 (實施形態二) 圖ό係顯示平面搭載型光結合元件的二次傳遞模塑後之狀 82511 -12· 200307353 態。 ,孩平面搭載型光結合元件亦與上述實施形態一所示相對 型光結合it件相同’靠近樹脂封裝體15形成二次聯結桿部 4b2此外,為了防止二次聯結桿部、仆2靠近樹脂 封裝體15而造成聯結桿切斷時的故障,於二次聯結桿部^ 、4b2—邊的侧緣部,亦即與樹脂封裝體^相對的侧緣部, 在聯結桿切斷時由穿孔機所t穿部分(亦即㈣導線 12b的兩側)各形成第一缺口部1。 基本上’上述構造之平面搭載型光結合元件的製造方法與 相T型光結合元件的製造方法相R,但與相對型光結合元 件最大不同處’係在於將受光元件與發光元件搭載於同一( 一個)導線架100c,以進行訊號傳達。 平面搭載型光結合元件中,,由於相對型導線架所需架頭 部的折灣或不必將二件導線架上下相對之背面並無相對,、 故有又光感度差’傳達效率不—致增加等缺點。此外,由 於平面配置,故會限制架頭11a、lib的大小。 从因此,一如圖6所示,本實施形態二中,分別-體連接(圖中 付號3所丁)第—聯結桿部4a2的另—邊側緣部,#即樹脂封 裝體15相對側的側緣部,與鄰接之樹脂封裝體15所延伸出 各外部導線13b前端部;同樣地,分別一體連接㈤中符號*
所示)第=聯結桿部4b2的另一邊側緣部,亦即樹脂封裝體I 相反側的側緣部,I# * 與鄰接心樹脂封裝體15所延伸出各外却 導線13a前端部。 $ 如此, 由於共用第二聯結桿部4a2、4b2與鄰接之樹脂封裝 82511 -13- 200307353 to15所延伸*各外部導線13&、n故可提升導線架⑽。 的實裝密度。換士夕,m τ 、 口 因為平均一導線架的光結合元件可 減少數增加,故可降低製造成本。 (實施形態三) ^ 7和圖8係顯示在上述實施形態—及實施形態二所說明 的第一缺口部1進行形狀改變之例。 換口之圖7中,在聯結桿切斷時由穿孔機所鑿穿聯結桿 部(實施形態-中聯結桿部14a、14b,實施形態二中一次聯 結桿料1、4Μ及二次聯結桿部4a2、4b2)的馨穿部(亦即, 、子應第1缺口 部分的聯結桿部平面),、沿I穿孔機奪穿方 向形成V型溝部5。 如此,藉由形成V型溝部,可更加減少聯結桿切斷時的毛 邊殘留或穿孔機磨損。 此外,圖8中,藉由共合的實施,將聯結桿切斷時由穿孔 機所塞穿聯結桿部(實施形態一中聯結桿部14卜Mb,實施 形態二中一次聯結桿部4al、4bl及二次聯結桿部私2、 的馨穿部(亦即,對應第!缺口部!部分的聯結桿部平面)形成 較導線部分薄(圖中符號6所示)H,(a)係只在對應第】 缺口邵!的部分實施共合之例’⑻係在鄭接之外部導線m 或13b之間全部實施共合之例。 如此,藉由實施共合,可減少聯結桿切%時的毛邊殘留或 穿孔機磨損。 可以各種形式實施 ’解釋並不受其限 本發明在不脫離其精神或主要特徵下, 如此,上述實施例的所有點僅是例示 82511 -14- 200307353 制。本發明之範圍係申請專利範 θ寸〜靶固所不者,不侷限於說明 曰本文”匕外,在申請專利範圍均等範圍的變形或變更, 均為本發明之範圍内者。 另外,本申请案係以日本所提出之特願2〇〇2_〇〇64ι〇號為 基礎而申請,其相關内容在此併入本申請案。又,本說明 曰所引用的各文獻’所有相關内容均具體併人本中請案。 [圖式簡單說明] 圖1為本發明之半導體用導線架的實施形態一平面圖,其 顯示發光側導線架與受光側導線架重疊之狀態。 圖2⑷為受光侧導線架的平面圖,圖2(b)為發光側導線架 的平面圖。 圖3為第一缺口部之缺口形狀一例的部分放大平面圖。 圖4為第一缺口部之缺口形狀其他例的部分放大平面圖。 圖5為第一缺口部之缺口形狀其他例的部分放大平面圖。 圖6為本發明之半導體用導線架的實施形態二平面圖,其 _ π平面搭載型光結合元件的二次傳遞模塑法後之狀態。 圖7(a)為實施形態一及實施形態二所說明之第一缺口部 形狀改變例的部分放大斜視圖,圖7(b)為A_ A線之放大剖 面圖。 圖8(a)、(b)各為實施形態一及實施形態二所說明之第一缺 口部形狀改變其他例的部分剖面圖。 圖9為以往之雙重傳遞模塑型光結合元件之模塑步驟完成 時的構造平面圖。 圖1 〇為已完成之相對型光結合元件構造(代表性構造)的 82511 -15- 200307353 縱剖面圖。 圖式代表符號說明 1 2 5 15 17 18 31 100a 100a 、 100b 、 100c 100b 10a、10b 11a、lib 12a 、 12b 13a 、 13b 14a、14b 4al 、 4bl 4a2 、 4b2 Pll 、 P12 第一缺口部 第二缺口部 V型溝部 樹脂封裝體 發光元件 受光元件 基準孔 發光元件側導線架 導線架 受光元件側導線架 引線 架頭 内部導線 外部導線 聯結桿線 一次聯結桿部 二次聯結桿部 空隙 -16- 82511

Claims (1)

  1. 200307353 拾、申請專利範圍: 1· 一種半導體用導線架,具有:半導體晶片搭載部、複數 内部導線,其按固定間隔配置於半導體晶片搭載部的周 邊、外部導線,其對應該等内部導線、及聯結桿部,其 連接各内邵導線與各外部導線間;其特徵在於 前述聯結桿部係靠近前述模塑封裝側而設置,以使導 線架樹脂模塑時,前述聯結桿部與模塑封裝(樹脂封裝) 間的空隙為0.07 mm〜0.1 mm。 2·如申請專利範圍第丨項之半導體用導線架,其中與前述聯 結桿部的前述模塑封裝側相對的側緣部,於聯結桿切斷 争由穿孔機所鏨穿的部分形成缺口部。 3·如申請專利範圍第丨或2項之半導體用導線架,其中在與 則述聯結桿部的前述模塑封裝側相反側的側緣部,形成 用以嵌入從鄭接之模塑封裝所延伸出各導線前端部之缺 口部。 4·如申請專利範圍第2或3項之半導體用導線架,其中前述 缺口部係形成俯視半圓弧形。 5.=申請專利範圍第2至4項中任一項之半導體用導線架, 在聯結桿切斷時由穿孔機所鑿穿前述聯結桿部的鑿 6 士 15岛,係沿著穿孔機鑿穿方向形成V型溝部。 其申二專利範圍第2至4項中任一項之半導體用導線架, ^ “藉由共合的貫施,將聯結桿切斷時抵接穿孔機之前 7心聯結桿部的抵接部分形成比導線部分薄。 申清專利範圍第1至6項中任一項之半導體用導線架, 82511 200307353 其中將對應於任意模塑封裝的聯結桿部與對應於鄰接該 模塑封裝的其他模塑封裝之外部導線前端部一體連接。 8.如申請專利範圍第1至6項中任一項之半導體用導線架, 其中前述聯結桿部係形成一次模塑用與二次模塑用之雙 重聯結桿部構造。 82511
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547960B2 (en) 2006-05-04 2009-06-16 Everlight Electronics Co., Ltd. Structure of a lead-frame matrix of photoelectron devices

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3872001B2 (ja) * 2002-11-18 2007-01-24 シャープ株式会社 リードフレーム、それを用いた半導体装置の製造方法、それを用いた半導体装置、及び電子機器
JP4369204B2 (ja) * 2003-10-30 2009-11-18 シャープ株式会社 光結合装置用リードフレームの製造方法、この方法により接続されたリードフレーム、およびこのリードフレームを使用した光結合装置の製造方法
US20070085179A1 (en) * 2005-08-08 2007-04-19 Honeywell International Inc. Automotive plastic lead frame sensor
US20070029649A1 (en) * 2005-08-08 2007-02-08 Honeywell International Inc. Plastic lead frame with snap-together circuitry
US7968377B2 (en) * 2005-09-22 2011-06-28 Stats Chippac Ltd. Integrated circuit protruding pad package system
US7943431B2 (en) * 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture
US7977782B2 (en) * 2007-11-07 2011-07-12 Stats Chippac Ltd. Integrated circuit package system with dual connectivity
CN101458366B (zh) * 2007-12-13 2010-12-01 旭丽电子(广州)有限公司 光耦合器导线架料带
JP5217800B2 (ja) 2008-09-03 2013-06-19 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
CN102403298B (zh) * 2010-09-07 2016-06-08 飞思卡尔半导体公司 用于半导体器件的引线框
EP2549531A1 (en) 2011-07-21 2013-01-23 Nxp B.V. Lead frame for semiconductor device
JP2013093418A (ja) * 2011-10-25 2013-05-16 Japan Aviation Electronics Industry Ltd 半導体装置用パッケージの集合体、半導体装置の集合体、半導体装置の製造方法
JP2013197302A (ja) * 2012-03-19 2013-09-30 Toshiba Corp 半導体装置およびその製造方法
US20150268261A1 (en) * 2014-03-18 2015-09-24 Trw Automotive U.S. Llc Circuit mounting apparatus and method using a segmented lead-frame
CN104332451B (zh) * 2014-11-24 2017-02-22 深圳市富美达五金有限公司 一种光耦封装支架

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4026008A (en) * 1972-10-02 1977-05-31 Signetics Corporation Semiconductor lead structure and assembly and method for fabricating same
JPS63115355A (ja) * 1986-11-04 1988-05-19 Matsushita Electric Ind Co Ltd 樹脂封止製品用リ−ドフレ−ム
JPH0595079A (ja) * 1991-10-02 1993-04-16 Ibiden Co Ltd リードフレーム、半導体集積回路搭載用基板及び半導体装置並びにそれらの製造方法
JPH06275764A (ja) * 1993-03-19 1994-09-30 Fujitsu Miyagi Electron:Kk リードフレーム及びそのリードフレームを用いた半導体装置の製造方法
JPH07221245A (ja) 1994-02-01 1995-08-18 Sony Corp 半導体装置用リードフレーム
JP2600616B2 (ja) * 1994-09-08 1997-04-16 日本電気株式会社 光結合装置
JP2928120B2 (ja) * 1995-01-18 1999-08-03 日本電気株式会社 樹脂封止型半導体装置用リードフレームおよび樹脂封止型半導体装置の製造方法
JPH08204101A (ja) 1995-01-25 1996-08-09 Nec Kyushu Ltd 半導体装置用リードフレーム
US6215174B1 (en) * 1997-01-20 2001-04-10 Matsushita Electronics Corporation Lead frame, mold for producing a resin-sealed semiconductor device, resin-sealed semiconductor device using such a lead frame
SG75958A1 (en) * 1998-06-01 2000-10-24 Hitachi Ulsi Sys Co Ltd Semiconductor device and a method of producing semiconductor device
JP2000058733A (ja) * 1998-08-03 2000-02-25 Sony Corp 樹脂封止型半導体装置およびそのリードフレーム
US6281568B1 (en) * 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
EP1020933B1 (en) * 1999-01-13 2003-05-02 Sharp Kabushiki Kaisha Photocoupler device
US6355502B1 (en) * 2000-04-25 2002-03-12 National Science Council Semiconductor package and method for making the same
KR100369393B1 (ko) * 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
JP2003133484A (ja) * 2001-10-30 2003-05-09 Tokai Rika Co Ltd 半導体装置及びその製造方法
EP1318544A1 (en) * 2001-12-06 2003-06-11 STMicroelectronics S.r.l. Method for manufacturing semiconductor device packages

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547960B2 (en) 2006-05-04 2009-06-16 Everlight Electronics Co., Ltd. Structure of a lead-frame matrix of photoelectron devices
US7843043B2 (en) 2006-05-04 2010-11-30 Everlight Electronics Co., Ltd. Structure of a lead-frame matrix of photoelectron devices

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