SU935988A1 - Device for control of graphic information recorder - Google Patents

Description

(54) DEVICE FOR MANAGING GRAPHIC RECORDER

Claims (2)

The invention relates to automation and computer technology, in particular to devices for controlling graphical recorders (such as information from an electrochemical recording method) and can be used to simultaneously output a large number of parameters. A device for managing graphic information that contains number registers, decoders is known. , write drivers, AND / 1 elements, AND, synchronization unit, stacking unit, recording unit, and tomato marking unit. The output of several parameters. The marking is done by recording graphs with dots of two different degrees of brightness. In this case, the graph line consists of repeated combinations of light and dark dots, and the combination of dots itself corresponds to a certain graph number l. A disadvantage of the known device is low reliability with registering and subsequent decoding of a large number of graphs; A device is known that contains a shift register, a decoder, a record driver, a reversible counter, a comparison unit, a pulse generator, in which the graph line is not interrupted when the line information changes, but is supplemented by a vertical row of points, the fields are filled 2. However, the known device is poorly reliable registration when changing the values of several parameters recorded on one medium. The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that in a known recorder control device containing a first register, the first input of which is connected to the first input of the device and the first input of the first comparison circuit, the second input of the first register is connected to the second input of the device, the first transducer is connected to the first decoder and the first pulse generator , the second pulse shaper is introduced, the first, second and third inputs of which are connected respectively with the output of the first register with the first input and with the output of the first comparison circuit , the first pulse distributor connected in series to the delay unit, the memory block and the OR element, the input of the first pulse distributor connected to the first input of the first register, the inputs of the second group of the memory block connected to the outputs of the first pulse distributor, the inputs of the third group of the memory block united with the release of the first register, p. the second input of the first comparison circuit, the output of the OR element is connected to the third input of the first comparison circuit, the outputs of the second pulse shaper are connected to the inputs of the decoder. The second pulse generator contains an adder, the first input of which is the first input of the second pulse forking unit, the first input of the second pulse distributor and the counter input is the second input of the second pulse generator, the output of the counter is connected to the first input of the second register, and the first input of the second comparison circuit, the second input of which is connected to the output of the second register, the second input of which is connected to the first output of the second pulse distributor, The output of which is sent by the first output of the second pulse generator, the output of the adder is the second output of the second pulse generator, the second input of the adder is connected to the output of the second comparison circuit, and the third input of the second pulse distributor is the third input of the second pulse generator. In FIG. 1 shows a block diagram of the device; in fig. 2 - structural diagram of the second pulse generator. The device consists of the first register 1, the comparison circuit 2, the decoder 3, the first pulse driver 4, the pulse distributor 5, the block of delay elements 6, the memory block 7 of the OR element 8, the second pulse driver 9, the first and second inputs of the device 10 and 11. 9 84 The second pulse generator 9 consists of the adder 12, the second pulse distributor 13, the counter 14, the second register 15, the second comparison circuit 16, the first, second and third inputs of the second pulse generator 17-19. Pulse distributor 5 performs the formation of readings from Ormash1I, received in the previous period of receipt from memory 7, and through a block of delay elements (5 recording pulses of newly received information. The second pulse shaper 9 is designed to automatically mark the graphs when changing values at least one of the registered parameters. The device operates as follows: The second input 11 of the device, connected to an external information source, periodically receives the current values and measured parameters. During the information receipt period, the value of each of the recorded parameters is received once, all of the measurements are received strictly in a certain sequence. Information is written to register 1 by synchronization pulses, which arrive at the first input 1O. the parameter is fed to the second input of comparison circuit 2, designed to compare the current value of the parameter and its value in the previous period. The sequence of counts in the parameter codes from the memory block 7 is set by the first pulse distributor 5. The read code through the element OR 8 is fed to the third input of the comparison circuit 2. In case the current value of the parameter is not compared with the output value read (M ti 7 from the output of the comparison circuit 2 when When a synchronization pulse arrives at the first input, a signal is outputted at the third input of the second pulse generator 9. The second pulse shaper 9 is synchronized by pulses and implements information for several periods the function of marking the graphs, and also transfers the values of the parameters from the output of the adder 12 to the decoder 3 and controls the operation of this decoder from the output of the second pulse distributor 13. The number of the decoder is determined by the discreteness of the recorded information. The marking of the graphs is alternately marked with a certain length clearly visible and next to the conditional continuation of the main line of the graph. The number of the graph corresponds to the serial number of the label counting from the start of margining. From the output of the decoder 3, the parameter codes are sent to П8 {th pulse generator 4, which generates pulses of the corresponding amplitude and duration and outputs them to the recorder of graphic information. After comparing the codes with the first comparison circuit 2, the current value of the parameter is written back to the memory block 7, where it is stored until the next period. Writing to the memory block is performed by a pulse from the output of the first pulse distributor 5, which has passed through the block of delay elements 6. In a similar way, the codes and the following parameters are compared with the values they had in the previous period. The second driver 9 works in a barely dukim way. The synchronization pulses accompanying the arrival of the next parameter arrive from the second clock 18 at the input of the counter 14, with which it forms the parameter number. The parameter code from the first input 17 is fed to the first input of the adder 12, the second input of which receives a code that increases the first term by one or two units of the youngest bit $ 1 yes (a specific value is determined by the constructive performance of the recorder) and is formed as a result of the arrival of the pulse the second comparison circuit 16 to the lower bits of the second term of the adder 12. At the inputs of the comparison circuit 16, the codes from the output of the counter 14 and from the output of the register 15 are fed. At the moment of changing the parameter value, the third input 19 receives a trigger signal automatic labeling. In this case, the second pulse distributor 13 starts causing code write pulses to the second register 15. The first write pulse to register 15 arrives with the arrival of the first parameter and rewrites the code of the parameter number (for the first parameter, unit code) from counter 14 to register 15. The pulse arrival pulse is defined The length of the written out label and makes several periods of receipt of the information. During these several periods. With the arrival of the first parameter, the second comparison circuit 16 generates a pulse in the second digit of the second term of the adder 12. The registration receives the parameter code, increased by one two units of the least significant bit, as a result of which the main line of the graph on the tape is interrupted and by conditional continuation, a label of a certain length is written. The label must be clearly distinguishable from the schedule. So, with; Navigate visual density of a registry of 3 points per millimeter, an enlarged code of one parameter should be submitted for registration within 8-16 information arrival periods, after which the second pulse distributor 13 generates a write pulse to register 15 with the second parameter. The process of marking the following parameters is similar. The introduction of new nodes and blocks allows us to increase the reliability of registration information, increase the number of simultaneously registered parameters, shorten the time of analysis of registration results and reduce the required number of recorders for a given registration volume. Claim 1. A device for controlling a graphic information recorder, comprising a register, the first input of which is connected to the first input of the device and the first input of the first comparison circuit, the second input of the first register is connected to the second input of the device, sequentially connected deshi {| pulse shaper, characterized in that, in order to increase the reliability of the device, a second pulse shaper is introduced into it, the first, second and third inputs of which are connected respectively to the output of the first o register, with the first input and with the output of the first comparison circuit, the first pulse distributor, the delay unit, the memory unit and the OR element, connected in series with the first input of the first register, the inputs of the second memory unit group, are connected in series the other outputs of the first pulse distributor, the inputs 93 of the third group of the memory block are connected to the output of the first register, to the second input of the first comparison circuit, the output of the OR element is connected to the third input of the first circuit to compare On the other hand, the outputs of the second impulator mapper are connected to the inputs of the decoder. 2.. The device according to claim 1, wherein the second pulse shaper comprises an adder, whose input is the first input of the second pulse shaper, the second pulse distributor and the switch, and the first input the distributor and the input of the counter are the second input of the second generator, the output of the counter is connected to the first input of the second register, to the second input of the second pulse distributor and to the first input of the second comparison circuit, the second input is connected to the output of the second register orogo connected to the first output pulse of said second distributor, the second output of which 1shl a first output of the second fo | the pulse generator, the output of the adder is the second output of the second pulse former, the second input of the adder is connected to the output of the second comparison circuit, and the third input of the second pulse distributor is the third input of the second pulse former. Sources of information taken into account during the examination 1. USSR author's certificate number 3640OZ, class, GO6 К 15/14, 197О. 2. USSR author's certificate number 618763. cl. G06 K 15/14. 1978 (prototype). fj one" f2 17 sixteen fS Ft