SU922880A1 - STORAGE DEVICE WITH SELF-MONITOR 1 - Google Patents

Description

The invention relates to memory devices.

Known memory device with self-control, containing the drive, input, output and address registers, four units of convolutions modulo two, the adder [1].

The disadvantage of this device is the reduction of the effective volume of the drive due to the allocation of part of it, θ under the control bits.

The closest technical solution to the invention is a self-checking memory device containing a drive connected to the input, output and address registers ¹ , the first, second blocks of convolutions modulo two, whose inputs are connected. To the inputs of the address and input registers, and the output to the inputs of the sum _{Μ of the} torus, the third and fourth blocks of convolutions are modulo two, the inputs of which are connected to the inputs of the address register and the outputs of the output register, additional 2

a tel adder, counters, a subtractor, while the outputs of the adders are connected to the inputs of the meters, the outputs of which are connected to the inputs of the subtractor; the inputs of the additional adder are connected to the outputs of the second and third blocks of convolutions modulo two [2].

A disadvantage of this device is its complexity, due to the presence of modules of convolutions modulo two, adders and counters, as well as increasing the likelihood of an error due to the formation of parity bits on two separate channels during recording and reading.

The purpose of the invention is to simplify the device.

This goal is achieved by the fact that in a memory device with self-control, containing modulo-two adders, an input, output and address registers and a drive whose address inputs are connected to the outputs of the address register, information 3 922880 4

The input inputs and outputs of the accumulator are connected respectively to the outputs of the input register and to the inputs of the output register, the inputs of the address and input registers and the outputs of the output register are respectively the address and information inputs and outputs of the device, the reversible counter and the OR element are entered, the inputs of which are connected respectively to the inputs of the input register and the outputs of the output register, the output element OR connected with the inputs of modulo adders two, the outputs of which are connected to the input of the reversible counter, the output which is the output of the device.

The drawing shows a functional diagram of the proposed device.

The device contains a drive 1, the input register 2, the output register 3, the address register 4, the element OR 5, the adders 6 modulo two and the reversible counter 7 ·

The device works as follows.

In the recording mode, the address code and code of the word being written are fed to the inputs of the address 4 and input 2 registers, respectively, and the word is recorded in the corresponding cell of drive 1. At the same time, the code of the word being written enters the first input of the OR 5 element · In the recording mode, the OR 5 element operates on the first the entrance; in read mode, the second one (control signals are not shown in the drawing). From the output of the element OR 5, the code of the written word is fed to the adders 6, which produce the parity bits of the written word. The parity bits are written to the reversible counter 7- Thus, by the end of the recording of the entire block of information in the drive 1, the counter 7 will record the number of single bits equal to "1".

In the read mode of the corresponding address code, the number is extracted from drive 1 and is output to the device. At the same time, the code of the read number arrives at the second input of the element OR 5 and from the output of the last goes to the adders 6. The parity bits formed by the adder. mi 6, are fed to the input of the reversible counter 7, which in the read mode performs the subtraction.

In the absence of errors at the output 5 of the counter 7 will be zero. If there are errors, counter 7 will show their total number. If the number of errors is unacceptably large, the recording and reading of information can be repeated, while the counter 7 is reset to zero. It is also reset to the beginning of the recording of a new block of information.

The technical and economic advantage of the proposed device lies in its greater simplicity and greater reliability in comparison with the known.

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Claims (1)

Claim A self-monitoring memory device containing modulo-two adders, an input, output and address registers and a drive, whose address inputs are connected to the outputs of the address register, information inputs and outputs of the drive are connected respectively to the outputs of the input register and to the inputs of the output register, the address inputs and input registers and outputs of the output register are respectively the address and information inputs and outputs of the device, characterized in that, in order to simplify the device, it contains p versivny counter and an OR gate whose inputs are respectively connected to the inputs of the input register and the outputs of the output register, output of OR element connected to inputs of adders modulo two, the outputs of which are connected to the input of down counter whose output is an output device.