SU922707A2 - Device for probabilistic simulation - Google Patents

Description

The invention relates to computing and is intended to simulate random processes.

According to the main auth. No. 488212, a device is known comprising a random number generator, a comparison block, a mask register, a number register, a block. a memory, an address register and a control unit, the input of the random number generator being connected to the first output. control unit, the first input of the comparison unit is connected to the output of the generator, random numbers, the second input to the second output of the control unit, and the first output to the first input of the address register, the second input of which is connected to the third output of the control unit, and the output to the input of the memory block ti, whose output is connected to the first input of a number register, the second input of which is connected to the fourth output of the control unit, the fifth output of which is connected to the first input of the mask register, the second input of which is connected to the second output of the comparison unit, and the third input is with the output of the register of the number, the first output with the third input of the comparison unit, and the second output g with the third input of the registrar of the address intended for

forming discrete random variables and simple Markov chains.

However, with the help of this device it is impossible to form more complex chains — multi-connected chains in which the probability of the occurrence of a subsequent state depends on more than one previous state.

The purpose of the invention - expansion

10 Functionalities due to the formation of multiple Markov chains.

Set goal Achieved by having a device containing a random number generator, a comparison block, a mask register, a number register, a memory block, an address register and a control block, the input of a random number generator being connected to the first output

20 of the control unit, the first input of the comparison unit is connected to the output of the random number generator, the second input is connected to the second output of the control unit, and the first output is connected to the first input of the address register, the second input is connected to the third output of the control unit, and the output is with the input of the memory block, the output of which is connected to the first input of the number register, the second

30 whose input is connected to the fourth output of the control unit, the fifth output of which is connected to the first input of the mask register, the second input of which is connected to the second output of the comparison unit, the third input to the output of the number register, and the first output to the third output of the comparison unit , additionally entered the counter, the element OR NOT, the element And, the modulo adder two, the switch and the group of elements AND, the first inputs of which are combined with the first input of the switch and connected to the second output of the mask register, the second inputs of the elements AND of the group are combined with per th input of the AND element, with the counting input of the counter and with the second input of the address register, the third input of which is connected to the output of the switch, the second input of which is combined with the second input of the AND element and connected to the output of the OR-NOT element, whose inputs are connected to the meter outputs, the third input of the switch is connected to the output of the modulo-adder two, the first and second inputs of which are connected respectively to the outputs of the elements of the And group and the element I. Figure 1 shows the block diagram of the device; 2 is a control block diagram. ; Fig. 3 shows diagrams of operation of the control unit. The device comprises a random number generator 1, a comparison block 2, a mask register 3, a register 4 numbers, a memory block 5, an address register 6, a control block 7, a block 8 for changing the communication depth of circuit states, a switch 9, a group of 10 elements And Modulo two adder 11, element ILINE 12, counter 13, element And 14. Blocks 1-7 relate to the main device, nodes 9-14 contained in block 8 are optional. Control unit 7 contains a clock frequency generator 15, elements OR NOT 16 and 17, shift register 18, elements OR 19 and 21, item AND 20, shift register 22, uh Elements 23-25, shifting register 26, element 27, element 28, elements 28 and 30, bus 31, communication with random number generator 1, bus 32, communication with register 4 numbers. Bus 33 communication with the mask register 3, bus 34 communication with the unit 2 comparison, bus 35 communication with the address register B, part 36 of the bus 35 used to synchronize the block B. In this case, R is the input of the zero setting C - synchronous input ;. D -. Information entry; 1 - the level of logical units. The power supply and initial settings of the initial state are not shown. Fig. 3 shows the timing diagrams of the control unit at the outputs defined ((nx of the circuit nodes. Random number generator 1 is pre-assigned for generating the original, uniformly distributed random binary numbers. The input of the random number generator 1 is connected to the first output of the control unit 7. Block 2 Comparison serves for parallel comparison of the group of boundary values of the partition intervals of the domain B formed of the random function with the initial random number. The first input of the comparator unit 2 is connected to the output of the generator 1 random numbers, the second input with the second input of the control unit 7, and the first output with the first input of the address register 6. The address register 6 serves to control the memory block 5 and is divided into two parts, the youngest and the most significant. cells of the memory block. The older part of the register indicates the location of the array of cells. The first input of the register 6 address, connected to the first output of the comparison unit 2, is the input of the younger part. The second input of register 6 of the address is connected to the third output of control unit 7 and the second input of unit 8. This input is a synchronization input. The third input of the register 6 of the address is connected to the output of the block 8 for changing the communication depth of the states of the circuit and is the information input of the upper part of the register 6. The memory 5 serves for storing the code of the distribution function and its arguments. The input of block 5 is connected to the output of register 6 of the address. Register 4 of a number is used to receive the contents of the 5 Ps1mti block and to store it for the duration of the comparison operation. The first input of register 4 is connected to the output of memory block 5, and the second input is connected to the fourth output of control block 7. Mask register 3 serves to mask the register bits of 4 numbers. The purpose of masking is to remove information only from a certain part of the bits of the cell of the memory 5 at a given device operation time. The first input of the mask register 3 is connected to the fifth output of the control unit 7, the second input to the second output of the comparison unit 2, and the third input to the output of the register 4 numbers. The first mask output register 3 is connected to the third input of the comparator unit 2, and the second output to the first input of the unit 8 for changing the communication depth of the states of the circuit. The block contains a switch 9, a group of 10 elements, an adder 11 modulo two, an ILINE 12 element, a counter 13 and an AND 14 element, the first input of the switch 9 and the first input of elements 10 are interconnected and form the first input of the block 8. The second input of elements 10, the first input element And 14 and the input of the counter 13 are also interconnected and form the second input of the block 8 The output of the block 8 is the output of the combator 9-. The second input of the switch 9 is connected to the second input of the element AND 1.4 and the output of the element —OR — NO 12, the input of which is connected to the output of the counter 13. The output of the element 14 and 14 is connected to the first Modular output of modulator 11 modulo two, the second input of which is connected to the output of the elements 10, and the output - with the third input of the switch 9. The principle of operation of the device is as follows. Obtaining random numbers XJ (1-1,2, ..., ..., p) with a given distribution law F (xj) is based on a comparison of uniformly distributed numbers with values of P (x |), finding the interval where the condition F (xi) (x ;,) (1) and issuing values corresponding to this interval. . To implement the relation (1). All values of T (x |) are divided into groups. Groups are selected from a memory block by a logarithmic search and each group is compared with the number e, in parallel. The logarithmic search is carried out in an orderly arrangement of the values of F (xj) and xj in groups. In the formation of simple and multifaceted Markov chains, the algorithms for obtaining X | serve to implement a single row of a stochastic matrix. The choice of the next line is determined by the obtained values of X |. The operation of the device consider the following example. Let (, b4) and the base of the logarithm be 4. Also, for definiteness, we assume that the generator 1 of random numbers is pseudo-random. The circuit of the control unit 7 corresponding to this example is shown in FIG. The device works as follows. By an external Start signal, which enters the control unit 7 via the Start bus (see Fig. 2), the trigger, formed by the OR-NOT elements 16 and 17, is set to one. At the same time on the information, the input shift register 18 receives the logic level. The leading edge of the next clock frequency pulse, which is fed to the synchronous input of the register 18 from the generator output 15 clock frequency, is recorded in the first digit of the register 18 (the upper one) 1. This 1 sets the initial zero state of the trigger formed by the elements of OR-NOT 16 and 17, and through the element OR 19 opens the element AND 20 for the passage of pulses of the clock frequency generator 15. When the next pulse of clock frequency 1 arrives from the first bit, register 18 is rewritten into the second, and O is recorded for the first bit. The sixth clock pulse causes the appearance of 1 at the output of the sixth, last bit of register 18, which is connected through OR 21 to D the input of the shift register 22. When | the seventh pulse arrives at the clock; the frequency of the register 18 is in the zero state, the AND 20 entry is recorded. The first bit of register 22 (the upper one forms bus 32) is recorded as a result. As a result, six pulses are formed on bus 31 linking the control unit with random number generator 1, which are necessary to generate the output. random 6-bit binary number. The resulting random number comes from the output of generator 1 to the first input of block 2 of comparison. The impulse on the bus 32, which is formed by the output of the first bit of register 22 and connects the control unit with the register 4 numbers, denies writing to register 4 the number of cell contents of memory block 5 whose address is determined by address register 6. In this case, the highest part of the register b defines the address of the array of cells, and the younger part - the address of the cell in the array. The contents of the memory block 5 in the register of 4 numbers, through the mask register 3, is fed to another input of the comparison block 2. In the example under consideration, three cycles are necessary to implement relation (1). In the first cycle, the conditions F (x,) "S, F (x, JJ), F (x, 6) 4.F (Xii), F (xjjk, F (xcе) F (Xc") 5.F (x bm). Let S fall into the interval F (XI), F () l, then in the second cycle the conditions F (x,) (x c), F (K4) (x8),, F (x) 5, F (xa), F (Xiz) (xis), Let J fall into the interval FCxtt), F (x., 6), then the conditions F (), F (xii), F (x .,) "5.F (x), F (x, c) 6.F (hch5), F (xis) 6, F (x, 6). During these three clocks, from the memory block 5, three cells are selected in which the following groups of values Ffx, 6), F (x), F (xue) are contained; F (x 1,), F (x s). f F (x ii); F (Xi, F (x, u),). These groups are compared in block 2 comparisons with a random number,. The relevance of the number to one of the four intervals is indicated as a logical unit on one or four outputs that make up the output bus of block 2. The result of the comparison goes to the lower part of the address register, which is a shift register, and is used to form the address which, from block 5 of memory, selects a new group, the values F (xj), the First group F (xi), which is compared in the first comparison cycle, does not depend on, that is, the cell address in which the first group F is stored (xj ) Is constant. This is achieved by setting the lower part of the address register B to the zero state before each comparison cycle. The comparison process is provided as follows. The shift register 22 performs the function of the pulse distributor, and the register 26 in combination with the AND-27 element functions as the counter clock counter. In this case, the first pulse arriving at the bus 32 is used to write to the register 4 the numbers of the next group F (x;). The second impulse, which from the second output of the register 22 through the open element I 29 enters the bus 34, is used to write to the register contained in the unit 2 of the comparison, the result of the comparison. Memorization of the comparison result is necessary for the mask register 3 to work properly, because otherwise, when masking the digits of register 4, the result of the previous comparison that controls the mask register 3 changes, which leads to a change in the result of masking. The third pulse, which from the third output of the register 22 through the open element I 30 enters the bus 35, serves to write the comparison result to the lower part of the address register b. After the completion of the comparison cycle, the group of values k /, is read into the register 4, one of which is the current state of the circuit. The selection of Xj is provided by mask register 3. Those parts of the mask register into which logical zeros have arrived at the outputs of block 2 of the comparison are closed. Only one part remains open, to which input is received 1. The number xj is removed from those bits of the register 4 numbers that correspond to this open part. Reading xf and going to the next row of the stochastic matrix is provided by changing the mode of operation of the control unit. If the first, second and third series of pulses generated by the register 22, provide the realization of the comparison cycle, then the last fourth - a series of pulses ensures the formation of the current value of the circuit and preparation for a new cycle of the device operation. Element And 27 is then opened, since after each pulse train, register 26 is recorded 1, and after the third series, And 27 is present at all inputs of element I. This leads to locking And 29 and 30 elements and unlocking And 23 and 25 elements. As a result, the second pulse from the register 22 does not go to the comparison unit 2, but through the element 23 to the bus 33 connecting the control unit with the mask register 3. At the same time this im-. the wheel enters the tires 36 and 35. Bus 35 takes this impulse to the lower part of register b of the address and sets it to the initial zero state, thus preparing for the new work cycle, and through bus 36 it goes to the input of the counter 13 and the second the input elements 10. The third pulse from the register 22 through the element And 25 enters the bus 36 and 35, and through the bus 36 it arrives at the first input element And 14, and through the bus 35 - on the older part of the register 6 address and serves to record information in the upper part of the register is 6. The resulting value of x, which represents the The second current state of the circuit, from the output of register 4 through the register 3 of the mask, goes to the first inputs of the switch 9 and elements 10. The impulse of the control unit 7 coming from the output of element 23 and setting the initial part of the lower part of the register b of the address simultaneously arrives the second, the input elements And 10, opens them, and the input xj modulo two arrives at the input of the module. The adder 11 is a set of T-flip-flops, the inputs of which are connected to the corresponding outputs of the elements And 10, and serves for a bit-wise modulo two Numbers xj. The initial state of the adder 11 is zero. The pulses coming in at the second input of a group of 10 elements are simultaneously received at the input of counter 13, which counts the number of summed numbers xi. After adding a number of numbers (the number m determines the increased depth of the circuit and represents the number of possible states of the counter 13, including zero), the counter 13 overflows and goes into the zero state, which causes the appearance of 1 at the output of the element OR NOT 12, the inputs of which are connected to the outputs of the triggers of the counter 13. In this case, the result is summed by the numbers x, from the output of the adder 11 through the switch 9 enters the input of the higher part of the register b i address. This information is written to register B by the pulse of control block 7, coming from the output of AND 25. The summation result recorded in address register B serves as the address of the array of cells in memory block 5, on which the next row of the stochastic matrix of the circuit is written. After each such cycle the modulo two adder is formed in the zero state by a pulse of recording information in the upper part of register 6. This pulse to the first input of the And 14 element, to the second input of which from the output of the el of the element OR-NOT 12 enters 1. The pulse arising at the output of the element 14 is fed to the input of the zero setting of the adder-11 modulo two.

The operation cycle of the control unit 7 is completed after the end of the impulse to write information to the older part of the register 6. At the same time, the next clock pulse of the clock frequency generator 15 causes the occurrence of H at the last output of register 22, which leads to occurrence) 1 at the last output of register 26. V As a result, at the output of the AND 24 element appears 1, which sets the registers 18, 22 and 26 to the zero connection and simultaneously sets the trigger formed by the OR-NOT 16 and 17 elements to the single state, making a new start of the unit 7 pack ION. This completes the cycle of operation of the device.

In the proposed device, along with the formation of simple Markov chains, which is achieved by setting the counter 13 to the zero state.

more complex circuits can be obtained, i.B whose probability of occurrence of the current state of the circuit depends on a given combination of previous states or on a given number of states. In terms of functionality, the proposed device can, at low hardware costs as compared with the known device, simultaneously replace two devices, one of which is designed to generate simple Markov circuits and the second to generate multiple Markov circuits. .

Claims (1)

Invention Formula Device for probabilistic modeling auth.St. No. 488212, characterized in that, in order to expand the functionality of the device by forming multiple Markov circuits, it contains a counter, an element OR — NOT, an element AND, a modulo two, the switch and a group of elements AND, the first inputs of which are combined with the first input of the switch and connected to the second output of the mask register, the second inputs of the elements AND of the group are combined with the first input of the AND element, with the counting input of the counter and with the second input of the address register, the third input of which is connected to the output of the AND element and connect ene to the output of OR-NO element, whose inputs are connected to the discharge dnymi counter outputs, the third input switch connected to the output of the modulo two adder, the first and second inputs connected respectively to the outputs of the AND elements and group VI