SU901991A1 - Device for timepiece synchronization - Google Patents

Description

(5) DEVICE FOR CLOCK SYNCHRONIZATION

I

This invention relates to instrumentation engineering and is intended for use in synchronized electronic clocks.

Known clocks with synchronization 113 However, known devices do not provide reliable synchronization.

The closest to the present invention is a clock synchronization device containing a series-connected crystal oscillator, a frequency divider made in the form of a multi-bit binary counter, and a decoder, the first output of which is connected to the trigger input, the outputs of which are connected to the first inputs of the first and second elements , the second inputs of which are respectively connected to the external synchronization input and to the output of the first OR element, while the outputs of the AND elements are connected to the inputs of the second OR element,

The disadvantage of this device is that the reliability is not sufficiently high, since with the loss of external synchronization pulses, counting pulses that are not identical to external synchronization pulses are generated at the device output. The duration of the generated pulses is equal to the zeroing time of the frequency divider and may be insufficient for reliable operation of the clocked clocks.

The purpose of the invention is to stabilize the duration of the counting pulses at the output of the device.

The goal is achieved by the fact that a device containing a series-connected crystal oscillator, a frequency divider made in the form of a multi-digit binary counter, and a decoder, the first output of which is connected to the trigger input, the outputs of which are connected to the first inputs of the first and second elements And, the second which inputs respectively. are connected. to the external synchronization input and to the 3 9 output of the first OR element, while the outputs of the AND elements are connected to the inputs of the second OR element, the third and fourth AND elements and the delay element are entered, the first inputs of the third and fourth AND elements are connected to the output of the quartz generator, the second inputs are connected respectively to the first and second outputs of the decoder, and their outputs are connected to the inputs of the first OR element, and the delay element is connected to the zero bus of the frequency divider and the output of the second OR element. The drawing shows a block diagram of a device for synchronizing clocks. The device contains a crystal oscillator 1, connected to dividers) 2 frequencies, a decoder 3 included at the output of the divider 2 frequencies, the first output of the decoder 3 is connected to the input of the trigger C and the second input of the element 5 and the second output of the decoder 6. First The inputs of elements 5 and 6 are connected to the output of the quartz oscillator ea 1, and the outputs to the inputs of the element OR 7 whose output is connected to the second input of the element 8 and 8, to the first input of which the second output of the trigger k is connected. The first output of the trigger C is connected to the first input of the element I 9, the second input of which is connected to the input of the external 10 synchronization. The outputs of the And 8 and 9 elements are connected to the inputs of the OR 11 element, the output of which is connected to the input of the delay element 12 and is simultaneously the output 13 of the device. The output of the delay element 12 is connected to the shanxi zero reset frequency divider 2. The decryption numbers on the first and second outputs of the decoder 3 are selected from the ratios N, (HG); Nj, where f is the frequency of the quartz oscillator 1; F is the frequency of the following external synchronization pulses; relative frequency error of the crystal oscillator 1. The device works as follows. In the initial state, the divider 2 frequencies and the trigger k are zeroed. At 14 start-up of the device, the divider 2 frequency receives permission to the account (the start circuit is not shown). The quartz oscillator 1 generates pulses with duration equal to external synchronization pulses arriving at input 10. The pulse frequency at the output of divider 2 frequency is exactly equal to the external synchronization pulse frequency, since the zeroing of the frequency divider is performed only by external synchronization pulses, because the zero signal with internal signals the first and second outputs of the decoder 3 is closed (element 8 is closed). To connect the zeroing circuit with internal signals, it is necessary to switch the trigger C, controlling the elements of And 8 and 9 that switch the zeroing circuit of divider 2. The trigger switches the signal from the first output of the decoder 3- This signal is generated only in case of loss of external synchronization pulses, because in the presence of external synchronization pulses, due to the choice of decryption numbers on the outputs of the decoder 3, the divider 2 is zeroed before it dials the code corresponding to the first decoder number. Thus, in the case of the disappearance of the external synchronization pulses to the input 10, the divider 2 is once again not reset, a signal is generated at the first output of the decoder 3, and the trigger i switches over. The element AND 9 is closed, the element AND 8 is opened, the element AND 5 si “-number from the first output of the decoder 3 is open at the second input. Frequency divider 2, made in the form of a multi-bit binary counter, changes its state along the falling edges of the pulses coming from the output of the crystal oscillator 1. Therefore, the signal at the first output of the decoder 3 is stored before the arrival and end of the next pulse from the output of the crystal oscillator 1. This pulse passes through the open elements AND 5, OR 7, AND 8, OR 11, arrives at the output 13 of the device and at the same time through the delay element 12 to the zero frequency divider bus 2, driving it to its original state. In order that divider 2 should not be zeroed before complete passage of the pulse to output 13 of mouth59

properties, the delay time of element 12 must satisfy the condition

U U)

where tj is the delay time of element 12; - pulse duration of the quartz oscillator; TC - the period of the pulse

crystal oscillator 1. Subsequently, divider 2 is impulsed with pulses from the output of the element 6 and generated when a pulse from the output of the crystal oscillator 1 and the signal from the second output of the decoder is simultaneously received at its input 3. The device issues counting pulses at its own frequency equal to F ( 1 ± S), i.e. will switch to internal sync mode. The switching time with an appropriate choice of the number N at the first output of the decoder 3 must be at least G / F.

The proposed device, thanks to the introduction of the third and fourth And elements gated by the first pulses from the output of the quartz oscillator, l of the Zadeh element, which does not allow the frequency divider to zero before the pulses pass to the output of the device, provides the output of the device, regardless of the synchronization mode, stable not only in frequency, but also in duration.

sixteen

Claims (2)

1. USSR author's certificate ff t3376S kp. G O C 3/00, 197. 2. USSR author's certificate IT 632981, kp. G Qk C 3/00, 1977. / 3