SU866487A1 - Digital converter of parallel-series follow-up balancing - Google Patents

Description

The invention relates to digital measuring equipment, and can be used for measuring constant and slowly varying voltages.

A digital parallel-serial balancing converter is known, in each discharge of which an amplitude analyzer, a voltage divider and C1J correction input unit are included.

The disadvantage of this converter is its low accuracy.

A parallel-serial balancing digital converter is also known, the discharge of which contains an amplitude analyzer, a voltage divider, a correction input unit and a subtractor, while the input bus is connected via a key to the input of the first amplitude analyzer and through a corresponding subtractor and key, followed by an amplitude analyzer of the next discharge, and the outputs of the voltage dividers through the key are connected to the second input of the subtracting device, the output of which through the key is connected to the course of the amendment input block, the output is last! it is connected to the second input of the voltage divider, the first input is connected to the output of the amplitude analyzer [2]. A disadvantage of the known converter is its low accuracy due to errors, the order of which corresponds to the weight of the subsequent discharge, as well as additional errors introduced by the device for determining the polarity when connecting the latter at the input of the device. So, when applying a voltage of 99.9 V to the input, the known device cannot

- can amend the digital output and output not 99.9 V, but .100 V.

The purpose of the invention is improving accuracy. This goal is achieved by the fact that a parallel-sequential follow-up balancing digital converter containing an input unit, a correction input unit, and in each category an amplitude analyzer connected by the output to the control input of the voltage divider in each category, except the last one, a polarity determination unit is introduced, the first input of which is connected to the reset bus, and the first and second polarity switches are inserted into all the discharges except the first and last, the first and last discharges are entered, respectively about the second and first polarity switches, while the second input of the polarity determination unit is connected to the output of the amplitude analyzer of the last bit and to the first input of the last bit 'of the correction input block, the second input of which is connected to the output of the polarity determination block, the inputs of each bit of the correction input block, except the latter are connected to the outputs of the amplitude analyzers of the corresponding discharges, and the output of the polarity determination unit is connected to the control inputs of all the polarity switches of each of the charge, the inputs of the first polarity switches of each discharge are connected, respectively, to the inputs and outputs of the decade-long voltage dividers of its own and the previous one: bits, and the outputs are connected to the second inputs of the amplitude analyzers of the corresponding bits, the inputs of the second switches of the triggers are connected to the outputs of the polarity detection unit.

In this case, the first bit of the amendment input block contains nine input elements * 5 ment OR and a three-input AND element, the second digit contains a nine-input OR element, two three-input OR elements and three two-input AND elements, the remaining bits, except for the last two, 10 contain a nine-input OR element, two three-input OR elements and four two-input AND elements, the penultimate category contains a nine-input OR element, two and three-input OR elements 15 and three two-input elements AND, the inputs of all bits of the corrections input unit, except the last it contains characters tire Ί, 2 ', 3 ... 9 ^minutes, the inputs of the second and all subsequent bits comprise shi20 us positive and negative polarity current value signal as well, except for the last digit, tires comprise positive and negative excess decade interval and the sign bus' О *, the second input of the last bit, contains buses of positive and negative polarity of the input signal, input! Nine-input elements of linearity are connected to the outputs of the corresponding bits of the correction input block, ₃ θ and the outputs are connected to the third inputs of the amplitude analyzers of the corresponding bits, the first inputs of all amplitude analyzers connected to the output of the input block.

In addition, the amplitude analyzer ^{35 was} performed on a decade-sensitive electron beam sign indicator (ELSI), the first three inputs of which are connected to the corresponding inputs of the amplitude analyzer, and the sign output ^{40 is} connected to the input of the amplifier unit, the ELSI correction output through the correction unit is connected to the third ELSIE INPUT.

In this polarity determination unit comprises two AND gates and two trigger 'zero inputs of which are connected to a first input of a polarity determination unit inputs, respectively, sub-keys ⁵⁰ to the outputs of the first and second AND gates, the first inputs of which are connected to second inputs of block determine the polarity, the second input of the first element And is connected to the zero output ⁵⁵ • of the second trigger, and the second input of the second element And is connected to the zero output of the first trigger, single inputs of two

OR of each category are connected to the corresponding spikes of signs 1 * -9, in the first category the output of the nine-input element OR is connected to the first input of the three-input element And, the output of which is connected to the output of the first category, the third input is to the sign bus O * of the second category, the second input is three-input , And element of the first discharge and the second inputs of the third two-input elements And subsequent discharges are respectively connected to the input of the first three-input element OR of the second discharge and with the outputs of the fourth two-input elements And its discharge and with the exception of the penultimate discharge, in which the second input of the third AND element is connected to the outputs of the two-input OR element, the first and second inputs of the first three-input OR element, each category, except the penultimate, are respectively connected to the outputs of the first and second elements AND of their category, and in the penultimate category the first and second inputs of the two-input OR element are respectively connected to the outputs of the first and second elements AND of its category, the first inputs of which are respectively connected to the positive and negative buses the polarity of the current value of the signal of the last discharge, the second inputs

8G6487 of the first and second AND elements of each category, respectively, are connected to the buses of negative and positive polarity of the input signal of the second input of the last digit, the outputs of the second and subsequent ₅ next bits of the correction input unit are connected to the outputs of the second three-input elements OR of the corresponding bits, the first and the second inputs of the second three-input elements OR of each discharge are respectively connected to the buses of negative and positive excess of the decade interval of their discharge, and the third input is connected to the output And third .dvuhvhodovogo its discharge element ₁₅ whose first input is connected to the output of OR devyativhodovogo its discharge, and a second input connected to a third input of the first OR gate and trehvhodovogo yield dvuhvhodovo- fourth _2Q th element and its discharge, except penultimate discharge in which the second input of the third two-input element AND is connected to the second input of the fourth two-input element AND of the previous discharge And to the output of the two-code element OR of its discharge, the first and second inputs The Fourth dvuhvhodo- O VI elements each respectively connected to the discharge marks tires G * and outputs OR of the first trehvhodovyh elements.

In FIG. Figure 1 shows the structural electric circuit of an η-bit digital converter of parallel-series follow-up balancing; ^{35 of} FIG. 2 is a circuit diagram of a polarity determination unit; FIG. 3 is a circuit diagram of an amendment input unit.

The converter contains an input unit 1, an amplitude analyzer made on ELSY 2, a correction unit 3 and an amplifier unit 4, decade voltage dividers 5, polarity switches 6, a polarity determination unit 7, the second input of which is connected to the bus '' Reset, c-bit unit 8 corrections, 9 polarity switches.

Block 7 determine the polarity (Fig. 2) contains the elements And 10, 11 and triggers 12 and 13.

Block 8 input amendments (Fig. 3) contains nine-input elements OR 14, 15, 16, 17, 18, the inputs of which are connected to the bus signs '1 * -' 9 * of the corresponding digits, three-input element And 19, two-input elements And 20, 21 , 22, three-input element OR 23, two input elements AND 24-27, two-input element OR 28, three-input elements OR 29, 30, two-input elements AND 31-38 and three-input elements OR 39-42.

The digital Converter parallel-serial tracking level is as follows.

When applying the signal l / χ to the input unit 1, made on the amplifier, the signal from the output of the latter goes to the first inputs of the ELSIE 2 amplitude analyzers, which have a ten-day sensitivity from discharge to discharge. In this case, the ηth discharge has the maximum sensitivity, and therefore, at the output of the ELSY 2 and block 4 amplifiers, a signal appears about the polarity of the input signal 9χ _? arriving at the first input of the polarity determination unit 7, where the polarity of the input signal is memorized, which also goes to the second input of the corresponding discharge of the correction input unit 8. Simultaneously with the output of the amplifier block, an information signal about the polarity of the input signal l / χ is fed to the first input of the same discharge of the correction input block. The polarity signal of the input signal Ux from the output of the polarity determination unit also goes to the controlled inputs of the first and second polarity switches 6 and 7 of all bits, bringing them into the corresponding state in order to process the input signal Uy corresponding to its polarity.

Suppose that the input signal is ϋχ = 99.9 V, and the first digit of this input signal Tsu corresponds, for example, to the second digit. Since the voltage 1> X = 99.9 V is close to 100 V, the ELSI 2 of the first category will operate, and the signal on the sign bus' 1 appears at the output of the unit 4 of amplifiers of this category, which is fed to the control input of the 10-day voltage divider 5 (ДДН) this discharge and the corresponding discharge of block 8 input amendments. The voltage from the output of the DDN 5 of the first discharge through the DDN of 5 subsequent discharges and through the first polarity switches 6 is supplied to the second input of the ELSY 2 of the next discharge, where the compensation signal removed from the output of the DDN 5 of the first discharge is subtracted from the input signal ϋχ. As a result of the subtraction, it turns out that in ELSIE 2 of the second and third category, the resulting signal is zero, and in the subsequent discharge it is

Ί unit, but with the opposite sign (99.9-100 = -0.1). This leads to the fact that on the first input of the last bit of the correction input unit 8, the signal appears on the bus with the opposite polarity information of the resulting signal, which leads to the error correction signal being sent to all previous discharges, starting from the first one that worked, resulting in in the first category, ELSIE 2 will fix the '0 * sign and hold it with a signal from the output of the correction unit 3, as well as in subsequent bits.

Information in the second category is recorded and held by the correction unit 3 and corresponds to the sign '9', as well as in subsequent categories. In this case, as soon as the information of the penultimate category is corrected, the signal equal to 99.0 V is synthesized at the output of the series-connected DDN 5. As a result of subtraction, in the last category, the result has the same sign as the sign of the input signal, therefore, at the first input of the last the discharge of the corrections input unit, a signal will appear on the bus of the same polarity compared to its first input, which will disable the corrections input unit 8.

When disconnecting the input signal l / χ from the input unit and applying a pulse to the input 'Reset', the output information in the digital converter is reset.

The operation of the unit for determining the polarity (Fig. 2) is as follows.

When a signal is supplied from the output of a block of 4 amplifiers to the first input of the And 10 element and, considering that the triggers in the initial position are in the zero state, the trigger 13 is triggered, and a signal will appear at its single output even when the first input of the And 11 element appears signal of opposite polarity. The polarity detection unit is in this state until a signal is sent to the 'Reset' bus, after which it is again ready for operation.

The operation of the input block amendments (Fig. 3) is as follows.

Suppose that a signal of 99.99 V is supplied to the input of the digital converter and, taking into account the error, it will record information of 100 V. In this case, a signal appears on the input of the first bit of the corrections input unit, which via the sign bus * 1 * through a nine-input element OR 14 goes to the third input of the three-input element And 19. At the first input of the same element And 19 also has a signal, since it is connected to the sign bus. '0' of the second bit input. At the input of the third and fourth category, signal 5 appears on the sign buses .'O ', which leads to the appearance of a signal on the second inputs of the elements And 24, 25. At the input of the fifth category, an information signal appears on the sign bus' 1', since 10 100 , 00 V + 99.99 V = -00.01 V. The remainder -00.01 shows the sign bus number, and the sign indicates that the polarity of the current value of the active signal in this discharge is opposite to the polarity of the input signal. This distribution of polarities leads to the fact that at the two inputs of the sixth category, the signal appears on the opposite in phase buses, positive and negative.

This will trigger the first ^{w of the} two-input element And 33 and the signal from its output through the first three-input element OR 30, the fourth two-input element AND 25, the first three-input element OR 29, the fourth two-input element AND 24 and the first three-input element OR 23 is fed to the second input of the three-input element And 19 and its output, therefore, at the output of the first 3Q of the first discharge appears the correction signal, which introduces a correction for one significant unit in the first digit of the digital Converter. As a result, at the input of the first discharge AND at the output of the element And 19 the signal disappears. The supplied signal = 99.99 V exceeds the decade interval of the second discharge by 9.99 V, which leads to the fact that a signal appears at the input of the second discharge and, through the sign bus exceeding the decade interval _χ * + X ', it enters through the second three-input element OR 39 the output of the second discharge, while the information in the digital converter of this discharge changes by one, i.e. fixed sign ⁴⁵ '9 *.

Similarly, on the bus exceeding the decade interval '+ X', through the second three-input element OR 40, the signal is output at the third time of the ^50th row, as well as in the fourth category.

As a result of sequential operations in three digits, the digital conversion is. The user will register 99.9 V.

⁵⁵ The difference of the input signal, synthesized in the digital converter, in the fifth digit of the signal appears on the sign bus' 9 *, which will lead to the appearance of a signal on the single-phase buses of all inputs of the bits, and the input of corrections will stop. The use of the invention allows to increase the accuracy of digital converters parallel-serial tracking balancing.

Claims (2)

1. USSR author's certificate No. 137187, cl. Q O1 R 27/16, 1961. 2. Digital electrical measuring instruments. Ed. V.M. Shl Ndina, M., Energie, 1972, p. 292-295, fig. 82 (prototype).  e Fl.1