SU798919A1 - Information registering device - Google Patents

Description

The invention relates to computing technology and is intended for use as part of the means for collecting and recording primary data in production process information acquisition systems. Information recording devices are known in which in order to improve accuracy. - operation when entering data of the variable part of the recorded message from the keyboard. The double information input method and format control method are used. In such devices, information is recorded when the information entered coincides in the Set 1 and Set 2, and the width of the word being registered is set by the input and registration program; occurs only when forming a word with a size equal to a given one. Such an information recording device contains sensors, a buffer register, information receivers, a symbol decoder, a control unit, a symbol counter, a state decoder, a code register, a code decoder, a gate, a trigger, elements AND, OR and Prohibition. It allows forming words of a variable, but predetermined, size when collecting data, and registering them 1. However, in the case when the specified using the bit program grid of the registered word was overfilled when typing, the described device does not automatically address the beginning of the registered word in the correction mode. Thus, when detecting a failed format, the operator must correctly enter and register the entire message first. This increases the burden on the operator. For correction, additional device operation time is used (device utilization rate decreases), and an increase in the number of characters entered by the operator (due to newly entered characters during correction) reduces the reliability of the entered message and increases the message input time, thereby reducing the operator and device performance. The closest in technical essence to the proposed is the device DL9 information registration, containing the control panel.

information sensors and a keyboard are connected to one of the outlets through a serially connected address register and a sensor call circuit, information receivers a buffer register are connected to others through a serially connected register of receiver addresses and a receiver call circuit, the inputs of which are connected to information sensors and a keyboard, and outputs with information receivers and a decoder, and a firmware automat, whose outputs are connected to a control panel, sensor and receiver address registers and calling circuits sensors and receivers, and inputs with a control panel and a decoder, a random access memory, a comparison register, a comparison circuit, and two AND circuits, with the outputs of the buffer register connected to one of the random access memory, to the others through the outputs of the firmware and the sensor address register, and the outputs through the comparison register are connected to the first inputs of the comparison circuit, the second inputs of which are connected to the buffer register, and the output to the microprogram automat.

Such a structure of the device allows the operator to detect operator errors when entering information from the keyboard and to improve the accuracy of the device 2.

However, if the first and second sets of information do not match, only the signal Mismatch is generated, and the alarm is provided on the control panel and the device is blocked.

To complete the Formation and Registration cycle; messages, most of which can already be entered correctly from the keyboard, the operator is obliged to reset the entered information, perform certain manipulations with the control keyboard of the control panel, and correct the information at the required addresses in the memory device.

At the same time, the increase in the Number of characters entered by the operator, taking into account the correction of information from the keyboard, increases the burden on the operator, reduces the reliability of his work and his. performance This also reduces the coefficient on the use of the device, since it takes additional time to operate the device, which could be used to record the following messages.

The purpose of the invention is to enhance. authenticity of registration for the account.

control the format of input information.

This goal is achieved by the fact that in a device for registering information containing serially connected an operator console, a register of sensor addresses, a sensor selection block, sensors and a keyboard, a buffer register connected to the first comparison block, to the service symbol decoder and through the memory block to the address decoder, receivers, receiver selection block and receiver address register connected to the operator’s console and the control unit, the control unit being connected to the operator’s console, the register of sensor addresses and receivers ministers, sensor and receiver selection blocks, first comparison block, service symbol decoder, memory block, buffer register and receivers, the first element OR of which inputs are connected to sensors, keyboard and receivers are added, and the output, word end address hub connected to control block, memory block address register, second and third comparison blocks, and memory block address buffer register connected to address decoder, first and second AND elements whose outputs are the first inputs to the control unit, the second OR element, whose inputs are connected to the first and second comparison blocks, the third OR element, whose inputs are connected to the third comparison unit and to the control unit, the trigger whose inputs are connected to the outputs of the second and third elements OR, and the outputs to the second inputs of the first and second elements AND, the third input of the first element AND connected to the output of the first element OR.

The drawing shows a block diagram of the proposed device for recording information.

The diagram contains the operator's console 1 register of 2-addresses, sensors, control unit 3, sensor selection block 4, keyboard 5, buffer register 6, sensors 7, receivers 8, receiver selection block 9, receiver address register 10, memory block 11, decoder 12 addresses, register 13 addresses of the memory block, first comparison block 14, decoder 15 service characters, buffer register 16 addresses of the memory block, second comparison block 17, word end address register 18, third block 19 compared. First, element 20 OR, the first element 21 AND and the second element 22 AND, the second element 23 OR, t Element 24 OR or trigger 25.

The paRoTaeT device is as follows.

At the beginning of the operation, the operator using the remote control 1 sets the program of operation of the device and the structure of the input information, which determine the order of operation of the sensors 7 and receivers 8. In the process of data recording, information, accompanied by clock pulses, is character-by-character coming from sensors 7 through the buffer register 6 The memory unit 11 and the control signals from the control unit 3 are determined to the corresponding receiver 8, to which information is sent for recording it on a printed document or on a punched tape.

From the output of the control unit 3, signals are received to enable the operation of the respective sensors 7 sequentially through the register 2. Of the sensor addresses and the sensor selection unit 4.

According to the enable signal of a certain sensor 7, indicated on the operator panel display (not shown), the operator enters the permanent information into memory block 11, for example, the width information of the workshop, section, part width, operator personnel number

The variable part of the Formed message, for example, the number of parts manufactured on the site, arrived at the warehouse, etc. is entered into block 11 from the keyboard 5 after entering information from sensors 7 in accordance with the input program. The input from the keyboard 5 is made using the control by the method of DOUBLE input and using a predetermined program of the bit grid of the recorded words. Moreover, the program records the address of these delimiters in the general structure of the Loriated message.

Upon receipt from the control unit 3 of the signal resolution of the call of sensor 7, block 4 generates a signal to call the sensor, which enters the input of such sensor 7 information, whose address was recorded either from the operator console 1, or from control unit 3 to the register 2 of the sensor addresses.

Information is entered into the memory block 11 through the buffer register. 6 for dinrhythms from sensors 7 through element 20 OR. Moreover, the code address of the cell of the memory block into which the character is written, oyred - is registered by the register of 13 addresses of the memory block whose output is connected to the decoder 12 of the address. At the end of the sync pulse, the buffer register 6 is reset and the first input of the first element 21 I, if there is a resolution in the initial state, with a single output of the trigger.

25, a modification of the state of the register of the memory block address 13 is made.

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The register 13 of the addresses of the memory block can be made in the form of a double reversible counter, in which the direct counting occurs when a signal arrives at its first input. The count output from the first element 21 Kf and the countdown occurs when it arrives at its second input.

0 signal Count - from the output of the second element 22 I-, while the output register of the address 13 is the cell address code of the next character entered in the memory block 11 from the sensor 7. The input cycle repeats until the service 7 is received from sensor 7 The symbol means the end of the input from the carrier. At the same time, the service symbol is decrypted by decryptor 15, and on a signal from its output, control unit 3 proceeds to input information from the following sensors 7. Clog 3 clears all registers and removes the input resolution from this sensor 7.

five

Next, the control unit 3 generates a call-enable signal for receivers 8, according to which the receiver selection unit 9 generates signals

Call the receiver and send them

0 to those receivers 8 whose addresses are recorded from block 3 in register 10.

After that, the clock pulses of the receivers 8 through the element 20 OR the output of information from

5 memory block 11 through buffer register b. At the end of each clock pulse, through the element 20 OR and the element 21 And the register 13 of the address of the memory block changes its state to

0, and the output of the decoder 12 is the code of the next cell of the input character. The cycle of outputting the information of the symbols to the receivers repeats until the output of the decoder 15 does not receive a signal about the decryption of the service symbol completing the registration of the entered information from this sensor 7,

During the next interrogation of the program from the control unit 3, the call enable signal of the next sensor 7 will be received, and the cycle of entering information in the memory And output unit and receivers 8 will repeat as described. Moreover, according to the program, such an input mode is also possible, when input of information in block 11 is possible immediately from all sensors 7, and then its serial output to receivers 8.

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The end of entering information from sensors 7 into memory block 11 and outputting it to receivers 8 is determined by a decoder 15, at the output of which a signal appears when the divider information divisors enter the buffer register b and the control unit 3 generates a control signal to the register 2 of the sensor addresses and the sensor selector block 4 to generate a signal; a keypad call, according to which the message on the operator console lights up: a message from the keypad and the signals of the control block 3 erase the contents of the register The 13 addresses of the memory block, the register 18 of the address of the end of the word, the buffer register B, and the reset of the trigger 25. At the next interrogation of the program from the control block 3, the address of the information separator completing the first entered word from the keyboard 5 is written into the register 18 of the end word address 18, Thus, in the register 13 of the addresses of the memory block, there is the code of the cell of the block of code, from which information will be sequentially entered into the memory block 11 during the initial dialing from the keyboard 5. The operator performs the first set from the keyboard 5, transferring the data from the flax prepared documents in the memory unit 11, the character-entry information received from the buffer register B to the first inputs of the memory unit 11 occurs on the sync pulses via OR element 20 at one input from block 11 the memory. The cell number of the memory block where the symbol is entered is determined by the register 13 of the addresses of the memory block through the decoder 12 address. At the end of the sync pulse from the keyboard 5, through the element 20 OR and the element 21 and the register 13 of the addresses of the memory block changes its state, thereby preparing at the output of the decoder 12 the code of the cell of the memory block 11 into which the next character will be entered. This order of operation continues until the operator dials the service symbol for the end of a word, the symbol is written into the buffer register b, and the output of the word is outputted at the output of the decoder 15. According to this signal, the control unit 3, in a clock cycle preceding the symbol write cycles in the 11th unit, and the state change, the register 13 of the memory unit addresses issues the interrogation signal of the second unit 17 for comparison, the address recorded in register 13 addresses of the memory block with the code of which block 11, to which the word csznets (separator, information) must be written, with the code of the cell recorded in the register 18 of the end word address when polling the program first Entering the first word from the keyboard 5 If the block 17 comparisons with this survey generates a signal C format to the first input of the second element 23 OR and to one of the inputs of the control unit 3, then by the second input the trigger 25 is set by this signal, coming from the output of the OR element 23, to the state when from its output to the second input of the element 22 AND The pulse enable signal by the control unit 3 to the first input of element 22I. Register 13 begins to modify its state every time another pulse arrives at its second input through element 22 And until the current state of register 13 addresses b flash memory does not match the contents of the buffer address register 16, which has been recorded the address of the first cell of the first input word. At the same time, the output of the third comparison unit 19 to the first input of the third element 24 OR a reset signal for trigger 25 arrives. After resetting trigger 25, the flow of pulses Count - to the input of the register 13 of the address of the memory block through element 22 And stops. On the operator's console 1, a banner appears. Format failure. ({Not shown in the drawing). The operator repeats the input of a word from the keyboard 5, starting with the first character. If the service character, the terminating word, is entered at its address, then when interrogated by the control unit 3 of the comparison block 17, the format failed signal is not at the output of the OR element 23, and the control block 3 in this case sequentially overwrites the signals: kept the address register 13 into the buffer register 16, Write the address of the next end of the word to register 18. (In the cycles preceding these signals; the contents of the said registers are extinguished). These signals in the buffer register of addresses 16 will contain the code of the cell from which the characters of the second layer will be output, and in the register of the address of the end of the word 18, the code of the address of the cell into which the end of the second word (information separator) will have to be written when typing 5 Similarly to the previous one, the subsequent characters and words are entered from the keyboard 5 in the memory block 11 to form a message; . The input process in the Set 1 mode from the keyboard 5 continues until a service character is written to the buffer register 6, signifying the end of the first set from the keyboard 5. At the output

The decoder 15 generates a signal. A laboratory end arrives at one of the inputs of the control unit 3, which sequentially generates the register blanking signals of the cell address in which the first character of the first word entered from the keyboard 5 is written. At the operator's console 1, the Set 2 banner lights up.

These signals in the buffer register 16 will have the cell address of the first entered character of the first word from the keyboard 5, and at the next polling from the control unit 3 in the end address register 18 there will be the cell code where it should be. recorded information separator, completing the first input word.

The operator continues to enter information from the keyboard in the Set 2 mode. Information from the keyboard 5 enters the character register buffer 6, and the sync pulse through element 20 OR compares the contents of memory block 11 with the contents of buffer register 16 on the first comparison block 14. Commands to write a character in the memory block 11 are not issued by the control block 3.

If the characters do not match (i.e., the characters of the first and second sets of information do not match), then from the output of the comparison unit 14 to the input of the control unit 3 and the second input of the element

23OR A signal is received. At the same time, on the operator’s console 1, a incomparability lights up, and the second input of the trigger 25 through the second element 23 OR a signal will be received that will set the trigger 25 to the state when the third input of the element 21 will be blocked by the second input of the 21 I.

In this case, the change in the state of the register 13 is blocked and the code of the former cell of the memory block 11 remains in it. At the end of the clock pulse, unit 3 issues a reset of trigger 25 through the second input of the third element.

24OR. The operator re-enters the already correct character at the cell address of the memory block 11, where there was a mismatch.

If the characters match in the first and second sets, after their comparison at the end of the clock pulse, the address register 13 changes its state to and from the output of block 11, because the cell code through the address decoder 12 has changed, the second character entered parts of the message from the keyboard 5. Now, when entering the second character, the comparison cycles are repeated. This continues until the operator dials the service character, which

is decoded by the decoder 15 as the end of the second set from the keyboard 5. This signal is fed to the input of the control unit 3. The latter clears all registers and removes input permission from keyboard 5.

The control unit 3 generates a call-enable signal for receivers 8, according to which the receiver selection unit 9 generates a call signal

0 receiver and sends them to those receivers 8, whose addresses are currently recorded from block 3 to block 11.

After that on sync pulses

5 receivers 8 through the element 20 OR the output of information from the memory block 11 is organized through the BuLer register 6. At the end of each sync {through a) through, element 20 OR n

0 element 21 And register 13 changes em

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and at the exit

your condition on

Descrambler 12 is the code of the next cell of the displayed character. The cycle of the output of the Inform symbols and to the receivers is repeated until

5 while the output of the decoder 15 does not give a signal from the decoding of the service character completing the registration of the entered information from the keyboard 5.

0

After this, the control unit 3 processes the firmware reset to which the entire device has returned to the initial state. The cycle of normalization and recording of the message with the correction when you enter from the keyboard 5 is over.

After the processing of the firmware is returned to the initial state, the device is ready for further work.

Thus, the operator receives information about his mistakes (corresponding signals are highlighted) and can correct them, entering the correct

5, the value of the corresponding symbol and without a new input, a previously formed part of the message and without a set of the address of a fixable sim wave. This reduces the amount of injected

0 characters when correcting errors and increases the productivity of the operator in the conditions of real work with errors and increases the reliability of his work.

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Claims (2)

Invention Formula A device for registering information containing a serially connected operator console, a register of sensor addresses, a sensor selection unit, sensors and a keyboard, a buffer register connected to the first comparison block, to the decoder of hearing characters, and a black memory to the address decoder, receivers, block receiver selection and the receiver address register connected to the operator’s console and control unit, the control unit being connected to the operator’s console, the registers of the addresses of sensors and receivers, the units of choice of sensors and receivers, the first comparison block, the decoder of service symbols, the memory block, the buffer register and memory 11, in order to increase the recording accuracy by controlling the format of the entered information, the first OR element, whose inputs are connected to sensors, is inserted into the device viature and receivers, and the output is connected to the memory block, the word end address register connected to the control block, the memory block address register, the second and third comparison blocks, and the memory buffer address register are connected first and second elements AND whose outputs are connected to the address register of the memory unit, and the first inputs to the control unit, the second: OR element, whose inputs are connected to the first and second comparison blocks, the third OR element, and which is connected to the third unit of comparison and to the control unit, the trigger, the inputs of which are connected to the outputs of the second and third elements OR, and the outputs to the second inputs of the first and second elements AND, the third input of the first element AND connected to the output of the first element and OR. Sources of information taken into account during the examination 1. USSR author's certificate No. 484515, cl. G 06 F 15/00, 1977. 2. USSR author's certificate number 468271, cl. G 06 K 15/02, 1977 (prototype).