SU725209A1 - Pulse shaper - Google Patents

Description

The invention relates to a pulse technique and can be used in digital computing machines and automation devices. A single pulse generator is known, which contains a trigger with separate inputs, a trigger with counting inputs, a bipolar intermediate switch and an output match 1, The disadvantages of this generator are low reliability, since it generates a shortened pulse at the output in those cases when the bipolar switch is triggered after the arrival of the leading edge of the next pulse from the pulse sequence, as well as a narrow area of its application, since it does not allow pulses or series of pulses. The closest technical solution to the invention is a single pulse shaper comprising a logic signal switch, a start trigger, input and output triggers, a feedback trigger, five AND-NES elements and two inverters 2. The disadvantage of this driver is its great complexity and bad synchronization as the clock pulses go to the output of the driver, pre-passing through four consecutive elements AND-NOT, which causes a large shift of the pulses at the output of the forms atel with respect to the f pulses of the clock frequency. The purpose of the invention is to improve synchronization while simplifying the former. The goal is achieved by the fact that the driver; containing a trigger trigger, the inputs of which are connected to the switch contacts of a logic signal, and a single output connected to the R inputs of the input and output triggers, an element And whose output is connected to input C of the output trigger, outputs I and To which are connected to the control bus, and zero output - with the first input of the element And the second input of which is connected to the clock frequency bus and input C of the input trigger, - input To of which is connected to its zero output.

A single output - with the third input of the element I.

The drawing shows a structural diagram of the pulse former.

The pulse former contains a trigger 1, the inputs of which are connected to pins 2 and 3 of the switch 4 of the logic signal, and a single output is connected to the R inputs of the input and output triggers 5, b. The zero output of the input trigger 5 is connected to its output K, and the single output is connected to the third input of element 7. 7. The input C of the input trigger 5 pd is connected to the bus 8 clock pulses and to the second input of the element 7, the first input of which is connected to the zero output of the output trigger 6. The output element And 7 is the output 9 of the former and is connected to the input C of the output trigger 6, the inputs I and K of which are connected to the control bus 10, Contacts 2.3 through the resistors il, 12 are connected to the voltage bus 13, bias, .

The pulse shaper operates as follows

In the initial state from pin 3 of switch 4 to trigger input

1 A logical input signal is generated on the resistor.

12 connected to the bias voltage 13 bias, and the input R signal of the logical zero from the contact

2 and resistor 11, Trigger 1 triggers the input and output triggers 5.6 to the zero state. Element And 7 is closed on the third input signal of a logical zero, coming from a single output trigger 5, on the bus 10 pack {

. a signal of the logical unit is applied: /: - :. ,

When contact 2 is opened and contact 3 is closed, trigger 1 is triggered, the zero signal is removed from the inputs R of the input and output triggers 5, b. Trigger edge 5 is triggered on the falling edge of the pulse arriving from bus 8, opening element 7 and blocking with a logic zero signal coming from zero output to input K. on the entry C of the trigger b, set it on the falling edge in the unit state. The logical zero signal from the zero output of the trigger b closes on the first input element And 7, prohibiting the passage of clock pulses to the output 9 of the driver. Upon opening of contact 3 and closing of contact 2, the driver returns to its initial state.

If it is necessary to obtain a series of pulses at the output of the shaper 9, then in the initial state, the control bus 10 is given the command

 Signal zero signal, which blocks the inputs I and K trigger b. After switching switch 4 and setting trigger 1 1 to one state, the second and all subsequent pulses pass from bus 8 through

5 element and 7 on. Exit 9 shaper. The first after the removal of the logical zero signal, the impulse sets the trigger b into one state, closing the element And 7 on the first

0 input and prohibiting the passage of the so Bbix pulses to output 9 of the driver.

Thus, with a simpler

: the driver can generate both single pulses and their series. This improves synchronization, since the delay of the pulses at the generator output compared to the clock pulses is equal to the response time of only 0 of one element And:

Claims (2)

Invention Formula Pulse builder containing a trigger trigger whose inputs 5 is connected to the pins of a logic switch, and a single output is connected to the R inputs of the input and output flip-flops, characterized in that Q improvement of synchronization while simplifying the driver, an element I is inserted into it, the output of which is connected to input C of the output trigger, inputs I and K of which are connected to the control bus, and zero output is connected to the first input of the element I, the second input of which is connected to the clock bus frequency and input C input trigger, the input of which is connected to its zero output, and 0 single output - with the third input of item No. Sources of information taken into account in the examination 1, USSR author's certificate 5 5 2bSS, cl, H 03 K 3/84, 24.06,75, .. 2. USSR author's certificate 570189, cl, H 03 K 3/78, 02.04.76,