SU624352A1 - Digital pulse generator - Google Patents

Digital pulse generator

Info

Publication number
SU624352A1
SU624352A1 SU772475720A SU2475720A SU624352A1 SU 624352 A1 SU624352 A1 SU 624352A1 SU 772475720 A SU772475720 A SU 772475720A SU 2475720 A SU2475720 A SU 2475720A SU 624352 A1 SU624352 A1 SU 624352A1
Authority
SU
USSR - Soviet Union
Prior art keywords
input
trigger
inputs
divider
logic
Prior art date
Application number
SU772475720A
Other languages
Russian (ru)
Inventor
Анатолий Алексеевич Белезин
Original Assignee
Предприятие П/Я В-2969
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Предприятие П/Я В-2969 filed Critical Предприятие П/Я В-2969
Priority to SU772475720A priority Critical patent/SU624352A1/en
Application granted granted Critical
Publication of SU624352A1 publication Critical patent/SU624352A1/en

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Claims (2)

  1. (54) The DIGITAL PULSE GENERATOR is connected to the second inputs of the frequency healers. The drawing is a functional diagram of the proposed digital pulse generator. The digital pulse generator contains the first and second logic elements 1 and 2 connected to the first inputs of the first and second dividers 3 and 4 of the frequency, respectively, their outputs are connected via the logic element OR 5 to the counting input of trigger 6, the outputs of the latter are connected to the first inputs of logic elements 1 and 2, the second inputs of which are connected to the output of the master oscillator 7, the input 8 of the zero setting trigger 6 is connected to the second inputs of dividers 3 and 4. The generator works as follows. A zero setting impulse is input to the zero setting 8, which converts the bits of the dividers 3 and 4, the trigger 6 to the zero state, and the voltage level corresponding to 1 arrives at the input of element I 1 from the inverse output of trigger b, and the input of element And the 2-level voltage corresponding to O. The second inputs of logic gates And 1 and 2 receive pulses from the master oscillator 7. At the end of the zero-state setup pulse, divider 3 starts the pulse sequence from the master oscillator. 7 through the logical element I 1 and the 4 does not change its state. At the end of division, divider 3 is at its output. A pulse appears, which through the element OR 5 changes the state of trigger 6 to the opposite, and the generator state changes as follows: the input voltage of the logic element AND 2 comes from trigger 6 , corresponding, and to the input of the logical element I 1 is the voltage level, corresponding to O. In this case, divider 4 starts division, and divider 3 does not change its state. At the end of the division, a pulse appears at the exit of the divider 4, which changes the state of trigger 6 through the element OR 5 to the opposite. The divider 3 is again connected to the master oscillator 7 via the AND 1 logic element, and the divider 4 is turned off and the process is repeated. Thus, at the output of flip-flop 6, a periodic is formed — the rectangular-shaped voltage, the duration of the long part of which is equal to Hi Td, and the duration of the other part of the period is equal to Rt, where f M is the division factors of divisors 3 and 4, respectively; TO is the period of the reference voltage of the master oscillator 7. Due to this switching on of the outputs of the frequency dividers through the logical element OR to the counting input of the trigger, the digital pulse generator circuit has a simple structure. In addition, if it is necessary to increase the period and (or) the duration of the output voltage, only the number of bits of the frequency divider increases, and the rest of the circuit remains unchanged and not complicated. DETAILED DESCRIPTION OF THE INVENTION A digital pulse generator comprising a master oscillator, two AND elements and a trigger, one of the outputs of which is connected to the first input of the first logical element AND, another output to the first input of the second logical element AND, the second inputs of which are connected the fact that, in order to simplify the device, two frequency dividers and an OR gate are introduced into it, with the outputs of the first and second AND gates, respectively, connected to the first inputs of the first and torogo frequency dividers whose outputs via a logic OR element connected to the count input of the flip-flop, the input of which is connected a zero setting to second inputs of the frequency dividers. Sources of information taken into account in the examination: 1. The copyright certificate K 420097, cl. And OZ K 1/18, 03.20.72.
  2. 2. US Patent No. 3805167, cl. 328-61, 1974.
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SU772475720A 1977-04-15 1977-04-15 Digital pulse generator SU624352A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU772475720A SU624352A1 (en) 1977-04-15 1977-04-15 Digital pulse generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU772475720A SU624352A1 (en) 1977-04-15 1977-04-15 Digital pulse generator

Publications (1)

Publication Number Publication Date
SU624352A1 true SU624352A1 (en) 1978-09-15

Family

ID=20704841

Family Applications (1)

Application Number Title Priority Date Filing Date
SU772475720A SU624352A1 (en) 1977-04-15 1977-04-15 Digital pulse generator

Country Status (1)

Country Link
SU (1) SU624352A1 (en)

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