SU624295A1 - Storage cell for homogeneous matrix structure - Google Patents

Storage cell for homogeneous matrix structure

Info

Publication number
SU624295A1
SU624295A1 SU762398612A SU2398612A SU624295A1 SU 624295 A1 SU624295 A1 SU 624295A1 SU 762398612 A SU762398612 A SU 762398612A SU 2398612 A SU2398612 A SU 2398612A SU 624295 A1 SU624295 A1 SU 624295A1
Authority
SU
USSR - Soviet Union
Prior art keywords
information
cell
bus
cells
matrix
Prior art date
Application number
SU762398612A
Other languages
Russian (ru)
Inventor
Валерий Федорович Гусев
Геннадий Николаевич Иванов
Владимир Яковлевич Контарев
Генрих Исаевич Кренгель
Вячеслав Яковлевич Кремлев
Мансур Закирович Шагивалеев
Юрий Иванович Щетинин
Азат Усманович Ярмухаметов
Original Assignee
Предприятие П/Я В-2892
Предприятие П/Я А-3886
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Предприятие П/Я В-2892, Предприятие П/Я А-3886 filed Critical Предприятие П/Я В-2892
Priority to SU762398612A priority Critical patent/SU624295A1/en
Application granted granted Critical
Publication of SU624295A1 publication Critical patent/SU624295A1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/414Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the bipolar type

Description

The invention relates to the field of automation and computer technology and is intended for use as a functional element of universal and specialized homogeneous structures (computing environments).

Known memory cells for a matrix of uniform structure containing a trigger, information and address buses, an additional tunable element.

Information buses are used in setup mode l.

The disadvantages of well-known memory cells are the impossibility of working in several directions with one trunk and limited functionality due to the organization of the cell output.

Of the known ones, the closest technical solution is a memory cell, the D-trigger output of which is connected to the first inputs of the NAND elements, the second inputs of which are connected to the read address buses,

and the outputs of the AND-NOT elements are connected to the corresponding information inputs of the D-flip-flop .2.

In addition, this memory cell has neki e performance characteristics when combining cells into large-capacity matrices, which is necessary when building devices for processing data such as computers.

The goal of the {} study is to improve the exploitation. characteristics by providing autonomous control capability when combining cells into a uniform matrix structure.

This goal is achieved by introducing into the proposed cell of memory elements of NOT (compensated inverters), the inputs of which are connected to the write address lines, and the outputs to the corresponding information inputs of the D-rigger.

FIG. 1 shows a memory cell for a matrix homogeneous structure; in fig. 2 - merging cells into a matrix.

Drngger 1, shown in FIG. 1 dotted line, connected by address inputs 2 entries to elements 3 NOT (compensating inverters), the inputs of which are connected to address buses; 4. records. Other inputs 5 D-flip-flop 1 are connected to information bus 6 and to the outputs of 7x-AND-NOT elements, the first inputs of which are connected to output 8 of D-rigger 1, and their other inputs are connected to address buses of 9 readouts. The cell works as follows. Recording by EYI | worm; ash1I into the cell is carried out from the information bus 6 by sending recording signals to the address bus 4 records. The signals from the corresponding address bus 4 through the elements 3 do NOT allow reception of information from the information bus 6 on the D-trkgger 1 I11 from the information bus 6. To read 1 and the information from one cell on the information bus 6, send the input signal to the address bus 9 of the corresponding element 7 and “NOT. At the same time, the information bus 6 connected to the output of element 7 will have a potential corresponding to the evdium content of the D “trigger recorded previously from the same data bus 6 or from any other of the information bus 6. Cell 1O of the uniform matrix of the unified structure in the matrix (see FIG. 2, the same outputs of the eyelids 10 are interconnected with each other using information buses 6, from which you can record both in the 10 and 2 readings on the data buses 6. Address addresses of the 1O cells are connected using address buses 4 readout and address bus 9. Readout information is processed in the matrix is carried out in the process of transmitting information on information 6 from the cell to the cell or while several cells Y are working simultaneously. For example, the logical AND operation is performed by simultaneously reading the corresponding information bus 6 the content of two cells of Yu at once. At the same time, single information on informational tires 6 remains only in those digits of the matrix, ya, which are simultaneously read units. In the same bit for which at least one zero was read. remains. zero information. The OR operation is performed by simultaneously recording information from different information buses 6 into one cell 10. At the same time, if at least one unit exists on any of the information bus lines 6, it is recorded in this cell 10. Reassembly operations are performed on cell 1O , the various outputs of which are biased with information buses of 6 other columns of the matrix (in Fig. 2, see the bottom row of the matrix). For example, right-shift operations are performed by writing to this line on the first inputs of cells from the first information bus b, and reading — on the second output to another information bus 6 — left-shifting - in the reverse order. Information transfer operations are performed by reading the contents of one cell 10 and writing to another, with the transmitting cell 10 being the source, and all the others on this information 6 are receivers. At the same time, it is possible to send information between other cells; You are sent via another data bus 6, between the third group of cells (which partially Morjrx is included in and already working on other tires) cells are sent over the third bus 6, etc. In order to receive a network each with each need to have as many inputs and outputs at the cell as there can be transfers at the same time. It has been experimentally proven that to build a computer processor it is necessary and sufficient to have a chey with three outputs. At the same time, the first operand is sent over one bus, the second operand is sent over the other bus, and the result of the processing is transmitted over the third one. However, the number of cells connected to the buses is limited. Output elements 7 AND have NO limited load capacity, and very large. The power elements at the output lead to a significant degradation of the output signal parameters. C brtHo accepted that the elements of mo. Can be loaded on 10 similar elements. And although in the matrix all the connected cells 10 cannot be consumers at the same time, nevertheless, each D-flip-flop input requires 1 1/2 of the load. To eliminate this drawback, additional elements 3 are NOT (compensating inverters). The parameters of these inverters are selected so that the potential at their output in the closed state, i.e. when there is no entry in this cell 10, it is significantly lower than the potential on the information bus b, and so on the other input of D-flip-flop 1. The currents are redistributed in such a way that the current consumption from the information bus 6 is significantly less than 12 loads. Thanks to this, it became possible to connect to the information bus 6 of a considerably larger number of cells 10, which improves the performance characteristics of the cells. The additional inclusion of inverters into the cell is not an explicit application (they are usually used to reduce the power consumption of the control signal) and the choice of a cell at their output below the potential on the information buses 6 allowed to achieve a positive effect o (coupling to the bus of a large number of cells. The use of additional elements 7 I-NOT at the output of the first cell allowed us to increase the functionality of one's ki, combining them into a matrix with independently working information buses with autonomous control. The agaem cell can be implemented by means of Microelectronics i and moheset used in the Unified system of electronic computers of socialist countries (EU.COM). The use of the cell will allow: to increase the fast-J operation model to 1 million 7 copier .1

About about a rotary format per second, it is possible to reduce the amount of equipment (three times). The formula for acquisitions A memory cell for a matrix unanimous structure containing D-griggr, the output of which is connected to the first VHSU of I-NOT elements, the second inputs of which are connected to the address tracing buses, and the outputs of the JohnEme elements are connected to the corresponding information inputs of the D-trigger, About 8 hours per second with the fact that, from the peleo, the operational characteristics of the PC are improved by providing the possibility of autonomous control when combining the cells into a matrix homogeneous structure, it contains NOT elements which are connected to the address Ghana th recording and outputs - to the corresponding inputs of the D-vaformaonoschnym trnggera. Sources of information, taken into account during the examination: 1. USSR author's certificate No. 395832, (F 7 / OO, 1971. 2. USSR author's certificate No. 486376, q 11. C 11/40, 1973.

9 b

9

ten

Fto

fff

SU762398612A 1976-08-17 1976-08-17 Storage cell for homogeneous matrix structure SU624295A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU762398612A SU624295A1 (en) 1976-08-17 1976-08-17 Storage cell for homogeneous matrix structure

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
SU762398612A SU624295A1 (en) 1976-08-17 1976-08-17 Storage cell for homogeneous matrix structure
IN1197/CAL/77A IN147561B (en) 1976-08-17 1977-08-04
PL20013977A PL109105B1 (en) 1976-08-17 1977-08-09 Homogenous matrix structure cell
DE19772736061 DE2736061C2 (en) 1976-08-17 1977-08-10
JP9518977A JPS5341139A (en) 1976-08-17 1977-08-10 Uniform matrix cell
DD20053677A DD132688A1 (en) 1976-08-17 1977-08-11 Cell of homogeneous matrix structure
BG7737170A BG30596A1 (en) 1976-08-17 1977-08-15 Cell of matrix homogenous structure
FR7725004A FR2362471B1 (en) 1976-08-17 1977-08-16
GB3440677A GB1545338A (en) 1976-08-17 1977-08-16 Matrix logic cell
RO7791379A RO73483A (en) 1976-08-17 1977-08-16 The cylinder of a momental matrix structure

Publications (1)

Publication Number Publication Date
SU624295A1 true SU624295A1 (en) 1978-09-15

Family

ID=20674913

Family Applications (1)

Application Number Title Priority Date Filing Date
SU762398612A SU624295A1 (en) 1976-08-17 1976-08-17 Storage cell for homogeneous matrix structure

Country Status (10)

Country Link
JP (1) JPS5341139A (en)
BG (1) BG30596A1 (en)
DD (1) DD132688A1 (en)
DE (1) DE2736061C2 (en)
FR (1) FR2362471B1 (en)
GB (1) GB1545338A (en)
IN (1) IN147561B (en)
PL (1) PL109105B1 (en)
RO (1) RO73483A (en)
SU (1) SU624295A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60226090A (en) * 1984-04-25 1985-11-11 Nec Corp Static random access memory circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3638204A (en) * 1969-12-19 1972-01-25 Ibm Semiconductive cell for a storage having a plurality of simultaneously accessible locations
US3675218A (en) * 1970-01-15 1972-07-04 Ibm Independent read-write monolithic memory array

Also Published As

Publication number Publication date
JPS5341139A (en) 1978-04-14
PL109105B1 (en) 1980-05-31
GB1545338A (en) 1979-05-10
DD132688A1 (en) 1978-10-18
FR2362471B1 (en) 1980-07-11
PL200139A1 (en) 1978-04-24
DE2736061C2 (en) 1982-05-06
IN147561B (en) 1980-04-12
BG30596A1 (en) 1981-07-15
DE2736061A1 (en) 1978-02-23
FR2362471A1 (en) 1978-03-17
RO73483A (en) 1981-11-04

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