SU468236A1 - Code Conversion Device - Google Patents

Description

(54) DEVICE FOR TRANSFORMING CODES

one

The invention relates to the field of automation and computer technology and is intended for converting digital codes from one number system to another. A device is known for converting a binary code into a binary-decimal one consisting of two pulse counters and a pulse generator.

However, such a device has a large code conversion time equal to | t4T

(N is the number to be converted, T is the pulse period).

The purpose of the invention is to reduce the time for converting a binary code of a number into a binary-decimal code, i.e., to increase the speed of the device.

This is achieved by the device co, holding additional AND and OR circuits, the additional AND circuit input, and connected to the outputs of the pulse generator and the first AND circuit, the output of which is connected to the input of the second AND circuit, the output of the additional circuit AND AND of the binary counter CTapuiHx bits and additional schemas.

we or, with another input connected | .output of the binary-decimal counter of the least significant bits, the output of the additional circuit OR. is connected to the input of the binary-decimal

5. Senior bits.

The drawing shows a diagram of the proposed device.

The device contains binary-decimal counters of the low-order bits 1 and the upper-half bits 2, binary counters of the younger ones: bits 3 and high bits 4, the generator of pulses 5, circuits AND 6-9, OR 10, inverter 11 and the bus FlycKf 12.: The binary and binary-decimal counters are divided into parts so that the capacity of the NO (binary digits) of the low-order counter 3 is insignificantly different from the capacity of M)

the binary-decimal counter of the lower-order ranks 1 (the counter capacity is the maximum number that can be written in the counter). The capacities of binary and daoic-decimal counters of the higher bits 4 and 2 are denoted by

NI and M, respectively. 1 The device operates as follows in the initial state in the counters 3 and 4, the numbers HQ and tl-j are written corresponding to the binary code being converted, and the counters 1 and 2 are set to the zero state. In this case, the output potential of the circuit And 7 appears prohibiting potential, if in the counter 3 is written any number that is different from zero. Under the Start command, the pulses from output 5 are fed through the AND 6 circuit to the meter input of the subtraction of counter 3 and to the counting input of the addition of counter 1 and the units are subtracted from counter 3 and the units are added in counter 1 (one pulse for each) until counter 3 is set to zero. Thus, the number nQ is transferred to the eV counter 1 If the capacity of the counter 1), then a transfer unit occurs, which enters the counting input of the counter 2 stacked bits through the OR 1O scheme.: And in the counter 1 remains the number Shd Tl, .- 11 Q. If the IQ MO of the counter 1 remains the number tnQ, the permissible potential appears at the output of the circuit AND 7, and the forbidden potential appears at the output of the inverter 11. The impulse from the output of generator 5 passes through the AND 8 circuit and subtracts the unit from the 4 high-order counter, adds one to the 2 high-end counter and sets the number in the 3 counter. At the output of the AND 7 circuit, the inhibitory potential appears, and the output of the inverter 11 permitting potential. The next pulse train subtracts the number NQ-MQ from counter 3 and adding the number N Q- to counter 1. If counter 1 overflows, the transfer unit enters the counter input of counter 2 through the OR 11 circuit. Further operation of the device occurs analog- Similarly: each pulse arriving at the inputs of counters 4 and 2 simultaneously sets the number of NQ-HQ in counter 3, after which the next series of pulses subtracts the number of counter 3 and adds it to the first number in counter 1, after subtracting the last one from the account snip 4 and followed by a number of counter 3 visode AND circuit 9 is to enable potential, which rules shvaet work generats pulses and 5, in this code conversion is completed. The total number of pulses that must be sent from generator 5 to the counters will be equal to Hp no n No-Mol. For example, to convert twenty-bit binary code into binary-decimal, binary and binary-decimal counters can be divided into two parts. so that in the binary bits of the binary counter there were 10 binary bits, and 1 VKOY113D: the binary bits of the decimal digit - 3 decades. Then MQ 10, and in the case of converting the maximum number from binary code to binary-decimal, time 1 is necessary: „m g By -1g | (Mo-Mo) 1T iT. e. Cgshg 11023 + 1023 (1О24-10ООООООО TJ 261O T ... In the case of the conversion of this number on a known device, time is required ГЬ |) 4 1023-1023 10® T. Obviously, the larger the value of the converted number N ( N 1023), the greater the gain in time is given by the proposed device. Object of the Invention A code conversion device containing binary counters of the lower and higher bits, the outputs of which are connected to the inputs of the first and second circuits AND, respectively, the output of the first AND circuit is connected via an inverter to the input of the third AND circuit, with another input connected to the output of the pulse generator, the output of the second circuit AND is connected to the control input of the pulse generator, the output of the third circuit AND is connected to the inputs of the binary and binary-decimal low-order counters, the binary-decimal high-order counter In order to improve speed, the device contains additional AND and OR circuits, the inputs of the additional AND circuit are connected to the outputs of the pulse generator and the first AND circuit, the output of which is connected to the input of the second AND circuit, the output of the additional AND circuit is connected with binary 1 counter input

older bits, with the installation input of a double-bit low-order counter, n an additional OR circuit, with another input of which is connected to the binary output

decimal counter for low-order bits, the output of the additional circuit OR is connected to the input of a binary-decimal counter for higher-order bits.

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