SU1753482A1 - Multichannel device for input, processing and output of information - Google Patents

Abstract

The invention relates to automation and computing and can be used in multichannel systems for transmitting and receiving discrete information in serial and parallel codes. The purpose of the invention is to increase the speed of the device. The device contains information inputs 1, 2, 3, trigger groups 4, 5, 6, pulse generator 7, counter 8, distributor 9, multiplexers 10, 11, demultiplexers 12, 13, 14, 15, memory block 16, decoder 17, comparator unit 18, address control unit 19, decoder 20, pulse generator 21, memory unit 22, recorders 23, setup input 24. The serial codes are transmitted by channels through inputs 3 to triggers 6. Transmission channel requests (L C h ( L 2 so y fig

Description

and the output of information is received by the triggers 4, 5. Triggers 4, 5, 6 are polled by counter 8 through multiplexers 10, 11. The recording of information bits and the conversion of serial codes into parallel ones are performed in memory block 16. The counting of the number of bits and bytes received or issued by the channels is performed in the address block 19. The storage of the received information and its output by the channels are provided

memory unit 22 through output registers 23. Memory units 16, 22 control unit 19 is performed by valve 9 through shaper 21, demultiplexers 13, 14, 15, decoders 17, 20, and block 18 comparing the number of bytes with the given one. After processing the requirements of the channels, the corresponding triggers 4, 5 are set to the zero position via the demultiplexer 12. 1, z p. f-ly, 4 ill.

The invention relates to automation and computing and can be used in multichannel systems for transmitting and receiving discrete information in serial and parallel codes.

A device for receiving information is known, comprising an actuator block, three counters, a pulse generator, a shift register, a comparison block, a switch, a register, a chronizer, pulse drivers, decoders, and OR, AND NOT, NOT elements

A disadvantage of the known device is that it only provides information input through one channel common to several information transmitters, which limits the possibility of using this device in multi-channel information receiving and transmitting systems.

Closest to the proposed technical entity is a multichannel device for collecting and processing information that contains sensors, a pulse generator, triggers, counters, a memory block, registers, a comparison block, pulse shapers, AND, OR elements.

In the known device, reception modes (recording information in a memory unit) and issuing (reading information from a memory unit) alternate sequentially, and the issuance modes are performed only after all channels are polled and discrete information is recorded, regardless of the presence or absence of information in them which increases the processing time of information and reduces the speed of the device.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 - distributor circuit; in fig. 3 - control unit diagram

addresses; in fig. 4 - time diagram of the device.

The device contains information inputs 1 (service requirements from

information receiving channels), inputs 2 (information output requirements), information inputs 3 (receiving information bits), trigger groups 4-6, pulse generator 7, counter 8, distributor 9, multiplexers 10 and 11, demultiplexers 12-15, block 16 memory, decoder 17, comparison block 18, address control block 19, decoder 20, pulse driver 21, memory block 22, resistors 23, setup input 24. Distributor 9 contains counter 25, decoder 26, HE element 27, switch 28, element AND 29, element OR 30. Block 19 contains a multiplexer 31, an adder 32, a switch 33 and register 34.

The device works as follows.

In the absence of signals at the inputs of multiplexer 10, a single signal from its output resolves the counting of generator 7 pulses in counter 8 and keeps distributor 9 in zero state. Counter 8 after switching on generator 7 sequentially through multiplexers 10 and 11 interrogates triggers 4-6, respectively.

Channels that transmit information place requirements on inputs 1, information in consecutive turns on devices. Channels requiring the release of information place requirements on inputs 2.

In this case, the triggers 4 and 5 are set to one, respectively, and the information triggers 6, to single or zero states, depending on the logical values (0, 1) of the information bits. Trigger 4 transmitting channels, for example, odd, triggers of 5 receiving channels - even, respectively, addresses of the channels formed by the counter 8 during polling

Triggers 4 and 5 for transmit and receive channels differ in the low-order bit value of the address. Depending on which of the current triggers 4 or 5 is polled by the counter 8, the device performs the reset or output modes, respectively. In this case, the demultiplexer 12, at the current address of the sitchik 8, selects the corresponding trigger 4 and 5 for setting it to zero. The demultiplexer 13 connects to its input only a group of outputs corresponding to the addresses of the channels transmitting information. The demultiplexer 14 connects to its input only a group of outputs corresponding to the addresses of channels requiring the issuance of information. The demultiplexer 15 for the addresses of the transmitting channels sets the information recording mode on the group of its outputs, and for the addresses of the requesting channels the information reading mode.

When polling, for example, triggered trigger 4, a zero signal is generated at the output of multiplexer 10, stopping counter 8 and triggering distributor 9. At the outputs of counter 8, the address of the n-th transmission channel is set. The bit of information from the output of the trigger 6 through multiplexer 11 is fed to the input of block 16. Distributor 9, depending on the control signal at its input, forms two control cycles: short or long. With short cycles, the accumulation of consecutive bits of information on a given received channel to a parallel byte occurs; during long cycles, the accumulated byte of information is recorded in memory block 22. The first pulse of the distributor 9 is fed to the demultiplexer 13, the group of outputs of which, corresponding to the addresses of the transmitting channels, is connected via a matching resistor to the power source. Therefore, a pulse is generated at the corresponding output of the demultiplexer 13, which ensures the recording of the first bit of information of the nth channel into the memory block 16, which is addressed to the output W by the counter 8. The second pulse of the distributor 9 is fed to the clock input of the address block 19. In block 19 the multiplexer 31, the adder 32, the switch 33 and the register 34 form a multi-channel counter of the number of bits and bytes of each transmitting and receiving channel. The number of bits and bytes are counted as follows. Information from the channels comes in the form of arrays of a certain length, which

determined by some setup code received at input 24 to comparison unit 18, the beginning of the array is marked by the marker code, which is decoded by decoder 17. Until the marker is received for the fifth channel, a single signal is generated at decoder 18 output. For the addresses of the transmitting channels, multiplexer 31 is connected to the input of the decoder.

17, therefore, a single signal is also generated at the output of the multiplexer 31, which is fed to the first input of the adder 32 and opens the switch 33. The adder unit 32 adds one to the number accumulated in the register 34, which is fed to the other inputs of the adder 32. The sum of the outputs of the adder 32 through the switch 33 enters the inputs of the register 34 and is fixed in the cell addressed by the counter 8 at the input

W of this register, by the signal of the distributor 9, which is fed to the C input of the register 34. This amount is read into the same register cell 34, which is addressed by the counter 8 to the input R of the register 34, and is fed to the inputs

adder 32 for modification in the following distributor 9 cycles, etc. Thus, in the following cycles of the allocator 9, upon receipt of the information bits of the nth channel,

The new number of bits in the corresponding register cell 34. After all the bits of the marker corresponding to the beginning of the n-th channel information array are received, the output of the decoder 17 generates a zero signal that closes the switch 38. In this case, the zero number - the beginning count the number of bits of the received data array.

The third pulse of the decoder 26 of the distributor 9 through the element And 29 polls the output of the decoder 20 bytes, which are supplied with three low-order bits from the outputs of register 34 of block 19. If the information byte is not accumulated on this n-th channel (three lower bits of the block 19 address are not if a single value is received), then a single signal is set at the output of the decoder 20. This signal opens the item

Both the 29 and the third pulse from the decoder 26 through the element OR 30 are fed to the input of the demultiplexer 12, switched by the counter 8 to the R input of the trigger 4-n, and the trigger 4-n is set to zero. With this again

a single signal is generated at the output of the multiplexer 10, which turns on the counter 8 for subsequent polling and sets the counter 25 of the distributor 9 to zero. The described process of polling the flip-flops 4-6 is repeated. The total polling time of triggers 4-6, taking into account the time of the long cycle of the distributor 9, is shorter than the period between requests exhibited by the channels 1-3, which eliminates the loss of information during its reception and processing. The accumulation of n-th channel bits in the corresponding cell of memory block 16, addressed by counter 8, is provided by feedback from the outputs of block 16 to a group of its information inputs shifted by one bit. In this case, each subsequent bit shifts the previous bit along This cell will be discharged before the nth channel information byte is accumulated in this cell. After accumulating the byte of the pth channel information in memory block 16, a zero signal is set at the output of the 20 bytes decoder, which closes the distributor 9 And 29. In this case, the distributor 9 performs a long control cycle, and the third pulse of its decoder 26 does not zero. trigger 4-p. The information bit from the output of the memory block 16 is fed to the D-inputs of the memory block 22, to the address inputs of which the address is fed from the outputs of the high bits of the counter 8 and from the high bits of the block 19. The high bits of the counter 8 determine the basic the address of the memory region for the nth channel, and the high bits of block 19 are the numbers of the bytes written or read from this memory region. The write control signal from the outputs of the demultiplexer 15-, which is determined by the addresses of the transmitting channels, is input to the W / R input of the memory block 22. The fourth pulse of the distributor 9 is sent to the shaper 21 of the callback access to the memory block 22 and the byte of information of the n-th channel is written to this block. The fifth pulse of the distributor 9 does not change the states of the outputs of the demultiplexer 14, since its address inputs are affected by the addresses of the transmitting channels. The sixth pulse of the distributor 9 through the element OR 30 and the demultiplexer 12 sets the trigger point 4-n to zero and the described process repeats. When polling, for example, a triggered 5-n trigger, the device goes into the mode of issuing information previously received for this channel. In this case, similarly to that described at the outputs of the counter 8, the address of the n-th receiving channel is set and the distributor 9 is started, the operation of which is similar to that described. The first pulse of the distributor 9 does not change the state of the outputs of the demultiplexer 13, since the address of the received channel acts on its address inputs. In block 19, the multiplexer 31, when supplied to its address inputs of the received channel, switches to from the output of the decoder 17 to the output of the comparison block 18. A single signal from the inverse output of block 18 is fed through multiplexer 31 to the input of adder 32, and the second impulse distributor 9 increases by one the content of the n-th cell of the re- 34 addressed by counter 8. Similarly, the third impulse decoder 26 of the distributor 9 polls the decoder 20 bytes and if the block 19 address does not correspond to the number of bits in a byte, the distributor 9 performs a short control cycle, after which the trigger 5-n is set to zero. If the lower digits of the block address are set to one, then the decay Rathore 20 closes AND gate 29 and the valve 9 performs a long control loop. In this case, the demultiplexer 15 at the address of the receiving channel generates at the output a read information signal input to the W / R input of the memory block 22. The fourth impulse 9 pulse through shaper 21 reads the information byte from memory block 22 to an address, which is also determined by the high bits of block 19 and counter 8. The read byte is fed to register 23-n selected by demultiplexer 14. And th pulse

0 distributor 9 provides writing bytes to the specified output register 23-p. The sixth impulse pulse 9, as described above, sets the trigger point 5-n to zero and the described process repeats. By

5, it determines the position of the read bytes in the information array.

After reading all the bytes of the array

0 the n-th channel at the output of the address block 19 is set to the code that matches the setup code of the input 24. In this case, from the output of the comparison block 18, a zero signal is output and, similarly to that described, in the current

At cycle 5 of the distributor 9, the corresponding cell in block 19 is zeroed out, and the nth channel re-receives the array of information. Repeated reading and receiving of information arrays by the nth channel and

0 comparison of the corresponding bytes in it ensures the required reliability of information transmission.

In the device, the alternation of modes of reception, processing and issuing information

5 is determined by the sequence of channel requirements. This ensures the reception of information in serial codes with its conversion into parallel codes and the issuing of information by channels in parallel codes. Arbitrary alternation of requirements from the transmitting and receiving channels allows reducing the time to bring information to the user, increases the speed of the device in the process of information exchange.

Claims (2)

The invention is 1, a multichannel device for collecting, processing and issuing information containing a pulse generator, a pulse distributor, a first multiplexer, the output of which is connected to the first input of the first memory block, a counter, the outputs of which are connected to the corresponding address the inputs of the first multiplexer, the control inputs of the first memory block, the decoder, the comparison block, registers, pulse generator, characterized in that, in order to improve speed, groups of triggers are introduced into it, the second cartoon and a plexor, a second memory block, demultiplexers, an address control block, a pulse generator output connected to the inputs of the first counters and a distributor, the trigger outputs of the first and second groups are connected to the corresponding the information inputs of the second multiplexer, the outputs of the third group triggers are connected to the corresponding information inputs of the first multiplexer, the outputs of the first counter are connected to the address inputs of the second multiplexer, the first, second, third and fourth demultiplexers and the address control block, the installation inputs of the first block memory, address inputs of the first group of the second memory block, address inputs of the first group of the second memory block, the output of the second multiplexer is connected to the installation inputs account the first output of which is connected to the information input of the second demultiplexer, the second output of the distributor is connected to the synchronizing input of the address control block, the third output through the pulse shaper to the first input of the second memory block, the fourth and fifth outputs are connected respectively to the information the inputs of the third and first demultiplexers, the outputs of the second demultiplexer are connected to the synchronization input of the first memory block, the outputs of which are connected to their like info mation entry The information inputs of the first decoder and the second memory block, the inputs of the first group of the comparison block are the installation inputs of the device, the output of the comparison block and the first decoder are connected respectively to the first and second control inputs of the address control block whose outputs are connected to the inputs of the second group of the block comparison, the address inputs of the second group of the second memory block, and the information inputs of the second decoder, the output of which is connected to the control input of the distributor, the outputs of the fourth demultiplier The lexor is combined and connected to the second input of the second memory unit whose outputs are connected to the information inputs of the respective registers, the outputs of the third demultiplexer are connected to the synchronization inputs of the corresponding registers, whose outputs are the device outputs, the trigger inputs of the first group and the synchronization inputs of the third group trigger are combined The first information inputs of the device, the information inputs of the triggers of the third group are the inputs of the device, the outputs of the first g a multiplexer connected to respective inputs of flip-flops mounting the first and second group of flip-flops inputs of the second group are second information inputs. 2. Device pop. 1, characterized in that the address control unit contains a multiplexer, adder, switch and register, the multiplexer output is connected to the first input of the adder and the control input of the switch, the inputs of the adder are connected to the inputs of the switch, the outputs of the switch are connected to the information inputs of the register, the outputs of which are connected by the inputs of the first group of the adder and are the outputs of the block, the inputs of the second group of the adder are combined with the power supply bus, the first and second inputs of the multiplexer are respectively the first and second channeling yuschimi block inputs and address inputs of the multiplexer control inputs of the first and second register groups are combined and are addressable unit inputs, a clock input register is timing input unit. ffXK (roq I