SU1736001A1 - Device for information transmission - Google Patents

Abstract

The invention can be used in automated systems. Control and management of technological processes and production. The purpose of the invention is to increase the speed of the device. The latter contains two switches, a reversible counter, a setup block, a clock generator, an AND element, an RS flip-flop, an OR element, a group of counters, a first algebraic adder, a nominal value memory block, a group of receiving blocks. Each receiving unit contains a clock pulse generator, an OR-NOT element, an initial setup pulse generator, a register, a delay element, a second algebraic adder, and a setpoint value generator. 5 il. S

Description

The invention relates to automation and computing and can be used to transmit information in automated systems of control and management of technological processes and production.

A device containing sensors of monitored parameters, connected via registers, a first switch and an element of coincidence with the bit inputs of the fourth register, the zero input of which is connected to the output of the second register, and the output with zero input of the first and single input of the second trigger, is known. The inverse outputs are connected to the inputs of the matching elements, and the direct outputs with the control inputs of the key elements, the clock generator,,

the output of which through one of the key elements is connected to the first input of the OR circuit, and through the other key element to the input of the second switch and the second input of the OR circuit, the output of which is connected with the counting inputs of the second and fourth registers, and the outputs of the second switch with the inputs of the third registers.

The information from the output of the polled sensor is written in parallel to the fourth register. Upon receipt of the trigger signal, the counting inputs of the fourth and second registers receive pulses from the generator. When the fourth register overflows, these pulses also arrive at the counting input of the third register corresponding to the sensor being polled. AT

with

317

the moment of the overflow of the second register and the third register of the code that was present at the output of the specified sensor at the time of launch.

The drawback of the device is that it has low speed due to the presence of two consecutive transfers of the same information (first from the input register to the intermediate, and then from the intermediate to the output), and low reliability, since the probability of transmission interferences exist both in the first and in the second sequential transfer of information.

The closest in technical essence to the present invention is a device comprising the first switch, the information inputs of which are connected to the outputs by a sensor of monitored parameters, and the address input is the first address input of the device, the reversible counter, the initial setup block, the OR element, the first input of which connected to the overflow output of the reversible counter, and the second input to the output of the setup block, an RS flip-flop, the input R of which is connected to the output of the OR element, and the input S is the trigger input element, the second input of which is connected to the output of the rs flip-flop and to the input of the permission to pre-record the reversing counter, and the output with the counting input of the reversible counter, clock generator, the output of which is connected to the second input of the element i, the second switch, information input which is connected to the output of the element AND, and the address input is the second address input of the device, a group of counters whose counting inputs are connected to the outputs of the second switch, a group of receiving blocks, information and time stems inputs and outputs are reset respectively connected to the outputs count input and a reset input of one of a group of counters. Each receiving unit contains serially connected clock generator and an OR-NOT element, initial setup pulse generator and register, whose information inputs are the information inputs of the unit, the control input connected

with the second output of the clock generator, and the zeroing input - with the output of the initial setting pulse generator and the first input of the OR-NOT element connected by the output to the output of the unit reset.

During operation, the initial pulse shaper produces a pulse that sets the preset mode of the reversible counter, prohibits the impulses generated by the generator to pass to the counter inputs, and the information from the polled sensor through the first switch goes to the reversible counter. The second switch connects to the reception information of the corresponding counter, and the receiving unit of the group. The trigger signal generates pulses at the counting input of a reversible counter and at the counting input of a connected group counter, which ensures the formation of a code corresponding to the output code of the polled sensor on the corresponding counter of the group at the moment of the reversing counter overflow. From the output of the group counter, this code with a certain delay is written to the register of the receiving unit of the group. The polling time for one sensor is determined by the formula:

2K

+ w,

(one)

BUT

where K is the decimal value of the maximum possible code transmitted by the device; T1 - the period of the pulse

generator output; C - the duration of the pulses generated by the shaper clock pulses.

This device also has a low speed. This is due to the fact that to record information, it is necessary to read a certain number of pulses corresponding to the input code. Therefore, for large values of the input code, the device has a low speed, i.e. the recording time of the input information on the registers of the blocks of the receiving registers depends on the value of the code being written.

The aim of the invention is to improve the speed of the device.

The goal is achieved by the fact that the device for transmitting information containing two switches, a reversible counter, an initial setup block, a clock generator, an AND element, an RS flip-flop, an OR element, a group of counters, a group of receiving blocks, the group of information inputs and the address the input of the first switch is, respectively, a group of information inputs and the first address input of the device, the second address input and a group of information outputs of which are respectively the address input of the second com the output and information outputs of the receiving units of the group, and the start input is the S input of the RS trigger, the first input of the OR element is connected to the overflow output of the reversible counter, the second input to the output of the initial setup unit, and the output to the R input RS a trigger whose output is connected to the enable input of the prerecord reversing counter and the first input of the element I, the second input of which is connected to the output of the clock generator, and the output connected to the counting input of the reversing counter and the first information input w The first switch, the first group of outputs of which is connected to the counting inputs of the corresponding group counters and clock inputs of the corresponding receiving blocks of the group, the information inputs and reset outputs of which are connected respectively to the outputs and the reset inputs of the corresponding group counters, each receiving block of the group containing a clock pulse generator and elements OR NOT, the pulse shaper of the initial setup and the register, the output of the pulse shaper of the initial setup is connected to the corresponding The first input of the OR-NOT element and the register zero reset input, the inputs of the clock drivers and the outputs of the OR-NOT elements, respectively, are the clock inputs and reset outputs of the corresponding receiving blocks of the group whose information outputs are connected to the outputs of the registers; the first algebraic adder and a nominal value memory block whose address input is connected to the first address input of the device 10

15

20

25

360016

the output is connected to the input of the first algebraic adder to be subtracted, the input of which is decremented is connected to the output of the first switch, and the information output and transfer output are connected to the set input of the reversible counter and the second information input of the second switch the delay element, the second algebraic adder and nominal value adjuster, the output of the clock generator is associated with the clock input of the second algebraic adder and with the input of the element back The terminal, whose output is connected to the input of the OR-NOT element and the register recording resolution input, whose information input is connected to the output of the second algebraic adder, the zero input of which is connected to the output of the initial setting pulse generator, is decremented and is connected to the output of the nominal value setter, and the input deductible is one of the information inputs of the receiving unit of the group, the control outputs Addition-subtraction of which are connected to the control inputs Addition-subtraction of the second al. hebraic adder and connected to the second group of outputs of the second switch.

Each process parameter has a nominal value, and the task of automated monitoring and control is to control the deviation of the parameter from the nominal value and to control the technological process in order to reduce this deviation to the minimum value, i.e. ensuring the nominal value of the monitored parameter in the process. Therefore, informative is not the absolute value of the controlled parameter, but the deviation of its value from the nominal value, which is usually (in normal technological processes)

50 is much less than the nominal and absolute (current) value. Based on this task of monitoring and controlling technological processes, it is possible to solve on the basis of monitoring the deviation of the technological parameter from the nominal value of this parameter. The latter allows to reduce the processing time of the control result,

thirty

35

40

55

since, in this case, the width of the input codes is much smaller. This is the essence of the proposed device, i.e. the reversible counter records codes corresponding to the deviations of the monitored parameters from their nominal values, obtained by subtracting the corresponding codes on the first algebraic adder of digital codes. Further, the information recorded in the reversible counter is transferred to the receiving units. In the receiving blocks, codes corresponding to deviations and nominal values are summed with the help of the second algebraic adder, and the code corresponding to the value of the parameter being monitored is written to the register.

Based on the above, the polling time of one sensor in the proposed device can be determined as follows:

Top T, LK + ЈB + ЈC + C,

where & K is the decimal value of the maximum permissible deviation of a code from the nominal one; t-b - code subtraction time; Ј0 is the time to add codes. Taking into account the fact that Јv Јc 25 is not and T, b20 is not, we can accept Qu tJc T,. Then

Top T1 L K + 2T + Ј

Since T, and & K K -, we get

 t, (k - k „) + 32,

expressions (1) and (3) it can be seen that

 i

on

 t

on

Thus, a comparative analysis with a known device allows us to conclude that the proposed device provides an increase in speed with an increase in the number of sensors and receivers serviced by this device.

Figure 1 shows the block diagram of the device; figure 2 is a functional block diagram of the receiving registers; on fig.Z time diagrams

signals in the device; in fig. - scheme of the first algebraic adder; on fig.Z - the scheme of the second algebraic adder.

The device contains sensors 1 of monitored parameters, the first switch 2, whose information inputs are connected to the outputs of sensors of monitored parameters, the first algebraic adder 3, the input of which is decremented is connected to the output of the first switch 2, block 4 of the memory of nominal values of monitored parameters, the output of which is connected with the input of the readable first algebraic adder 3, the first address input 5, the reversible counter 6, the setup input of which is connected to the output of the first algebraic sum Ator 3, block 7 of the initial installation, the element OR 8, the first input of which is connected to the overflow output of the reversible counter 6, and the second 25 ROY input - to the output of the initial installation block 7, RS flip-flop 9, the input of which is connected to the output of the element OR 8, and the input is connected to the device start input, element 10, the first

The Q input of which is connected to the output of the RS flip-flop 9 and to the resolution enable input of the reversing counter 6, a clock generator 11 whose output is connected to the second output of the AND 10 element, the second switch 12 whose second information input is connected to the transfer output of the first algebraic adder 3, and the first information input with the output element And 10, the second address input 13, a group of counters 1, the counting inputs of which are connected to the first outputs of the second switch 12, a group of receiving units 15, information and clock inputs

5 and the reset outputs of which are connected respectively to the outputs, the counting input and the reset input of one of the counters of the group. At the same time i address input of the first switch 2

50 and the memory module of nominal values are connected to the first address input 5, the address input of the switch 12 is connected to the second address input of the remote control 13 and the second outputs of the switch

55 12 are connected to the control inputs. Addition-subtraction of the receiving units 15.

Each receiving unit 15 contains serially connected shaper 16 clock pulses, delay element 17, as well as an OR element 18, the output of which is the reset output of the block 15, shaper 19 of the initial installation pulse, the output of which is connected to the first input of the element OR NOT 18, the second algebraic adder 20, the input of which is subtracted is one of the information inputs of block 15, and the control input Addition-subtraction is connected to the control input Addition-subtraction of block 15. nominal value adjuster 21 controlled parameter whose output is connected to the input of the decreasing second algebraic adder 20, the clock input of which is connected to the output of the clock 16 clock pulses, register 22, the information input of which is connected to the output of the second algebraic adder 20, and the zeroing input is connected to the zeroing input of the second algebraic adder 20 and connected to the output of the initialization pulse generator 19, the register write enable input 22 is connected to the output of the delay element 17.

The device works as follows.

When applied to the supply voltage device, the initial set-up unit 7 generates a pulse (Fig. 36), which through the element OR 8 (Fig. 3b) enters the R input of RS flip-flop 3 and fixes a logic zero level at its output (Fig. 13 ), which sets the preset mode of the reversible counter 6 and prohibits the passage of pulses produced by the generator 11 at the output of the And 10 element (FIG.). In the receiving units 15, at the same time, the initial pulse shaper 19 generates a pulse (FIG. 36), which zeroes the second algebraic adders 20 and registers 22 and pass through the OR-NOT 18 element (FIG. 3) to the reset inputs of counters 1 , sets them to zero.

After the time t (Fig. 36), after the moment when the supply voltage is applied to the device, the outputs of the block 7 and the drivers 19 are set to a logic zero level, after which the device receives control signals from the control system

yy (lsh

The control system, which can be used as a computer, or from the dispatch console, is first assigned at output 5 the address of the sensor 1 at which information is present, and at input 13 the output address at which this information is required to be transferred. In this case, information from the sensor 1 to be scanned through the first switch 2 is fed to the input of the decreasing first algebraic adder 3. To the input of the first algebraic adder 3 that is subtracted from the block

.g memory of the nominal values of the monitored parameters receives the code corresponding to the nominal value of the monitored parameter. The code corresponding to the deviation of the value of the parameter being monitored from its nominal value, which is fed to the installation input of the reversible counter 6, is generated on the curve of the algebraic adder 3. Since 25 the reversing counter 6 is in the preset mode, a binary code corresponding to the deviation is written to it. monitored parameter from nominal value.

In addition, the second switch 12 connects the output of AND 10 to the input of that of blocks 15 and AND counters, which are assigned the address present at address input 13, as well as the transfer output of the first algebraic adder with the Addition – subtraction control input of the receiving unit 15.

After that, the control system outputs a trigger to the input (Fig. 3c), which fixes the logic level (Fig. 3g) at the output of the RS flip-flop 9, which determines the mode of the reversible counter 6 and permits the passage of pulses

5 from the generator 11 through the element And 10 (Fig.).

The pulses from the output of the element And 10 are fed to the counting input of the reversible - “j th counter 6 and through the second switch 12 to the input of that of the counters 11 and blocks 15, whose addresses are present at the input 13.

With each pulse arriving 55 at the counting input, the reversible counter 6 decreases its content by one until all its bits become zero and its

thirty

40

I173600

an overflow pulse will not form.

The overflow impulse of the reversible counter 6 (FIG. 3), when counting from the overflow output, arrives at the K-input of the RS flip-flop 9 and fixes a logic zero level at its output (FIG. ZJ). which again prohibits the passage of an impulse from a gene

rator 11 through the element And 10 (Fig.Zd h) and determines the preset mode of the reversible counter 6.

By pulses passed to the counting input of the counter I and to the input of block 15, whose addresses are present at input 13, block 15 forms at its outputs to the actuating element a code corresponding to the value of the monitored parameter through T {+ Ј + Dp from the moment the front enters the front of the last pulse arriving at this block is 15.

Thus, at the output with a given address control system, there is the information that was present at the device input specified by the control system, i.e. at the output of the sensor whose address is present at the input 5 by the time of the appearance of the pulse at the Start input. The code generated at any output is saved until the next control system reduction to this output.

After the time Tc T op from the moment of the start pulse arrival, the control system removes the address codes at inputs 5 and 13.

In block 15 of the reception register, a code corresponding to the value of the parameter being monitored is generated as follows.

When pulses are received from the corresponding output of the switch 12 (Fig. 3), the logic zero level is set at the leading edge of the first pulse at the output of the former 16 (Fig. 3k). Through time T + C after the moment when the leading edge of the last pulse arrives, the shaper 16 sets the level of the logical unit at its output (FIG. 3d, k). At the same time, at the outputs of the reduced and calculated algebraic adder there are codes corresponding to the deviation and the nominal value of the controlled parameter, which are received respectively from the output

0

, 0

five

five

0

5 0 5

112

counter 1 setpoint 21 of the nominal value of the parameter. In addition, the signal from the transfer output of the first algebraic adder 3 also goes to block 20 via switch 12. This signal sets the mode of block 15 to correspond with the sign of the subtraction result.

When a logic zero level is established at the output of the shaper 16 (Fig. 3k), the indicated codes are summed up in the adder of block 20 and a code corresponding to the value of the monitored parameter is generated at its output. The output signal of the imaging unit 16 after a delay in the element 17 (FIG. 3) after time поступc goes to the register 22 and provides for rewriting the code from the output of the adder 20 to the output of the register 22.

The impulse from the output of the delay element 1 through the element OR NOT 18 (Fig. 3g) is fed to the reset input of the counter I, and has wrapped it. Therefore, at the outputs of register 22 there is a binary code corresponding to the value of the parameter being monitored.

Algebraic adders are built on the basis of the K1802 IM1 integral dischargers (Fig. 1). The adder provides the subtraction of gig 8-bit codes. The input I of the adder 3 (DAO-DA7) receives the code corresponding to the output code of the switch 2. The input corresponding to the output code of the block k is fed to the input II of the adder 3 (DSO-DS7). In this case, adder 3 subtracts the input codes. The result of the subtraction is fed to the output I (DSO-DS7) of the adder 3 and is fed to the installation input of the reversible counter 6 of the device. And at the output II of the adder 3, a signal is formed that corresponds to the sign of the result of the subtraction, codes, which is fed to the input II of the second switch 12. Moreover, if the result is positive, the signal is high, and if negative, a low level.

The adder 20 (figure 5) is implemented on integrated circuits K1802 IM1. The input I of the adder 20 is supplied with a code from the output of the counter I, and the input II - the output code of the block 21. The output V of the adder 20 is connected

131

with the output of the former 16. When a high level signal arrives from the output of the former 16, which is fed to the control inputs STB of the integral adders, the input registers of the adders become transparent and the codes available at the inputs I (DAO - DA7) and II (DBO - DB7) , arrive at the summation matrix of integral adders. At the same time, the input IV of the adder 20, which is connected to the output I of the switch 12, receives a sign signal of the result of the subtraction of the codes in the adder 3. If the result is i. subtracting a negative (positive) one, a low (high) level signal is fed to the input IV of the adder 20, which is fed to the control inputs of the OPA of the integral adders. Since the inputs of the OPA adders received a low (high) level signal, they operate in addition (subtraction) mode. Thus, depending on the level of the signal coming from the output I of the switch 12, the addition or subtraction mode is set in the adder 20.

Resetting the adder 20 is performed when a high level signal is received from the former 19. Since the input III of the adder 20 is connected to the output of the former 19, this signal is fed to the control inputs of the EDB integral adders, and therefore zeros are written to all bits of the second registers of the adders. In addition, the output signal of the driver 19 through the element OR - NOT 18 enters the counter k and resets it. Therefore, at the input I (DAO-DA7) of the adder 20 there is a zero code. Accordingly, zeros are also written to all bits of the first registers of the adders. Thus, the reset of the adder 20 is ensured.

You can use programmable logic arrays or well-known integrated ROM and PROM as a memory block of nominal values of monitored parameters. The second switch 12 of the proposed device can be constructed on the basis of two switches connected in parallel, identical to the second switch of the known device. Nadl controllers min. Values controlled by na

0

01

14

The parameters can be program switches type PP10-HV.

As the remaining nodes of the proposed device, you can use 1

call nodes identical to those used in the known device.

Thus, the proposed device reduces the transfer time of discrete parameter values from the preselected sensor to the preselected receiver, which allows increasing the number of sensors and receivers serviced by this device or increasing the frequency of calls to each sensor, which in turn allows you to get closer to registering instantaneous values of parameters

0

five

0

five

0

five

O

five

Claims (1)

Invention Formula A device for transmitting information containing two switches, a reversible counter, an initial setup block, a clock generator, an AND element, an RS flip-flop, an OR element, a counter group, a group of receiving blocks, the group of information inputs and the address input of the first switch are respectively the group of information inputs and the first address input of the device, the second address input and the group of information outputs of which serve respectively the address input of the second switch and information outputs of the The first blocks of the OR element are connected to the overflow output of the reversible counter, the second input is connected to the output of the initial setting block, and the output is connected to the K input of the RS flip-flop, the output of which is connected to the enable input of the prerecording of the reversible counter and the first input of the element I, the second input of which is connected to the output of the clock pulse generator, and the output is connected to the counting input of the reversing counter and the first information input of the second switch, the first group of output which is connected to the counting inputs of the corresponding group counters and clock inputs of the corresponding receiving units of the group, the information inputs and reset outputs of which are connected respectively to the outputs and the reset inputs of the corresponding group counters, each receiving unit of the group containing a clock driver, OR the pulse shaper of the initial setup and the register of the pulse shaper of the initial setup are connected to the corresponding first input of the element OR NOT and the input do zero reset of the register, and the input of the clock drivers, and the outputs of the OR-NOT elements are respectively the clock inputs and the reset outputs of the corresponding receiving blocks of the group, whose information outputs are connected to the outputs of the registers, characterized in that, in order to improve speed, the first algebraic adder and nominal value memory block, the address input of which is connected to the first address input of the device, and the output is connected to the input of the calculated first algebraic adder , the input of which is decremented is connected to the output of the first switch, and the information output and output five five 0 the transfer is associated with the setup input of the reversible counter and the second information input of the second switch, with each element of the group receiving a delay element, the second algebraic adder and nominal value adjuster, the output of the clock pulse generator is connected with the clock input of the second algebraic adder and the input of the delay element The output of which is connected to the input of the element OR-NOT and the input of the resolution of the register entry, whose information input is connected to the output of the second algebraic sum Pa, the zeroing input of which is connected to the output of the initial setting pulse generator, the input of the reduced value is connected with the output of the nominal value setpoint generator, and the input of the deductible is one of the information inputs of the group receiving unit, the control inputs Addition – subtraction of which are connected to the control inputs Addition -the subtraction of the second algebraic adder and connected to the second group of outputs of the second switch. I I ,) Kl € . 2 I about 13 y; tuel I G L / 3 " I t RSG. / 07 / U )  4Z w i and in - .0-010 y / fc / 1009 I L 20 J (i & o + ogo) / 7 th ЈX & iSCj pats & .tsSxzx- XX / Oj / l tw / tn JcfO (fcfO OQS J03 $ 03 1/03 too 00.4 ЈЈОО fg / i // 6W 0EO  | ffa WC J. tsa-t g and / o and (tt / ff- & t / O) l Q9i Y u we w5 sxi $ n & Ja.- Jos- J & J # J Ocfo J & O 900 003 EOE 003 UOE Ј00 HO OOQ Oee VH f & Q OQQ #a 9bz.S