SU1721609A1 - Data exchange controller - Google Patents

Description

the first and second element IS-NOT, the sync input of the first trigger is the device start input, the information input of the first trigger is connected to the bus of the logical unit, the output of the second trigger is connected to the information input of the third trigger and the first input of the first element IS-NOT whose output is connected to the input reset the first trigger, the direct output of the third trigger is connected to the first input of the element AND whose output is the output of the device, the inverse output of the third trigger connected to the first input of the element OR, the second inputs of the el The element AND of the element OR is the input of the reading device, the output of the element OR is connected to the first input of the second element AND –NE, the output of which is connected to the synchronous input of the third trigger, and the second input is the first synchronization input of the device, the output of the first trigger a trigger whose sync input is the second synchronization input of the device, the output of the OR element is connected to the second input of the first NAND element, the third input of which is combined with the second input of the second AND NAND element.

Improving the speed of the proposed device allows to expand the class of subscribers served by the device, due to the possibility of connecting more high-speed subscribers.

Increased speed is achieved in the absence of signals at the input of reading. The next external signal cannot be received at the first trigger of the device before the moment at which the second trigger is released (zeroed) from the storage of the previous external signal. Otherwise, it may be lost. The period of the external signals for the proposed device can be determined by the expression

TVS tl + tcHX + Atcn + te,

where ti is the switching time of the first trigger;

1снх - synchronization time;

A ten is the time from the sync pulses from the second synchronization input to the sync pulses from the first sync input of the device;

te is the delay time of the signal on the NAND element.

For the proposed device, the TVS value is greater than at least for the time: the signal delay on the NAND element excluded from the known device, is located between the first and second triggers, i.e. on ts. The analysis shows that the gain

is the value of 2te + t2, where t2 is the switching time of the second trigger.

Figure 1 shows the functional diagram of the device; 2 and 3 are temporary

diagrams of his work.

The device contains the first 1 and second 2 registers, the first 3, the second 4 and the third 5 triggers, the first element AND-NOT 6, the elements AND 7 and OR 8 and the second elements AND-NOT 9.

0 The information inputs 10 of the device are connected to the information inputs of the register 1, the outputs of which are connected to the information inputs of the register 2, the outputs of which are connected to the information outputs 11 of the device. The trigger of trigger 3 is the trigger input 12 of the device and is connected to the synchronization of register 1. The information input of trigger 3 is connected to bus 1. The output of trigger 3

0 is connected to the information input of the trigger 4, the sikhrovkhod of which is the second synchronization input 13 of the device. The output of the trigger 4 is connected to the information input of the trigger 5 and the first input

5 of the NAND element 9. The forward output of the trigger 5 is connected to the first input of the element AND 7, the output of which is the output 14 of the device. The second inputs of the element And 7 and the element OR 8 are the input 15 of the reading

0 devices. The first input of the element OR 8 is connected to the inverse output of the trigger 5, and the output to the first input of the element AND-NOT 9 and the second input of the element AND-NOT 6. The output of the latter is connected to the synchronous inputs of the registry of the 2nd and trigger 5. The second input of the element AND-NO 9 is the first synchronization input 16 of the device and is connected to the third input of the NAND element b, the output of which is connected to the reset input of the trigger 3.

0 The device operates as follows.

In the initial state, all the triggers are set to zero. On the positive edge of the external signal (BC) received at the device start input 12, the input information register (CI) received at the device inputs 10 is received, and, thanks to the level logical 1 on the information input of trigger 1,

0 setting this trigger to 1. On the front of the nearest sync pulse SIS, arriving at the second input 13 of the device sync, trigger 4 is set to 1. On the front of the nearest sync pulse SI,

5 arriving at the first synchronization input 16 of the device and then to the third input of the element AND-NOT 9 and the second input of the element AND-NOT b due to the permission levels at the remaining inputs of these information elements from register 1 is transmitted to register 2,

trigger 5 is set to 1, and trigger

3- in O.

If the synchronous request (THU) in the inverse phase at the input 15 of the device and further to the second inputs of the AND 7, OR 8 elements and having a higher priority is absent in the next clock cycle of the synchro-frequency, then the output of the And 7 element and further to the output 14, the device generates a write request signal (3D). Following the clock pulses of the SIS and SI, triggers 4 and 5 are zeroed (if by this time the next C is not received). If after setting in 1 flip-flop 5 it turns out that a THU request has been received, then the transfer of the output signal of flip-flop 5 to the output 14 of the device is blocked by the second input of the element 7. And in addition, the signal O from the output of the element OR 8 will not block register 2 and flip-flop 5 and resetting flip-flop 3. As a result, flip-flop 5 and flip-flops of register 2 retain their state, and flip-flop 3 saves the next aircraft if it arrives at the considered time interval. After the signal is removed, the device is unlocked and the SI clock pulses are resumed. HTTP requests are generated, for example, by the control device during the execution of a program that reads and processes the received information; they can also be requests from the same kind as described by another information exchange control device.

When the device is in the presence of requests THAT (figure 2). The BC signals are received with a period of 2Tsi in the immediate vicinity of the clock of the SIS, i.e. at a time when the trigger 2 can be triggered by both the sync pulse SIS (1st, 3rd, 5th VS Signals) coinciding with the sun, and from the next (2nd, 4th VS signal). In particular, the situation is considered when B (C) (second) in trigger 4 is received with a maximum delay, and the following (BC) aircraft is received with a minimum delay. In this case, the transfer of the third aircraft from the trigger

4, trigger 5 is blocked by a THI signal. However, by blocking the nullity

trigger 3, the second B C is stored in it. In the next cycle, the PN request is cleared and the signal flow is unblocked. When operating the device in the absence of

requests THAT (FIG. 3) the period of the BC signals in this case may be less than the value 2TCi. Signals of aircraft with odd numbers are received in the immediate vicinity of the clock of the SIS. Some of them (1st, 2nd

BC signals are received in trigger 4 with a maximum delay, the other part (3rd, 5th BC signals) with a minimum. However, this does not interfere with the formation of RFP signals for each aircraft and the issuance of relevant information on the output buses with a register 2 output.

Claims (1)

Claims An apparatus for controlling the exchange of information, comprising the first, second and the third flip-flops, the AND element, the OR element, the first and second NAND elements, the sync-stroke of the first flip-flop is the device start input, the information input of the first one is connected to the bus of the logical unit, the output of the second flip-flop is connected to the information input of the third trigger and the first input of NAND element whose output is connected to the reset input of the first trigger, direct output of the third the trigger is connected to the first input of the element AND whose output is the output of the device, the inverse output of the third trigger is connected to the first input of the element OR, the second inputs of the AND element and the element OR is the read input of the device, the output of the OR element is connected to the first input of the second NAND element, the output of which is connected to the synchronous input of the third trigger, and the second input is the first a device sync input, characterized in that, in order to simplify and increase the speed of the device, the output of the first trigger is connected to the information input of the second trigger, the sync input of which is the second synchronization input of the device, the output of the OR element is connected to the second input of the first AND-NAND element, the input of which is combined with the second input of the second element AND-NO. ten BU Jj s I eleven V sixteen 15CU i I I I I-I I I CMC I I I I I I I I I I FIG. I D Uz.