SU1714784A1 - Digital frequency synthesizer - Google Patents

Description

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The invention relates to radio engineering and can be used in radio transmitting devices and in the construction of measurement generators.

The aim of the invention is to increase the spectral purity of the output oscillations.

In the drawing, a block diagram of a digital frequency synthesizer is shown,

The digital frequency synthesizer contains a reference frequency generator 1, a frequency code setting block 2, an accumulator (NS) 3, a memory register 4, a first digital-to-analog converter (D / A converter) 5. second. DAC 6, D-flip-flop 7, generator 8 linearly varying voltage (CLAY), the first comparator 9, trigger 10, the first low-pass filter 11, the second comparator, the frequency-phase detector (H PD) 13, the second low-pass filter 14.

Digital frequency synthesizer works as follows.

The required output code from the outputs of unit 2 of the installation goes to the HC 3 and to the outputs of the second DAC 6.

With CLEANING the following pulses from the output of gzibrator 1 in HC 3, the accumulated number is added with the number M corresponding to the code at the output of unit 2 of the installation.

Through To the periods of the pulses of the generator 1, an overflow of HC 3 occurs, at its output of the overflow a pulse appears, which is fed to the control input of register 4 and to the p input of the D-trigger 7. Register 4 fixes the code of the number P, remaining in HC 3 after it is overflowed. The first DAC 5 converts the code of this number to the voltage supplied to the first input of the first comparator 9. The second input of the first comparator 9 receives impulses of a saw-shaped form from the output of GLINE 8 whose duration is exactly equal to the follow-up period of the reference frequency pulses, and the position is determined by the pulses from the Q-output of the B flip-flop 7 delayed by relative to the overflow pulses by one period of the reference frequency. When the voltage levels coincide at both inputs of the first comparator 9, it produces pulses, the duration of which varies during the operation of the synthesizer. The trigger 10 operates in the counting mode necessary to obtain 11 symmetric pulses at the input of the first filter. From the output of the second D / A converter 6, the voltage determined by the code arriving not its inputs from the corresponding bitwise outputs of the installation unit 2 is fed to the input of the second comparator 12. The other input receives pulses from GLINE 8. When the voltage levels at both inputs of the second match comparator

12on produces a short pulse. FFD

13 compares the moments of arrival of pulses from the second comparator 12 with the moments of arrival of pulses from the inverse b-output of D-flip-flop 7. The voltage from the output of the FFD 13 is fed to the input of the second filter 14, and its output goes to the control input of the steep line part of the GLIN 8.

Since the time interval between the pulses from the Q-output of the D-flip-flop 7, which triggers GLINE 8, and the pulses from the inverse Q-output of the D-flip-flop 7, which are fed to another input of the FPD 13, is equal to one period of the pulses of the reference frequency generator 1, the steady state, the value of the steepness of the linear section of the output CLIN 8 voltage will be such that over a time interval equal to the period of the generator 1 pulses, the HLID 8 pulses will accurately reach the value of the voltage at the output of the second DAC 6.

With this, changing the parameters of CLAY 8 under the influence of various destabilizing factors will not affect the operation of the digital frequency synthesizer, since the FFD 13 constantly analyzes and, if necessary, adjusts the slope of the LN, iris sections of the output pulses of GLIN 8.

When changing the code of the synthesized frequency of the unit 2, the PFD 13 unit will change its output voltage so that the steepness of the linear sections of the output impulses GLINE 8 corresponds to the new value of the output voltage of the second DAC 6.

As a CPS 13, it is most advisable to use a frequency-phase detector with three stable states.

If one chooses the parameters of the second filter 14 so that the transient process at cm, the code of the synthesized frequency in the automatic control ring, which includes GLINE 8, the second comparator 12, the PDP 13 and the second filter 14, ends at several adjustment intervals, the automatic ring controlling the steepness of the GLINE 8 will almost not degrade the dynamic characteristics of the digital frequency synthesizer, but will significantly improve its spectral characteristics, in particular, the degree of suppression of the discrete mechs in the output spectrum.

Goiter formulas A digital frequency synthesizer containing serially connected reference frequency generator, D-flip-flop, linear voltage generator, first comparator, low-pass trigger m, series accumulating adder, memory register and first digital-to-analog converter , the OUT of which is connected to the BTOpoi y input of the first comparator, the installation unit of the frequency code, the code output of which is connected to the code input of the second digital-to-analog converter and to the code input on aplivayuschego adder, a signal input coupled to an output of the generator oporyS1y

frequency, the overflow output of the accumulating adder is connected to the r-input of the 0thrigger and to the control input of the memory register, which, in order to increase the spectral purity of the output oscillations, between the output of the second digital-to-analog converter and the second input of the ramp voltage generator are introduced a second comparator, a frequency-phase detector and a second low-pass filter, which are connected in sequence, while the second input of the frequency-phase detector is connected to the second output of the O-flip-flop, and

5, the second input of the second comparator is connected to the generator output of a linearly varying voltage.

Claims (1)

The formula is a Digital frequency synthesizer containing a series-connected reference frequency generator, a D-flip-flop, a ramp generator, 5 first comparator, a trigger and a first low-pass filter, serially connected accumulating adder, memory register and the first digital-to-analog converter, the output of which is connected - 10 chan to the second input of the first comparator, a frequency code setting unit, the code output of which is connected to the code input of the second digital-to-analog converter and to the code the accumulating adder 15, the signal input of which is connected to the output of the reference frequency generator, the overflow output of the accumulating adder is connected to the D-input D of the trigger and to the control input of the memory register, which differs in that, in order to increase the spectral purity of the output oscillations, between the output of the second digital-to-analog converter and the second input of the ramp generator are connected in series with a second comparator, a frequency-phase detector and a second low-pass filter, at m second input of the phase-frequency detector connected to the second output of the D-flip-flop and the second input of the second comparator connected to the output of the generator linearly varying voltage. ♦ '. · - ·.