SU1695307A2 - Device for multiplication in additional codes - Google Patents

Abstract

The invention relates to computing and can be used in digital computers in the construction of automatic monitoring and diagnostics systems. The purpose of the invention is to increase the reliability of the calculation result. The device contains registers 1.4 inversion circuit 2, adders 3,32,41, elements AND 5,6,8.36,40, half-adder, element IL AND 9, delay element 10, converter 16 direct code to additional, nodes 17,24 parallel convolution modulo, multipliers 18,31,35, shaper 19 multiplication factors, registers 21,34 check bits, comparison nodes 22, 42, nodes 27,30 sequential convolution modulo checker deductor 33, trigger 38, shaper 39 additional control deduction. Nodes 1-10 multiply in additional codes. 8 il. with “in YOUR SCH) ate 00 oh KD Vut.l

Description

The invention relates to computing and can be used in digital computers in the construction of automatic monitoring and diagnostics systems.

The purpose of the invention is to increase the reliability of the resultant of the device.

Figure 1 shows the functional diagram of the device; figure 2 is a diagram of the node parallel convolution modulo three; FIG. 3 is a diagram of a sequential convolution node modulo three; Figs. 4 and 5 show the execution schemes of the third adder and the third multiplier; figure 6 - schemes of the first and second multipliers; figure 7 - diagram of the driver control deduction; FIG. 8 is a diagram of a multiplication factor generator for modulo three control.

The device contains the first register 1, the inversion circuit 2, the first adder 3, the second register 4, the second 5 and the first 6 elements AND, the half adder 7, the third element AND 8, the element OR 9, the delay element 10, the control input 11 of the device, the information input 12 devices, inputs 13 and 14 of the multiplier and device multiplier records, device clock input 15, direct code to additional converter 16, first modulus parallel modulus 17, first multiplier 18, shaper 19 multiplication factors, device 20 check bits, first register p 21 check bits, first comparison node 22, first failure output of device 23, second parallel convolution node 24 modulo, parallel information output 25 of device I, first output 26 check bits of the device, first serial modulation node 27, sequential information output 28 of the device, second output 29 of control bits of the device, second node 30 of sequential convolution modulo, second multiplier 31, second adder 32, driver 33 of control deduction, second register 34 control bits, the third multiplier 35, the fourth element And 36, the input 37 records the control bits of the device, the trigger 38, the shaper 39 additional control deduction, a group of 40 elements And, the third adder 41, the second node 42 comparison, the second output 43 of the device fault signal .

Node 17 is made on the elements AND-OR 44 and 45 and has inputs 46-49 and outputs 50 and

51.

Node 27 contains elements AND-OR 52, 53, triggers 54 and 55, inputs 56-58 and outputs 59 and 60.

Node 41 is made on the elements AND-OR 61 and 62 and has inputs 63 and 64, outputs 65 and 66 and inputs 67 and 68.

Node 35 contains AND-OR elements 69 and 70, outputs 71 and 72, and inputs 73-76.

The node 18 is formed by the inputs 77 and 78, the elements AND-OR 79 and 80 and the outputs 81 and 82.

Node 33 contains the element AND-OR 83, input 84 and outputs 85 and 86. 0 Node 19 is made on trigger 87 and has an input 88, outputs 89, 90.

The device works as follows.

The multiplicand X is written to register 1 5 from the input 12 of the device. The multiplier V is recorded in register 4 from the input 12 of the device according to a signal from input 14 of the device.

The shift in the adder 3 and register 4 is carried out according to the clock signals from the input 15 0 of the device.

A collection of nodes 1-10 performs an X and Y multiplication operation in the usual order.

The control of register 4, half adder 7, 5 of the AND 8 element, the OR 9 element and the delay element 10 is carried out as follows.

The most significant sign bit of register 4 is not involved in the shift, it remains in place. The successive modulo multiplier code generated at the output of half-adder 7 by node 1B is again converted to additional and written into the most high offset register register 4. Thus, in 5 register 4 the cyclic shift of the multiplier is performed. The node 17 forms a subtraction of the current state of the multiplier modulo. In multiplier 18, this deduction is multiplied by the coefficient K1, so that at its output a deduction corresponding to the initial position of the multiplier is formed. At comparison node 22, this deduction is compared with the multiplier deduction recorded in register 21. If the deductions did not match, there was a failure. 5 The control of the remaining blocks of the multiplier is performed in accordance with the expression:

t (K2 Calc ZciOmR + Calc 3 (Calm I XI Calc I Yi l) mp + + Aux (Calc 1

Q (Bbi4 (Y |).

where Calc | A (is the modulo A deduction;

(operation) tv - some operation is performed modulo R;

Dop (Cal. A) - Supplement 5 is deducted from A to R;

ZcriiZfcuii is the current value of the major and minor work bits that are formed at the output of the adder 3;

Bbw (Yi) is the deduction of the multipliers that were worked out in the 1st step;

K2, KZ - coefficients;

S is the sign bit of the product from trigger 38.

In the convolution node 24, the calculus ZCTI is formed, in the multiplier 31 it is multiplied by the coefficient K2. At convolution node 27, the Calm ZMni and Adder 32 are formed — the left side of the expression

At convolution node 30, a calculus is formed (| |); in multiplier 35, it is multiplied by calculus (X). If the trigger 38 is in the O state, the product passes through the imaging unit 39 without change. If in flip-flop 38 is code 1, shaper 39 is searched for its addition. In the adder 41, the product of the deductions (or its addition) is added with zero (if in the flip-flop 38 code O) or with the short-circuit coefficient (if in the flip-flop 38 code 1). In the comparison node 42, the left and right parts of the expression are compared. If the device output 43 does not match, a malfunction signal is generated.

Claims (1)

Invention Formula A device for multiplying in additional codes according to ed. St. No. 1081640, which is based on the fact that, in order to increase the reliability of the result of the device, the second and third adders, the fourth And element, three multipliers, two comparison nodes, And group of elements, trigger, two parallel convolution nodes are entered into it module, two nodes of sequential convolution modulo, two registers of control bits, a direct code to additional converter, a multiplication factor generator, a control residue generator, and an additional control residue generator, and the output of the second register a is connected to the information input of the first parallel convolution node modulo, the output of which is connected to the first information input of the first multiplier, the output of which is connected to the first information input of the first comparison node whose output is the first output of the device fault signal, the output of the first bits of the first the adder is a parallel information output of the device and is connected to the information input of the second parallel convolution node modulo, the output of which is the output of the control bits of the device and connected to the first information input of the second multiplier, the output of which is connected to the first information input of the reference node, whose output is the second output of the device fault signal, the output of the lower digit of the result of the first adder is a sequential information output of the device and is connected to the corresponding bit of the information input of the first sequential convolution node modulo, the output of which is the second output of the control bits of the device and connected to the second information input of the second adder, the output of the sum of the half adder and the inverse output of the sign bit of the second the register are connected respectively to the first and second information inputs of the direct code to additional converter, the output of which is connected to the information the input of the sign bit of the second register, the output of the sum of the half-adder is connected to the corresponding bit of the information input of the second sequential convolution node modulo, the output of which is connected to the first information input of the third multiplier, the information and clock inputs of the first register of control bits are connected respectively to the inputs of the control bits and multipliers of the device, the output of the first register of control bits is connected to the second information input of the first comparison node, the signs the bit of the information input of the device and the input of the control bits of the device are connected to the corresponding bits of the information input of the pilot deduction generator, the output of which is connected to the information input of the second register of control bits, the clock input of which is connected to the input of the multiplicable device, the output of the second register of control bits connected to the second information input of the third multiplier, the input of the multiplication factor generator is connected to the clock input of the device, the first and The information output of the multiplication factor generator is connected to the second information input of the first multiplier and the corresponding bits of the information inputs of the first and second polarization modules of the module, the second information output of the multiplication factor generator is connected to the second information input of the second multiplier, the digit information device information input and the recording input the control bits of the device are connected respectively to the first and second input of the fourth element And, the output which is connected to the counting input of the trigger, the output of which is connected to the first inputs of all elements AND of the group, the second inputs of which are connected to the corresponding bits of the third information output of the multiplication factor generator, the outputs of the trigger and the third multiplier are connected to the corresponding bits of the information input of the additional check deductor, the output of which is connected to the first information input the third adder, the output of which is connected to the second information input of the second comparison node, the outputs of the elements AND groups are connected to the corresponding bits of the second information input of the third adder. FIG. 2 Fy fig.Z 5 6 Fig.8 7