SU1689990A1 - De-update dynamic memory - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices. The purpose of the invention is to increase reliability by controlling and updating stored information. The device contains multiplexers 1,3,4, 6, drives 2, 5, address counter 7, trigger 8, elements OR 9, 10, control unit 12 and control block 11. The goal is achieved by the fact that in the information recovery mode specified from the control input, the device successively checks the contents of the cells of the first and second drives 2 and 5 that store the same information, and if an error is detected in one of the drives, the error is corrected by overwriting information through the output and input multiplexers 4 and 3 from another drive. 2 Il.

Description

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The invention relates to computer technology, in particular, to storage devices (RAM) made on dynamic memory elements.

The purpose of the invention is to increase the reliability of the device by monitoring and recovering the stored information.

Figure 1 shows a flow chart of a dynamic storage device with information recovery; Fig. 2 illustrates the structure of the control unit.

The device contains multiplexer 1, accumulator 2, multiplexers 3 and 4, accumulator 5, multiplexer 6, address counter 7, trigger 8, elements OR 9 and 10, control block 11, control block 12. The device has an address input 13, information input 14, information output 15, write input 16, read input 17, information recovery input 18, error sign 19 output during information recovery.

Control unit 12 is a modulo two convolution scheme (for example, 533IP5), Control unit 11 contains a master oscillator 20, trigger 21, the output of which is connected to one of the inputs of element U 22, trigger 23, delay element 24, the element NOT 25, the element AND-NOT 28, the element 27 delay, the element And 28 and 29, the element AND-OR-NOT 30, the element 31 delay, triggers 32-34, registers 35 and 36, ele-, -shit AND -I L1 / 137, elements AND 38 and 39, element AND-CHE 40, element AND-OR 41, trigger 42, elements AND-OR-HE 43 and 44, elements AND 45-47, elements 48 and 49 of the delay, element AND 50 delay element 51

The device works as follows.

The device has four modes of operation, the mode of absence of calls to the device, the recording mode, the read mode, the information recovery mode. In this case, appeals setting the device at the same time several modes than are allowed.

Consider the operation of the device in the absence of calls to it, which is determined by the presence of the level of the logical unit from the write inputs 16, read 17, information recovery 18. In this case, in control block 11, the direct outputs of the trigger 23 and 42, the outputs of the delay element 31 And 39 are in the state of logical zero, and the outputs of the elements AND 38, AND-NO 40, elements 48, 49, 51 of the delay, the elements AND-OR 37 and 41, the elements AND 46, 47, 50, the elements AND-OR-NOT 30, 43, 44, the inverse outputs of the register 36 direct output of the trigger 34 are in the state of logical units s. Moreover, the states of these elements are provided by mutual ties and no effects on their prior installation are required.

The master oscillator 20 generates a sequence of pulses, for each of which control unit 11 generates a row sampling signal of accumulator 2, which from output of element 46 enters storage 2, simultaneously with this, multiplexer 1 transmits to control address inputs of accumulator 35 2 the regeneration address with the output of the address counter 7. The line sampling signal is generated during regeneration in the control block 11 by applying pulses of the master oscillator 20 to the chain

elements consisting of flip-flop 21, element AND 22, register 35, delay elements 27 and 24, element NOT 25, element IS-NOT 26, and elements 27 and 24 of delay determine the duration of the regeneration cycle.

The drive in which the regeneration is to be carried out is determined by the state of the trigger 8, with a logical zero at its direct output allowing regeneration in the accumulator and prohibiting regeneration in

drive 5, and the logical unit enables regeneration in drive 5 and prohibits drive 2. At the end of each regeneration cycle, address counter 7, by the signal from the output of the item IS-NOT 26, adds one to the main content, and when the counter reaches the last regeneration line, it generates a transfer pulse, which is fed to the counting input of trigger 8 and by duration

it is at least twice the switching time of this trigger. In the appearance of the transfer pulse, the trigger 8 switches its state, and thus the control unit 11 proceeds to regenerate the accumulator 5,

the next overflow pulse is back to the regeneration of accumulator 2, and this process is repeated cyclically throughout the entire operation of the device.

When accessing the device in mode

recording the signal from input 16 is remembered by trigger 23, which by its inverse output temporarily prohibits the start of the next regeneration cycle, from the direct output of trigger 23 application for recording through the element

31 delays are fed to the input of element 38, which prohibits recording, if the previous regeneration cycle has not been completed in the accumulator, which is determined by the state of element 45 and AND-NOT 26, to which the corresponding inputs are connected

element 38. In case the regeneration has ended, then at the output of element 38 an signal appears that sets the trigger 42, which through the AND-OR-43 and 44 element outputs, respectively, the recording signals in the accumulator 2 and 5, establishes through the AND-OR-NOT 30 element the inverse outputs of register 36 to the state of logical zero, and the signal from the inverse output resets the trigger 23 and prohibits the regeneration to start during the write cycle time. With inverse outputs of the register 36 through the elements And 46 and

47, respectively, drives 2 and 5 receive signals to fetch rows, and from the elements

48 and 49 delay signals sampling columns. At the same time, the register 35 is in such a state that the signals from its outputs, which control, respectively, multiplexers 1 and b, set the latter to the transmission mode on the address inputs of the address memory accumulators from the address inputs 13 of the device. This set of signals causes simultaneously in accumulators

2 and 5, recording information received from the information inputs 14 of the device through the input multiplexer 3. In this case, the recording cycle is determined by the delay in the AND 50 element and the delay element 51, the last propagation number in it through the AND-OR 37 element is reset. em register 36 and trigger 42, which corresponds to the end of the recording cycle and the resolution of the regeneration and subsequent calls to the device.

When a read device is accessed, the access from the device input 17 goes to the gate input of register 36. in which a row sample signal is immediately generated, and in delay elements 48 and 49, the column sample signal, respectively, of drives 2 and 5, which is not the information is regenerated, this is determined by the state of the outputs of the elements 9 and 10, which are connected to the outputs of the trigger 8. In this case, the register 35 controls the outputs of the multiplexers 1 and 6 so that the corresponding drive where the regenerator is produced Enters regeneration address outputs from the address counter 7, and the drive free from regeneration, the read address is supplied to the address input 13 of the device. The duration of the read cycle is determined by the delay in the AND 50 element and in the delay element 51, the latter resetting the register 36 and the trigger 42 as the signal propagates through the AND-OR 37 element, which corresponds to the end of the read cycle. The output multiplexer 4 transmits the read information from the drive.

in which the readout occurred, - according to the state of the output of the element AND - OR 41, which is determined by the caution of the first output of the register 36

When accessing the device to restore information, which is determined by the fact that the input of the device 18 is set to the state of a logical zero for the time required to view the entire memory and error correction. In this case, from the input 18 of the device, the logical zero arrives at the control input of the multiplexer 3 and sets it to transmit information from the output of the multiplexer 4, and in the control unit 11 the logical zero arrives at the information input of the trigger 34 and is stored by it under the influence of a gating pulse arriving from the output of the element AND NOT 26, which is generated at the end of the regeneration cycle, as a result, the outputs of the elements 28 and 29 are set to a logical zero state, at the corresponding inputs of the element 39, the element -NOT 40, AND-OR elements 41 and 37 and the AND-OR-NO element 30 is set to a logic-one state, corresponding to the resolution of informa- tion reduction mode.

On the next clock pulse from the output of the master oscillator 20, the trigger 21 is set to the state of the logical unit, which through the element 22 sets the outputs of the register 35 to the state of logical zero, and through the AND-OR element 30 it sets the state of the logical zero to the outputs of the register 36, corresponding to the fact that multiplexers 1 and 6 are switched to the transfer mode to the address inputs of the accumulators 2 and 5 of the address of the memory cell being restored from the address counter 7, line sampling signals are generated at the outputs of the elements 46 and 47, and at the outputs of the delay elements 48 and 49, signals are sampled from the columns that are fed to the corresponding inputs of the accumulators 2 and 5, as a result of which the information is read out in accumulators 2 and 5, the output multiplexer 4, controlled by the output state of the AND-OR element 41, transmits the read information from accumulator 2 to the inputs of the control unit 12, in which the reliability control takes place, the result of which from the output of the control unit 12 goes to the information input of the trigger 33 and is stored therein in time and from the accumulator defined by the delay time in the delay element 27. Simultaneously with storing in the trigger 33 the result of monitoring information from accumulator 2, the state of the AND-OR element 41 changes, as a result of which the output multiplexer 4 switches and starts transmitting information from accumulator 5 to the input of control unit 12. 12, the control is fed to the input of the trigger 32, and is stored there by the gate input through the delay time determined by the delay element 24.

According to the results of the information control, four options are possible: no errors were found in both accumulators; detected errors in both drives; an error was detected only in the first drive; An error was detected only in the second drive. If no errors are detected in both accumulators, the recording resolution from the outputs of the HE elements 43 and 44 is not received in the accumulators, the triggers 21, 32, 33 are reset, the sampler 35 is set to a logical unit, and a signal arrives at the counting input of the address counter 7 , at which the address counter 7 increases its value by one. If an error is detected in both accumulators, similar operations take place, but the output signal of the IS-NOT 40 generates an error signal during the recovery of information, which will arrive at the output 19 of the device. If an error is detected only in the first accumulator, at the output of the AND-OR-NOT 44 element a recording signal is generated, which is fed to the accumulator 2, and at the output of the AND-OR 41 element a signal is generated that the multiplexer 4 transmits the read information to through multiplexer 3 to the information inputs of the accumulator 2, as a result of which the contents of the memory cell of the accumulator 5 are recorded in the cell with the same address of the accumulator 2, due to which the error detected in the first accumulator will be corrected. If an error is detected only in accumulator 5, then a similar procedure occurs, only information read from accumulator 2 through multiplexer 4, controlled by the state of the AND-OR element 41, will go through multiplexer 3 to information input drives 5 and will be overwritten under the signal records from the output of the element AND-OR-NOT 43.

The duration of the rewriting operation is determined by the delay in delay element 27. At the end of the recovery cycle, the address counter is incremented by one. For each subsequent pulse c. the master oscillator 20 similarly, the rest of the cells are restored

memory until it is removed from the input 18 of the device, accessing the device to restore information. The duration of this treatment should be

such that the device has time to recover all the information stored in it.

Thus, in case of distortions of information stored in the device, the device allows you to independently restore

0 her. Recovery of information is performed by searching for errors in each drive and, if it is found, correcting it by rewriting from another drive.

five

Claims (1)

DETAILED DESCRIPTION A dynamic storage device with information recovery comprising first and second drives, 0 first, second and third multiplexers, address counter, trigger, control unit, first and second elements OR, and the information outputs of the address counter are connected to information 5 inputs of the first groups of the first and second multiplexers, the outputs of which are connected to the address inputs of the first and second drives, respectively, the outputs of which are connected to the information inputs of the first and second groups of the third multiplexer, respectively, the outputs of which are information outputs of the device, information inputs of the second groups of the first and second multiplexers 5 are combined and are address inputs of the device, the transfer output of the address counter is connected to the first inputs of the first and second OR elements and to the counting input of the trigger, the forward and inverse outputs of which are connected to the second inputs of the first and second OR elements respectively, first, second and the third outputs of the control unit are connected to the control inputs of the first, second and 5 of the third multiplexers, the fourth, fifth and sixth outputs of the control unit are connected respectively to the write input, to the row sample input and to the sample input of the first drive column, the seventh, eighth and ninth outputs of the control unit are connected respectively to the write input, to the sample input rows and to the sample input column of the second storage device, the first and second inputs of the control unit are respectively a write input and a read input of the device, which is so as to increase the reliability of the device due to ol and reduction of stored information, it comprises a fourth multiplexer, and a control unit, the inputs of which are connected to the outputs of the third multiplexer and to the information inputs of the first group of the fourth multiplexer, the information inputs of the second group of which are information inputs of the device, the third input of the control unit is the input of information recovery of the device and connected to the control input of the fourth multiplexer whose outputs are connected to the information inputs of the first accumulator, the input of the sign of the error of the control unit is connected to the input of the control unit, the first and second inputs of the task of setting the mode of the block the control is connected to the outputs of the first and second elements OR, respectively, the ninth output of the control unit is connected to the counting input of the address counter, the eleventh output of the control unit is the output error of the device.