SU1651280A1 - Device for calculating arcsine function - Google Patents

Abstract

The invention relates to computing and can be used in computers and systems. The aim of the invention is to simplify the device. The device contains the first, second, third and fourth registers, a multi-digit adder, an inversion unit, a single-digit adder, a delay line, the first and second elements 2I-Ilffllj and the second and second triggers. 3 il.

Description

I.

The invention relates to computing and can be used in computers and systems.

The aim of the invention is to simplify the device.

On league. 1 shows a block diagram of the device; in fig. 2 is a diagram of the generation of control signals and sequences applied to the input of the device; in fig. 3 - timing diagrams of the sequences fed to the input devices.

The device contains a register 1, a multi-digit adder 2, a register 3, an inverting unit 4, a register 5. a single-digit adder 6, a delay element 7, elements 2N-SHI 8. and 9, triggers 10 and 11, a register 12. The control unit contains a register 13, triggers 14-17. counter 18, elements And 19-21 and a pulse generator 22 "

The device works as follows.

The Start signal includes a control signal generation circuit, at the output of which potential P1 is formed, which is fed to the setup inputs of the trigger 10 and 11. Since the setup inputs are priority, the state of the triggers will not change until the end of the signal P1. By this, the required synchronization of the process is achieved; it cannot be started until signal C 'is received. On this pulse, the signal P1 disappears, and the triggers receive information on the inputs D. At the same time, on the pulse C y, the argument X is received and written to registers 1 and 5. The argument X varies from 0-1. The definition of the bits of the results is conducted in accordance with the algorithm

OS

or

tc

Ltd

 - a re in X

n

z

- Sc.

tfK 1 if Xk O (Yk Os if Xk 0 Xk-H 2X - 1 if

XK4, 1 - 2X. if a

4. 1 1 - 2X 2 O (P 0)

" ten. ..; four

4-2

In this case, it is necessary to shift the result, invert and add one to the low-order bit.

From where receive

It should be noted that 1, m., E. in fact, the result has a full part. To obtain the correct result, the register bit is made such that after n steps, W0 is lost. When issuing the result, zero is transmitted on this pin.

Every new value of x. may have a plus or a minus sign, since the square is always positive, then the construction operation can be performed on the modules. An inversion unit 4 is used to obtain the module.

Consider in what situations should the inverting occur, and in

which argument passes unchanged .5 lower bit (signal C (). There are four different cases. 2

 0; .2

2X

1.ts 0; 2X - 1

/ zxj- 1) --ml- o .. 1 The value of 1-2Xj, can be represented

as

0.111 ... 1 + 2X.

If 2X is written as 0.. ,,, where is O or 1, then

the square is barely done. blowing way. Register 1 contains the value of the current argument XK (X0 X). At adder 2, 30 addition occurs. Register 5 also contains the value of the current argument, which is a sequential code, starting from the lowest one, arrives at the input of register entry 3. If the current bit is one, then the falling edge of the C0 signal is entered into register 3. If the current bit is zero, This entry is missing. This multiplies the multiplicand by the current multiplier of the multiplier and adds it to the product being formed. The resulting product is then shifted one bit towards the lower bits and the circuit is ready for

0.111 0.

1 A

ABOUT,

Thus, 1 - 2X ,, 0 .. .. +

- MK

i.e. to obtain module X

to-and

g.

the square is barely done. blowing way. In register 1 it finds the value of the current argument HK (X0 X). On the adder 2, the 30 addition takes place. Register 5 also contains the value of the current argument, which is a sequential code, starting from the youngest, arrives at the input of register 3. If the current bit is one, then the trailing edge of the C0 signal is entered into the register 3. If the current bit is zero then no entry. This multiplies the multiplicand by the current multiplier of the multiplier and adds it to the product being formed. The resulting product is then shifted one bit towards the lower bits and the circuit is ready for

must be double inverted

result and add a unit to a junior

bit e. The value 1 - 2x will then be 45 multiplied by the next bit multiplier only if P0 is the leading body. After passing the n cycles

the significant bit of the square X (P0) will be

equals zero. So, inverting a non-signal, a signal is generated

verticalization (trigger 11) and new value, Itfx + f (trigger 10). The discharge (the C-signal to the signal C is entered into the register 12, and simultaneously the falling edge of the register 3 is reset to O and the registers 3 are rewritten into registers 1 and 5.

it is necessary if (XKc0i P0 0

2.o4k 0 2Xfc

In this case

2

one

O (pft 1)

2x 1. ...;

1. ... - 1 0. ..., i.e. a positive number is immediately obtained and no inversion is required.

Z.СХ „1 1 - 2хЈсО (Pfl 1)

 2XЈ | -O - 2X0

one .. . .A - 1 0 ... .

f.V

2X2kU

RO, KM V (X,

k o

The obtained logical expressions are implemented respectively with the help of triggers 10, 11 and element 2I-NLI 9. The value Xk + l is written in registers 1 and 5. In this case, if inverted in X, the least significant bit is missing. To compensate for it in the multiplied transfer of the adder, a unit is continuously supplied, if the inversion was performed, otherwise zero is received. The unit in the lower order of the multiplier is made by feeding the unit to the transfer input of the adder 6 when passing

the square is barely done. blowing way. Register 1 contains the value of the current argument XK (X0 X). On the adder 2 is 0 addition. Register 5 also contains the value of the current argument, which is a sequential code, starting from the lowest one, arrives at the input of register entry 3. If the current bit is one, then the falling edge of the C0 signal is entered into register 3. If the current bit is zero, This entry is missing. This multiplies the multiplicand by the current multiplier of the multiplier and adds it to the product being formed. The resulting product is then shifted one bit towards the lower bits and the circuit is ready for

YU

By multiplying the next bit by a multiply signal, a signal is generated.

verticalization (trigger 11) and new value, Itfx + f (trigger 10). The discharge (the C-signal to the signal C is entered into the register 12, simultaneously on the falling edge of the register 3 is reset to 0, and the value of the register 3 is rewritten in registers 1 and 5.

55

Claims (1)

Invention Formula A device for calculating an arcsine function containing two registers, 516 a multi-eraser adder, a one-bit adder, a delay element and the first element 2И-НЧ, and the device argument input is connected to the information input of the first register, the output of which is connected to the first input of the multi-digit adder, the output and the second input are connected respectively to the information input ( The second register and the output of the second register, characterized in that, for the purpose of simplification, it contains the third and fourth registers, the inversion unit, the second epement 2I-OR, and two flip-flops, with the output of the second register connected to the information input of the inversion unit, the output of which is connected to the information input of the first register and information input of the third register, the shift input of which is connected to the input of the device clock and the synchronization input of the second register, the input of the shift and recording resolution of which are connected respectively to the input of the device inverted sync pulses and output sum of one-bit adder, the first and second information inputs of which are connected respectively with the output of the lower bit the third register and the output of the first element 2I-OR, the first input of which through the delay element is connected to the transfer output of a one-bit adder, WITH five about The second and third inputs of the first element 2И-Ш1П are connected to the input of the first clock sequence of the device and the shift input of the fourth register, the information input of which is connected to the inverse output of the first trigger and the first input of the second element 2И-OR, the second and third inputs of which are connected to the output of the higher order Yes, the second register and the information input of the second trigger, the synchronization input of which is connected to the input of the second clock sequence of the device and the synchronization input of the first trigger, information This input and the direct output of which are connected respectively to the output and the fourth input of the second element 2И-ШШ, the inverse output of the second flip-flop is connected to the control input of the inverting unit and the transfer input of the multi-digit adder, the setting input in the second register, the input resolution of the third register and the enable input of the first register is connected to the input of the third clock sequence of the device whose installation input is connected to the installation inputs of the first trigger and the second trigger, W The input of the first element 2I-OR and the third input of the second element 2I-OR are inverse, the output of the fourth register is connected to the output of the device. five 0 stpenno in Oh .f Start W fflffiffiffiffifflfflfflfflffl fflffiffl. % L Sh ҐfflL Ush Yzzk ABOUT Cos 4 %% ШШ% 4% Ш1Ш W & HH% ( Ostanov8 / 7 {/ ek Figure 1 Sh Ush