SU1645982A1 - Phase discriminator of synchro-resolver transducer signals - Google Patents

Description

one

(21) 4625821/09

(22) 12.26.88

(46) 04.30.91. Bul N5 16

(72) B.S. Abezgauz, B.M., Rafalkes

and M. L. Sheep

(53) 621.376.55 (088.8)

(56) USSR author's certificate Ne960722, cl. G 05 B 1 / 01,1981.

(54) PHASE DISCRIMINATOR SQUNAL SQTT-SENSOR

(57) The invention relates to instrumentation. The goal is to increase reliability and enable determination of the sign of the phase change. The discriminator has comparators 4-6, AND-HE elements 7 and 8, ring counters 9 and 10, variable voltage-to-constant voltage converter 11 and inverters 12 and 13. Entity

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of the invention consists in the fact that the voltage from the sinus and cosine windings of the sinus-cosine rotating transformer of the SCWT sensor is converted into a constant voltage, the magnitude of which is determined by the rotation angle of the rotor of the SCWT the sinus (cosine) function of the rotor angle of the SCRT due to the phase mismatch of the corresponding signals of the SCRT sensor and the voltage supplying it, while the polarity of the output voltage changes only after two times confirmation of phase mismatch until the next phase change is preserved, which ensures reliable operation of the device. 2 hp f-ly. 3 il.

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The invention relates to the field of instrumentation, specifically to means of automation and can be used to input analog information into a computer when using a sine-cosine rotating transformer (SCT) as a sensor; determination of the sign of the sine and cosine functions depending on the angle of rotation of the rotor of the SCWT and the formation depending on this deolar polarity.

The goal is to increase reliability, making it possible to determine the sign of the phase change.

FIG. Figure 1 shows the functional diagram of the phase discriminator of the signals of the SSCT sensor; in fig. 2 is a controlled inverter circuit; in FIG. 3, the phase diagram of the operation of the phase l / screener.

The phase discriminator (Fig. 1) contains inputs 1-3, the first, second and third comparators 4--6, the first and second elements AND-NOT 7, 8, the first and second ring counters 9, 10, the inverter 11 of the alternating voltage in the constant This (PPP), the first and second controlled inverters 12, 13, the output 14 of the sinus and the output 15 of the cosine voltage.

The controlled inverter 12 (13) contains (Fig. 2) the first 16 and second 17 keys, the algebraic adder contains four resistors 18, 19, 20, 21, the operational amplifier 22.

The timing diagram (Fig. 3) indicates: a - voltage at the input of the ACS; b - voltage at input 1 at the first (sinus nom) output of the ACS; in - pulses at the output of the comparator 4; g - impulses at the output of someone parator 6; d - pulses at the output of the element AND-NOT 7; e, g, s - pulses on the first, second and third outputs of the first ring counter 9; and - output voltage 14; k - output voltage 15.

The phase discriminator works as follows.

At the outputs of the SCRT sensor are formed and fed to the input 1 and the input 2 of the phase voltage discriminator Ui and U

Ui sin a sin a,

Ua Umaks sin (about t cos a, (1)

where a is the angle of rotation of the anti-burst SKVT;

a) - 2; rf - circular frequency;

f is the frequency of the power supply voltage; one

Kmax is the maximum value of the amplitude of the alternating voltage at the outputs of the ACS.

Compardors 4 5. 6 are null organs that determine the moments of voltage transition at their inputs through zero.

Comparator 4 connected to the first

(sinus) output of the SCRT, determines the zero crossing of the sinus voltage, thus forming square impulses of the square wave type (see Fig. 3 a, b, c). Wherein

a phase jump occurs during the transition from the second to the third and from the fourth to the first quadrants.

The comparator 6. Connected to the second (cosine) output of the CTLC, determines the cosine voltage across the zero, Form a square wave. For the comparator b, the timing diagrams of FIG. 3. graphs a, b, c (only a jump in the cosine voltage phase occurs during the transition

and the first in the second and from the third to the fourth quadrants)

A comparator 5 connected to the inputs 3 determines the zero crossing of the voltage supplying the SCRT, forming square impulses of the square wave type (see, Fig. 3, d). Elements AND 7, 8 are designed to detect the coincidence of the pulses at the outputs, respectively, of the Comparators 4, 6 with the pulses at the output of the comparator 5, then

there are g - determining the coincidence of the phases on the first and second outputs of SSC with the phase of the supply voltage of SSC; When the phase of the sinus voltage coincides with the supply (see FIG. 3 a, b), the pulses on the first and second inputs of the first element AND-HE 7 also coincide, and at its output impuguts are formed (see Fig. 3 1, graphs c, d, e), if the phases do not match, there are no pulses at the output of the AND-NE element 7 (see Fig.

3.2, schedule e).

For the sinus output of the SCRT, the phase of the output voltage coincides with the phase of the input supply voltage in the first and second quadrants (see FIG. 3.1, graphs

a, b) and does not coincide with the third and fourth quadrants (see fig. 3.2. graphics a, b). Similarly, for cosine voltage, the phase coincides in the first and fourth quadrants and does not coincide in the second and third coadrants.

The pulses from the outputs of the elemengs AND-NOT 7, 8, connected by co. Wall-mounted with the R inputs of the ring counters 9, 10, set these counters to the zero state. The output of the comparator 4 is also connected to the C-inputs

ring counters 9, 10. for which information is recorded in the counters.

The ring counters 9, 10 have three outputs. The third output of each counter is connected to its own CE input latch and accordingly to the control input of the inverters 12, 13.

The ring counter 9 (10) is intended for fixing the phase coincidence at the outputs of the comparators 4 and 5 (6 and 5) (while the zero state is fixed at its output) and for fixing the phase mismatch at the outputs of the comparators 4 and 5 (6 and 5) ( then a single state is fixed at its output). The transition of the ring counter from the zero state to a single (when the phase changes) occurs after the second confirmation pulse at the C input, which provides the circuit with increased noise immunity and reliability of the fixation of the phase change.

The controlled inverter 12 is connected by the first (informational) input to the sine output of the variable voltage converter 11 to the constant voltage, and its output is the sine output of the device 14. The controlled inverter 12 is designed to form at the output 14 of the bipolar voltage, depending on the phase of the sinus voltage of the SCRT relative to the supply voltage. When the phases coincide, the output voltage of the inverter 12 forms a positive voltage (see Fig. 3.1, graph k), with a phase mismatch a negative voltage (see Fig. 3.2, graph u).

The controlled inverter 13 is connected to the cosine output of the inverter 11 by the information input, and its output is the cosine output 15 of the phase discriminator. Its purpose is similar to the purpose of the inverter 12 (see Fig. 3, graph k).

The controlled inverter 12 (13) (Fig. 2) can be made according to an algebraic adder circuit with a control key 16 at the input, the normally open contact of which is connected to the information input of the inverter with its first output, and the second to the first summing input of the algebraic the adder and through the resistor 19 to the non-inverting input of the operational amplifier 22 (OU). The normally closed contact of the key 17 connects the second summing input of the algebraic adder to the common bus, and through the resistor 20 it is also connected to the non-inverting input of the OS 22, the inverting input of the OS 22 via the resistor 18 connected to the information input of the algebraic adder and through the resistor 21 s OU output, which is the output of a controlled inverter.

If there is no signal at the inverter control input, the operational amplifier 22 is switched on in non-inverting mode. When the unit is fed to the control input of the keys 16 and 17. they switch and the operational amplifier 22 switches to the inverting operation mode. The controlled inverter 12 (13) can be implemented on a 590KH4 type microcircuit.

The alternating voltage-to-constant-voltage converter 11 is designed to convert the amplitude of the sine and cosine voltages at the outputs of the ACS 1 into constant voltages proportional to the sine and cosine of the angle of rotation of the ACS.

Consider the operation of the converter when processing the sinus function in the first and second quadrants (see Fig. 3.1) and in the third and fourth quadrants (see Fig. 3.2). When the rotor of the SCRT rotates within the first quadrant (0-90 °) or the second quadrant (90-180 °), the voltage at the first (sinus) output of the SCRT coincides in phase with the supply voltage at input 3 (see Fig. 3 b, a). These voltages are fed to the first inputs of the comparators 4, 5, which form from positive half-voltages the same phase pulses (see Fig. 3.1, graphs c, d), coming to the inputs of the AND-NE element 7, the output of which is In this case, pulses are formed that coincide in phase with the supply voltage (see Fig. 3.1, graph e). The pulses from the output of the comparator 5 record information in the ring counters 9, 10 and simultaneously the pulses from the output of the element AND-NE 7 reset the counter 9, and the potential at its third output remains zero (see Fig. 3 1, schedule h), with the result controlled inverter 12 is turned on in a direct voltage transfer circuit from its first input. This input receives a positive voltage from the first output of the converter 11, which converts the alternating sinus voltage from the first output of the ACS to a constant unipolar voltage proportional to the sine of the angle of rotation of the ACSS.

Controlled inverter 12 transmits this voltage without changing sign to output 14.

In the third and fourth quadrants, when the phase of the output voltage of the SCWT (see Fig. 3.2, graph b) is opposite to the phase of the supply voltage (see Fig. 3.2, graph a), the pulses generated by comparators 4 and 5 do not coincide (see Fig. 3.2, graphs c, d), no pulses are generated at the output of the NAND 7 element, and the first pulse from the output of the comparator 5 sets at the first

the ring counter 9 has a zero level, and at its second output a unit level (see Fig. 3.2, graphs e, g), and the second input pulse causes the appearance at the third output of a positive potential, which goes to the CE input (latch) and the occurring state of the counter 9 is recorded (see Fig. 3.2, graph h). A positive potential is applied to the second input of the inverter 12, and the keys 16 and 17 (Fig. 2) switch to form an inverting circuit of the amplifier 22. The positive input signal at the first input of the inverter 12 is converted to negative at its output (see Fig. 3.2, the graph and ).

The part of the phase discriminator circuit works similarly, processing the cosine voltage at the output 2 of the SCRT, consisting of the comparator 6, the element AND-HE 8, the ring counter 10 and the controlled inverter 13. The operation of these elements is illustrated by the time diagrams of FIG. 3.2, (graphs a - e for the first and fourth quadrants, when the cosine voltage at the second output of SSCT coincides in phase with the supply voltage, and timing diagrams of Fig. 3.2, (graphs a - e) for the second and third quadrants, when these the voltages are in antiphase. The voltage at the output 15 is illustrated by the graph for Fig. 3.

The device has an increased noise immunity when determining the phase change due to its fixation not by the first but by the second pulse at the C input of the ring counter, as well as by cyclically confirming the state of the ring counter.

Formula inventions

Claims (3)

1. Phase discriminator of the signals of the SCRT sensor, containing in series the first latching element of the phase change and the inverter and the second latching element of the phase changing and the inverter, as well as the first AND-NES element, characterized in that. in order to increase reliability and enable determination of the sign of the phase change, an alternating voltage converter is introduced into it in a constant, the outputs of which are connected to the information inputs of the first and second inverters, the first and second comparators, the first inputs of which are respectively the first and second inputs of the phase discriminator of the SCRT sensor signals, connected in series to the third comparator, the first input of which is the third input of the phase discriminator signals of the SSCT sensor the second NAND element, to the second input of which and the second input of the first element NAND, and also to the clock inputs of the phase change latching elements, is connected the output of the third comparator, the second input of which, as well as the second inputs of the second and first comparators are connected to the common bus, and the outputs of the first and second elements AND-NOT - to the installation inputs of the first and second elements of fixing the change phases respectively, the outputs of which are connected to their own permissive inputs. 2. The discriminator of claim 1, wherein the first and second inverters comprise an algebraic adder, the subtracting input of which is the information input of the inverter and connected to the first output of the first key, the second output of which is connected to the first totalizing input of the algebraic adder, to the second the summing input of which is connected to the first output of the second key, the second output of which is connected to the common bus, the control wiring of the first and The second keys are the input of the inverter. 3. The discriminator according to claim 1, characterized in that the fixing element of the phase change is made in the form of an annular counter. Fig.Z Editor N. Kol Yes Compiled by V.Pov Kova Tehred M. Morgenthal Proofreader A.Osaulenko