SU1626451A2 - Device for automatic focusing of beam of cathode-ray tube - Google Patents

Abstract

The invention relates to television. The purpose of the invention is to increase the speed. The device contains a CRT 1, a video amplifier 2, an anchor block 3, a limiter 4 below, a limiter 5 above, an integrator 6, a synchronizer 7, an extreme regulator 8, a focusing current source 9, a counter of 10 lines, a task block 11 rows, block 12, match codes, EL 13, grs 14, 16, and 18 pulses, delay blocks 15 and 17, EL OR 19, pulsed bias voltage source 20, constant bias voltage source 1 and adder 22. In this device, the increase in speed is achieved by reducing the time Focusing the beam two beam recording CRT 1. Device of claim 2 f-ly different execution controller 8. given its yl. 1 з п. Ф-лы, 3 Il.

Description

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The invention relates to television, in particular, to automatic tuning systems for storing cathode ray tubes in signal-to-signal converters, which can be used in the radio industry in developing and producing systems for processing, transmitting and displaying video information, in particular air control systems. motion and means of non-destructive testing, and is an improvement device avto.sa. No. 720805.

The purpose of the invention is to increase the speed by reducing the focusing time of the recording beam of a two-beam cathode ray tube.

Fig. 1 shows a block diagram of a device for automatically focusing a beam of a cathode ray tube; Fig. 2 is a block diagram of an extremal regulator; on fig.Z - plot of signals at the outputs of the blocks of the proposed device.

A device for automatically focusing a beam of a cathode ray tube contains a cathode ray tube (CRT) 1. video amplifier 2, block 3, bindings, limiter 4 from below, limiter 5 from above, integrator 6, synchronizer 7, extreme regulator 8, focusing current source 9, 10 lines counter, block 11 for specifying lines, block 12 for matching codes, And 13, the first pulse generator 14, the first delay unit 15, the second pulse generator 16, the second delay block 17, the third pulse generator 18, the element OR 19, the source 20 of the pulse bias voltage, the source 21 of the constant bias voltage and the adder 22. Extreme Regulator 8 (FIG. 2) contains analogue-chi frame converter (ADC) 23. memory register 24, first digital-to-analog converter (DAC) 25, first key 26, comparison unit 27, first pulse generator 28, delay unit 29, second pulse generator 30, reversible counter 31, and second DAC 32, the third pulse generator 33, the clock pulse generator 34, the second key 35 and the fourth pulse generator 36.

The device works as follows.

Lower sync pulses (FIG. 3a) from the third output of the synchronizer 7 are fed to the input of the counter 10 and to the second input of the element 13. From the output of the counter 10, the number of the current line in the parallel code is fed to the first input of the block 12, to the second input of which the output of the block 11 in the parallel code comes the initial number

The helix string. As soon as the current and specified line numbers match, the output of block 12 forms a level (FIG. 3b) of the logical unit, which is fed to the first input of the element AND 13 and to the input of the block 11. At the output of the element And 13 (fig. 3) is the pulse arriving at the input of the first generator 14. The arrival of the level of a logical unit at the input of block 11 causes

0 change its state by one. In this case, the code at the output of block 11 is changed by one, and the logical zero level is formed at the output of block 12. Thus, a group of strings is sampled, starting

5 with some given starting line number. For example, when broadcasting the decomposition standard (50 fields, 625 lines), you need to select lines 200 to 232 for operation of the device. Block 11 must have a ten-bit counter in which the initial code 0001100100 is set. Since it is necessary to allocate 32 lines for operation of the device , then the five least significant bits should work in a cyclic mode.

5 accounts, and the remaining bits must be firmly fixed. As soon as the number of the current line becomes 0001100100, block 12 will begin to issue a logical unit level at its output. At the first coincidence of the codes, unit 1 will be written in block 11, i.e. the code at its output will be 0001100101. The arrival of the sitting line sync pulse will lead to the next match of the codes in block 12. This will continue until those

5 pores until the code at the output of block 11 becomes equal to 0010000100. If five lower bits of the code 00100 are output, the counter is set to the state 0001100100. The match of the current row number and the specified one stops and the row selection becomes possible only in the next frame.

In accordance with the group of selected lines, the first generator 14 generates

5 a packet of pulses with a frequency of lines, which are in time at the beginning of each line (Fig. 3g). Produce the first and then the second delay in the first block 15 (fig.Zd) and in the second block 17 (fig.Zh), the second generator

0 16 (Fig. Ze) and the third generator 18 (Fig. 3) generate working focusing pulses, temporarily located within the line, which are collected by element 19 (Fig. 3) and fed to the input

5 of the source 20. From the output of the source 20, the bias pulses arrive at the first input of the adder 22, to the second input of which a constant bias voltage is supplied from the output of the source 21. Thus, the output voltage of the CRT 1 is read out at the output of the adder 22 (constant bias voltage), and -. The images selected from the camera are provided by pulsed intensive reading of the smallest possible memory of CRT 1.

The video signal from the output of the CRT 1 is amplified by the video amplifier 2 and is fed to block 3, where the constant level of the video signal is tied. From the output of block 3, the video signal is fed to the input of the limiter 4. Since, with intensive reading, the amplitude of the video signal is several times larger than during the working reading mode, the limit threshold is chosen so as to separate the signal only from the parts of the image with intensive reading. The video signal is limited from below by input1, to the input of limiter 5, which converts the video signal into a bi-quantized one.

The integrator 6 calculates the energy of the binary-recognized signal arriving at its input and generates at its output a focus quality signal, which. It takes the minimum value with the best focus, i.e. forms an extremal characteristic with an extreme minimum. The reset of the integrator 6 is performed by the frame sync pulse Tcad.sync duration from the second output of the synchronizer 7. i.e. the integration time is set equal to the read frame triode. The quality signal focusing from the output of the integrator 6 is fed to the input of the extreme regulator 3.

In the extreme controller 8, operation proceeds as follows. From the first output of the synchronizer 7 to the input of the first generator 28 comes a personnel extinguishing impulse with a duration of Gfr. on the leading front of which the fourth generator produces the first working impulse of duration t, which opens the first 26 and second 35 keys. In this case, in block 27, a comparison of the previous value of the focus quality signal stored in digital form in the register 24. and the current focus quality signal from the output of the integrator 6. The comparison signal goes to the control inputs of the reversible counter 31, determining the counting direction in the last. A counting pulse with a duration of tC2, delayed relative to the leading edge of the first working pulse on the tead, is generated by the second generator 30 and is fed to the counting input of a reversible counter

31. AT THIS Gzad + c2 T.

At the end of the first working pulse, the first 26 and second 35 keys are closed and the third generator 33 generates a second working pulse of duration G2, which is fed to the register zero reset input 24 and which wraps its contents with the leading edge, as well as the inputs of the generator 34 and the fourth generator 36.

The generator 34 generates clocking pulses for the duration of the second operating pulse, which converts the current value of the focus quality signal into digital form using the A / D converter 23. At the end of the BT & pjro operation impulse, the fourth generator 36 generates a recording pulse with a duration g3al and enters the recording control record register 24. The current value of the focus quality signal poi ego is digitally recorded in register 2 and stored until the next cycle of the device, when it is Owned with the previous value of the focus quality signal. Wherein

Z i + G + Gzp Tkadr.gas - Gkadr.sichhr.

Thus, in the extremal controller 8, the current value of the signal of the quality of the focusing is transformed into cygr. form, comparing the current value of the focus quality signal with the previous one stored in register 24, generating the control signal as a result of the comparison, as well as storing the current value of the focus quality signal for operation1 in the next cycle. The digital focus control signal is converted by the DAC 32 into an analogue view and is fed to the input of source 9. From the output of source 9, the focusing signal is fed to the focus input of CRT 1.

In the proposed device, in comparison with the known one, the CRT memory control circuit is introduced at two localized parts of the CRT target. In this case, the amplitude of the video signal generated when reading the potential relief from these localized areas is provided. The control circuit of the CRT 1 memory in localized areas, including the counter 10, blocks 11 and 12, e; Oment 13. The first 14, the second 16 and the third 18 renepavors, the first 15 and the second 17 blocks, the element 19, the strainers 20 and 21 of the pulsed and DC bias, respectively, and the adder 22, together with the limiters 4 and 5 device when focusing the beam recording CRT 1 on the video signal generated by

reading the potential relief from the localized areas of the CRT 1 target, where the minimum memory mode is set.

Claims (2)

1. Device for automatic focusing of a beam of a cathode ray tube according to avt.S. No. 720805, characterized in that, in order to increase speed by reducing the focusing time of the recording beam of a two-beam cathode ray tube, a row-connected row counter, a block of coding matches, an AND element are entered, to the second input of which the row counter input and the third output are connected synchronizer, the first pulse generator, the first delay unit, the second pulse generator, the second delay unit, the third pulse generator, the OR element, to the second input of which the output of the second pulse generator is connected, an impulse bias voltage unit and an adder, the output of which is connected to the cathode ray tube memory management office, as well as a constant bias voltage source, the output of which is connected to the second adder input, and a row task unit, the input of which is connected to the output the code match unit, and the outputs are connected to the second inputs of the code match unit. 2. Pop-up device 1, characterized in that the extremal controller contains serially connected analog-to-digital converter (ADC), whose input is the second input of the extreme regulator, memory register, first digital-to-analog converter (DAC), first key , the comparison unit, to the second input of which the ADC input is connected via the first input of the second key, a reversible counter and the second DAC, the output of which is the output of the extreme regulator, connected in series by the first pulse generator, whose input This is the first input of the extreme controller, the delay unit and the second pulse generator, the output of which is connected to the additional input of the reversible counter, as well as the third and fourth pulse generator and clock generator, the input of which is combined with the input of the fourth pulse generator and the second input of the memory register TI and the output of the third pulse generator, the input of which is connected to the second input of the first key, the second input of the second key and the output of the first pulse generator, and the output of the fourth gene Ator pulses is connected to the third input of the memory register and the clock pulse generator output coupled to an input timing of the analog-digital converter. Nakhod and idyuchn FIG. 2 | With the synchronizer 7 : q with  i i III II WITH HB ii with I fg