SU1534469A1 - Device for modelling data collection system - Google Patents

Abstract

The invention relates to computing and can be used to simulate multi-channel microprocessor systems for collecting and processing information. The purpose of the invention is to expand the functionality by simulating channel queries. The goal is achieved by introducing a random pulse generator and a trigger trigger into each channel of the device. The device allows simulating data acquisition systems to determine the temporal characteristics of the service for incoming requests. 3 il.

Description

The invention relates to a computational technique and can be used to simulate multi-channel microprocessor control systems. nor the processing of information.

The purpose of the invention is to expand the iii functionality of the device by simulating channel queries.

Figure 1 shows the block diagram of the device; in fig. 2 - scheme; the algorithm of the device; FIG. 3 is a time diagram of the operation of the device.

The device comprises a clock pulse generator 1, address decoder 2, channel decoder 3, first AND 4 element, shift register 5, AND 6P element group, encoder 7, channel address code switch 8, OR 9 element, second. And 10 and

a group of information transfer channels 11, each of which contains a request indication trigger 12, an AND 13 element, a counter 14, an AND 15 block, a trigger 16; a trigger; a random pulse generator 17, an OR 18 element. The device also contains a write input 19, an address input 20, data bus 21, read input 22, initial setup input 23, interrupt code read input 24, interrupt request output 25, enable interrupt input 26.

The device works as follows.

At the initialization stage, the initial setup signal, which is fed to the input 23, resets the request indication triggers 12 and the counters 14 of all channels 11, as well as the start signal is generated by this signal.

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impulses. The address bus 20 receives the address of the register 5 shift. The decoder 2 addresses on the recording signal, the input to the input 19, selects the shift register 5 signal received from the output of the decoder 2 to the input of the recording of the shift register 5. At the same time, the data of the channel address of the channel from which the cyclical polling of the channels will start will arrive on the data bus 21. The address code is written to the selected shift register 5 by the pulse from the output of the decoder 2 to the input of the shift register record -5. This completes the initialization phase.

After writing the code of the channel address into the 5 shift register, its entry is received from the output of the decoder 2 potential logical zero, which includes the input, shift. The shift of the recorded unit occurs on the pulses of the generator 1, coming from the second output of the generator 1 through the open element AND 4 to the input of the shift of the shift register 5.

An impulse that, at a random time interval, at the generator output of 7 random pulses of the C-rc channel 1 arrives, from one CTOpOjibi, to the input of ipvirrepa 16 starts (trigger 16 is set at the stage that signals the input L 23) from the other side , TVOI impulg. ar-f- minaets in trigger. H. GND is degraded, the signal from the direct byte, Hera 16 turns off the generator. The signal from the direct output of the trigger. querying the request, the counter 14, the counting input of which from the first output of the generator 1 through an open element And 13 enters a sequence of counting pulses, If, arrives. an overflow occurs, the signal from the output of the over-discharge of counter 14 closes the element E 13, and the pulses from the third output of the generator 1 do not flow to the counting input of the counter 14. At the same time, the signal from the direct output of the trigger 12 goes to the second input of the corresponding element And 6 K-th bit of register 5 shift with a signal of a logical unit, coming from the direct output of the K-th trigger 12 of the request, he passed through the element OR 9, goes to the first input of the element And 10, from the output of which the signal if interrupts are enabled (on e 26 polo

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positive potency), is output to output 25 in the form of an interrupt request signal and to the inverse input of the AND 4 element, blocking the operation of the shift register 5. On the basis of the code coming from the output of the group of elements I 6, to vho, de encoder 7, the code of the transition command to the microcomputer memory cell is generated, in which the k-ro channel service subroutine is located. This code is read into the microcomputer by the read signal of the interrupt code received at input 24.

The service routine of the k-ro channel disables interrupts and reads information from counter 14. At the time of executing the read command of the device, the read signal coming from input 22 to the enable input of the decoder j lsiales turns it on. Decoder 3 K.I cash on the basis of the address of the counter, + k-ro channel, incoming chdr ,. entrance

20 devices, sign.shsm k-ro output group of outputs v lfrator opens an element of elements And 15 and the contents of the counter 14 goes to the bus

21 data in the microcomputer.

Analyzing sp.p.- the counter 14, the service subroutine k-ro kanalo-1. tiacTp; device according to the selected algorithm for dispatching Kan-J.-K., writing in shift registers 5

one address of another channel is similar to the initialization stage.

Next, the k-ro channel service routine processes the time characteristics of the k-ro channel and starts the random pulse generator 17, executes the write command to the k-th channel. At the same time at the time of execution. the device write command signal from the k-ro output of the group of second outputs of the address decoder, having passed through the OR element 18, resets the request indication trigger 12, which by the direct output signal resets the counter 14, sets the trigger trigger 16 for the generator with the direct output signal that goes on the permissive input of the generator 17 random pulses, and turn on the generator 17.

Next, the service routine resolves interrupts.

As follows from the consideration of the device operation algorithm, the code of the channel address from which cyclic channel polling will begin is generated by the control program based on the analysis of the time taken by the counter 14 group between the moment the request arrives from the channel until the microcomputer responds. the time from the arrival of signals from the random pulse generator group to the moment when the channel address switch information inputs are operated respectively, the output of the OR element is connected to the inverse input of the first AND element of the device and to the first input of the second And element, the second input and output of which are corresponding to the interrupt enable input and the quit output

command to read the contents of the account - IQ dew interrupt the device, input

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 Thus, the device allows the simulation of data acquisition systems. The statistical characteristics of the model of the interruption code of which is the control input of the channel address switch, the direct outputs of the channel request indication triggers before

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The data acquisition system is determined by the information jg is connected accordingly based on the readings of the counters 14. But with the second inputs of the elements AND group, the input of the initial installation of the device are the combined first inputs of the elements of the OR channels, information transfer, the output of the OR element in each channel the information transfer is connected to the zero input of the request indication trigger, the direct output of which is connected to the inverse reset input of the counter, the counting input of which is connected to the output of the I element of the information transmission channel, and organizational outputs are connected respectively to the information inputs of the block of elements And, the overflow output of the counter is connected to the inverse input of the element AND of the information transmission channel, the input of the device is. the enable input of deciphering the decoder of channels, the outputs of which are connected respectively to the control inputs of the blocks of information transmission channels and channels, different in order to expand functionality by simulating channel requests, each information transmission channel is up to. It additionally contains a random pulse generator and a trigger trigger, where, in each information transmission channel, the output of the random pulse generator is connected to a single request trigger trigger input —and a zero trigger trigger input, the direct output and single input of which are connected respectively to the random pulse generator reset input and to the output of the element of the scientific research institute of the information transmission channel, the group of outputs of the address decoder is connected respectively to the second inputs of the OR elements of the information transmission channels.

A device for simulating a data acquisition system comprising a clock pulse generator, an address decoder, a channel decoder, the first and second AND elements, a shift register, a group of AND elements, an encoder, a channel address switch, an OR element, and a group of information transfer channels, each of which made in the form of a trigger for displaying a request, an OR element, an AND element, a counter, an AND block, and the device’s address input is connected to the information inputs of the address decoder and channel decoder, the device recording input is A decigraphator decryption resolution input address, the first information output of which is connected to the shift register write resolution write input, the device data bus is connected to the shift register information input, the channel address switch output and the element blocks of all information channels, the first output the clock generator is connected to the direct inputs of the element 45 of the top of all information transmission channels, and the second output of the clock generator is connected to the direct input of the first element nTA AND device whose output is connected to the shift register shift input, information outputs of which are connected respectively to the first inputs of the AND elements of the group, the outputs of which are connected respectively to the inputs of the encoder and the inputs of the element OR of the device, the outputs of the encoder connected

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Claims (1)

Claim A device for simulating a data acquisition system containing a clock generator, an address decoder, a channel decoder, first and second AND elements, a shift register, an AND element group, an encoder, a channel address switch, an OR element, as well as a group of information transmission channels, each of which made in the form of a request indication trigger, OR element, AND element, counter, block of AND elements, moreover, the address input of the device is connected to the information inputs of the address decoder and channel decoder, the device recording input is with an enable address for decrypting the address decoder, the first information output of which is connected to the input of the write permission record for the shift register, the data bus of the device is connected to the information input of the shift register, with the output of the channel address switch and with the outputs of the blocks of elements AND of all transmission channels · information, the first output of the generator clock pulses connected to the direct inputs of the elements, And all channels of information transfer, and the second output of the generator. corresponding to the information inputs of the channel address switch, the output of the OR element is connected to the inverse input of the first element AND of the device and to the first input of the second element And, the second input and output of which are respectively the interrupt enable input and the output of the device interrupt request, the read input of the interrupt code of which is the control input of the switch of the channel address, the direct outputs of the trigger for indicating the request for information transfer channels are connected respectively to the second inputs of the elements AND groups, input The device’s initial installation is the combined first inputs of the OR elements of the information transmission channel, the output of the OR element in each information transmission channel is connected to the zero input of the request indication trigger, the direct output of which is connected to the inverse input of the counter reset, the counting input of which is connected to the output of the AND channel element information transmission, and information outputs are connected respectively to the information inputs of the block of AND elements, the overflow counter is connected to the inverse input of the AND element and the transmission of information, the read input of the device is. the decryption decryption enable input is the TPA channels, the outputs of which are connected respectively to the control inputs of the blocks of elements AND information transmission channels, characterized in that, in order to expand functionality by modeling channel requests, each information transmission channel is up to. additionally contains a random pulse generator and a trigger, moreover, in each information transmission channel, the output of the random pulse generator is connected to a single out-of-clock pulse connected to the direct input of the first element AND of the device, the output of which is connected to the shift-shift register input, the information outputs of which are connected respectively to the first inputs of the elements AND groups, the outputs of which are connected respectively to the inputs of the encoder and the inputs of the element OR device, the outputs of the encoder will connect the house. request indication trigger -and with zero trigger trigger input, direct 5θ output and a single input of which are connected respectively to the reset input of the random pulse generator and to the output of the OR element of the information transfer channel, the group of outputs 55 of the address decoder is connected respectively to the second inputs of the elements of OR channels information transfer. titsiamtstsmdet-tune-j devices CPW.Z t-XOKGHaLv doesn’t work · cash dipping fiOWoSCMt M / kastm Belt r-П-м other ^п _пллпгитпдлплллшггш ^ input ZQ input 19 element output I input element shift input / output 21 1 ~ element output ί-element output Direct element output 16 channel 1 element output / 7 channel 1 The output of element 12 of the channel 1 input of the element of M channel 1 input 26 output 25 input 2b input yy FIG. in