SU1511865A2 - Binary code transmission device - Google Patents

Abstract

The invention relates to a data transmission technique and can be used to transmit digital information in information systems. The purpose of the invention is to increase the reliability of the transmitted information. The device contains a transmission side 1, which includes a shift register 2, consisting of flip-flops 3, multiplier block 4, consisting of multipliers 5, an additional multiplier block 6, consisting of multipliers, block 8 of reference signal generators, consisting of reference signal generators 9, additional unit 10 reference signal generators, consisting of reference signal generators 11, adder 12, digital-to-analog converter 13, filter 14, communication channel 15, the receiving side contains a shift register consisting of triggers, multiplier unit, additional multiplier unit, reference signal generator unit, additional reference signal block, first adder, analog-to-digital converter, second adder, memory block, counter block, threshold element. The device allows to increase the reliability of information transmission by optimizing the values of the transmitted code signal during its encoding - decoding by transmitting the binary code values of the unit and zero values with two different pulses. 3 il.

Description

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The invention relates to a technique of data transmission, can be used to transmit digital information in information systems.

The purpose of the invention is to increase the reliability of the transmitted information.

FIG. G shows the functional diagram of the device; Fig 2 is a functional diagram of the receiving side of the device; in fig. 3 - functional multiplier circuit.

The transmitting side 1 (Fig. 1) contains the shift register 2, consisting of triggers 3, multiplier 4 block, consisting of multipliers 5, additional multiplier block 6, consisting of multipliers 7, block 8 of reference signal generators, consisting of generators 9 reference signals, an additional block 10 of reference signal generators, consisting of generators 11 reference signals, adder 12, digital-analog converter 13 ;, filter 14, communication channel 15.

The receiving side 16 (Fig. 2) contains a shift register 17 consisting of triggers 18, a multiplier block 19, consisting of multipliers 20, an additional multiplier block 21, consisting of multipliers 22, a block. 23 reference signal generators, consisting of 24 reference signal generators, additional block 25 of reference signals, consisting of reference signal generators 26, first adder 27, analog-to-digital converter 28, second adder 29, memory block 30, block 31 of counters containing counters 32, the threshold element 33.

The first multipliers 5 (20) (FIGO 3) contain the elements And 34, the second multipliers 7 (21) contain the elements And 35.

The device works as follows.

The transmitted binary code (MAC) enters sequentially into shift register 2 and shifts in it with a time interval

(one)

T - Q

Where

€ is the duration of the pulses Y, (t) and Yjt);

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Q is the number of intervals for which

divides G.

The values of the coefficients of the basis functions Y. (t) HYj (t) for the time intervals t, .ti are T, t + 2T, ..., t., + QT (Q 1,2,3, ...) calculated are pre-formula

ten

Y (t) 5: - (ha, - 1) T

.m, i

hehrГ- / 5 (t, - 1) -t,

(2)

where m is the sequence number of the pulse. y (t) a (t) cos (/ (t); a (t) exp (-. (5Ч), f (t) jw (t) -dt;

w (t) (- / s4) for Y, (t);

w (t) v, eyip {- / H} for Y (t),

subject to w w, (v,) / w: 1

l 4lnc, t.

- have

y

G-, s: 1,

0

five

 the pulse duration y (t), c is the number of times that a (t) and w (t) change and 0 is sent in the form of parallel N-pair spread codes of the function Y., (t) to the corresponding transverse the inhabitants are 5 blocks 4, and the functions are Y, (t) to the corresponding pendants 5 multipliers 7 of block 6.

The values of the basis functions are calculated starting from the moment of time corresponding to the maximum value of the derivative function y (t) and 0 equal to 1 / ft, and the sine function for y (t) is zero at this point. As a result, in blocks 4 and 6, one-to-one MPC multiplication occurs by the corresponding values of the coefficients of the basis functions.

When transmitting 1, the direct outputs of the flip-flops 3 of the register 2 permit the passage of parallel N-bit codes from the output of block 8 through the block of multipliers 4, which corresponds to the transfer of samples of the function Y, (t). The inverse outputs of the triggers of block 30 in this case prohibit the passage of samples Y, (t) through the multipliers.

unit 6, with the result that after summing up in unit 12 and converting the sum in the digital-to-analog converter 13, the output of block 14 will be in each T signal

 d. rrXr. ,,, - Y, (k.T) +

VM.).

(3)

At the receiving side analog-to-digital converter 28 in each T signal and; digitized and fed to a second adder 29, which performs the operation

 and - and.

 l

-d, (4)

where and

- value of modulating

signal;

d is the constant code. Since this is a binary code, then there can be two different values in each T. Before starting, these values are calculated and stored in memory block 30.

In each T, one of the Up codes enters the input of the memory block 30, with which the binary L-bit word is read from the memory, 1 in any bit which means the presence of 1 in the corresponding MAC level. The units of the corresponding bits from the output of memory block 30 are added (or are not added in the case of zeros) to the contents of the correspondence; their counters are "Before the next measure, the contents of each J-ro counter (where J 1,2,3 , о. ,, b) is rewritten into (j +1) -th counter, then the 1st counter is reset.

Thus, after L clock cycles in the leftmost counter, there is an accumulation of units equal to the number of cases when this unit is defined as unit. If this number of units is greater than L / 2, the threshold element 33 forms a unit at the output if it is less than or equal to L / 2 - zero.

the output of the threshold element 33 is the value of the formed p1azr and the drift. ts into the shift register 17, pos

,

5118656

The blocks 19 and 21 of the multipliers produce the operation + i + xy (1T) and feed these values to the first multi-input adder 27.

The operation of blocks 17,19,23,25 and 21 is similar to the operation of blocks 2,4,8,6 and 10 o In each T, in subtraction in block 29, the contents of block 27 from

Q block contents 28.

The use of pulses of the form Y, (t) and Y, j (t) for transmitting a binary code makes it possible to achieve an increase in the reliability of information transfer due to

15 optimize the values of U p; when encoding and decoding transmitted information.

Claims (1)

Invention Formula 20 five 0 0 five Device for transmitting a binary code by author. St. No. 1325718, characterized in that, in order to increase the reliability of the transmitted information, an additional block of reference signal generators and an additional block of multipliers are introduced on the transmitting side, the inverse outputs of the shift register are connected to the corresponding first inputs. Dami additional multiplier unit, the second inputs of which are connected to the corresponding outputs of the additional block of generators of the reference signals, the outputs of the additional multiplier unit are combined with the corresponding outputs of the multiplier unit, on the receiving side; an additional block of reference signal generators and an additional multiplier unit are introduced, the inverse outputs of the shift register are connected to the corresponding first inputs of the additional multiplier unit, the second inputs of which are connected to the corresponding outputs of the additional multiplier unit and combined with the corresponding outputs of the multiplier unit, the third input of the second adder is by entering a constant number code. 0 output 5 (20 2