SU1506463A1 - Identifier of binary signal combination - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase speed. The detector contains the shift register 1, the memory block 2, the adder 5, the threshold block 6, the threshold register 7, the information input 9, the clock input 10. The goal is achieved by introducing into the detector Q sequentially connected additional shift registers 3, Q additional memory blocks 4, Q = N / M-1, where N is the number of bits of the combination of binary signals

M is the number of bits of each of the series-connected shift registers 3, and D is a trigger 8. The detector analyzes the stream of received binary signals, followed by clock pulses, in each clock interval (the interval between adjacent clock pulses) calculates a correlation number equal to positions on which the selective combination coincides with the standard, and forms the decision on the detection of the combination, if this number is not less than the threshold. 1 il.

Description

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The invention relates to communication technology and can be used in discrete message processing devices for detecting a combination of binary signals of a known type with an unknown time of its arrival in a stream of binary signals.

The purpose of the invention is to increase speed.

The drawing shows a structural electrical circuit for detecting a combination of binary signals.

The binary signal detector comprises a first shift register 1, a first memory block 2, q successively connected additional shift registers 3 (where q

2,

3, ...), q additional memory blocks 4, adder 5, threshold block 6, threshold register 7, D-flip-flop 8, information input 9, clock input 10

The binary pattern detector operates as follows. The binary signal detector analyzes the stream of received binary signals, followed by clock pulses, in each clock interval (the interval between adjacent clock pulses) calculates a correlation number equal to the number of information points on which the orbit combination coincides with the standard, and forms a decision about the detection combinations, if this number is not less than the threshold.

The received binary signals in the form of a sequence of elementary parcels O, 1 are received via information input 9 to the input of the first shift register 1, to the other input of which act pulses synchronized with binary signals are received. The next clock pulse from clock input 1C also goes to clock input q of successively connected additional 3 shift registers and shifts their contents and the contents of the first shift register 1 by one bit towards the higher bits (in the direction of the shift registers output). As a result, in each clock interval, in the first shift register 1 in q the serially connected additional shift registers 3 contain the N-bit of the selective pattern formed by the binary signals received in this and N-1 preceding clock intervals

lakh, where N is the number of binary signals in the standard, i.e. in a detectable combination. At the same time, in the first shift register 1 and in each of the q consecutively connected additional shift registers 3, the t-bit word of the selected combination is contained, where m

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The words of the selective combination from the code outputs of the first shift register 1 and q serially connected additional shift registers 3 arrive in parallel code to the address inputs of the first memory block 2 and q additional memory blocks D, and the contents of the addressable cells are read to their outputs. The cells of the first block 2 of memory and each q of the additional block 4 of memory form a table of correlation codes representing the number of information positions of the corresponding t-bit word of the reference, on which it coincides with the addresses of the cells. As a result, the output of the first memory block 2 and each of the q additional 4 memory blocks (, 2, ..., q) reads the code of the number of information positions at which the i-e word of the selective combination coincides with the i-M word of the reference. For example, the standard word 1100110X (the symbol X denotes a non-informational position excluded from the analysis) when a word of a selective combination 11000100 arrives at the output, the code of number 6 is counted, and for a standard 11100110 (all informational positions), when the elephant of the selective combination 11100111 arrives, the code of number 7 is read.

Correlation number codes are sent to the corresponding inputs of adder 5, which at outputs outputs a code of the sum of correlation numbers equal to the number of information positions at which the selective combination coincides with the EA. If this number is not less than the threshold number contained in the threshold register 7, then the threshold unit 6 generates at its output a combination detection signal, which is recorded in the D-flip-flop 8 by the next clock pulse received at its sync input from the clock input 10 and outputted binary signal detector

Claims (1)

Invention Formula A binary pattern detector that contains the first shift register, the first input of which is an information input of the binary combination detector, whose clock input is the second input of the first shift register, the first group of outputs of which is connected to the first input group through the first memory block adder, and the first group of inputs of the threshold block is connected to the outputs of the threshold register, which means that, in order to improve speed, q are entered in series with l shift registers, to the information input of the first of which the output of the first register is connected the shift, q additional memory blocks, to the address inputs of which the code outputs of the corresponding q serially connected additional shift registers are connected, where q N / m - 1, N is the number of bits of the binary signal combination; m is the number of bits of each of the serially connected additional shift registers, the outputs q of additional memory blocks are connected to other inputs of the adder, the outputs of which are connected to the second group of inputs of the threshold block, and the D-flip-flop, the information input of the threshold block, synchronous input D-flip-flops and the second inputs q of the series-connected additional shift registers are connected to the second input of the first shift register.