SU1499338A1 - Device for raising to power - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of specialized computers and functional converters. The purpose of the invention is to expand the class of tasks to be accomplished due to the additional possibility of raising to a geometrically increasing degree the numbers specified by a sequence of pulses or a sequential positional code. The goal is achieved by the fact that the device containing two counters 1 and 2, the first 5 and the second 6 triggers, the first group of 8 elements AND, elements 11-18, elements OR 19-22, entered the second 9 and the third 7 groups of elements AND adder 4, delay elements 23-27. 1 il.

Description

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The invention relates to the field of automation and computing, in particular, can be used in the construction of specialized computers and functional converters,

The purpose of the invention is the expansion of the class of tasks due to the additional possibility of raising to a geometrically increasing degree the numbers defined by a sequence of pulses or a sequential positional code.

The drawing shows a block diagram of a device for exponentiation

The diagram shows: counters 1 and 2, shift register 3, adder 4, triggers 5 and 6, groups of elements AND 7–9, group of elements OR 10, elements 11, 12, 13-18, OR 19-22, elements 23 - 27 delays, information input 28, inputs 29-31 of the task enter the information inputs of the group of elements AND 8 through the rpyimy of the elements OR 10) “Then the pulse from the output of the element AND 15 passes through the element 25 of the delay, elements AND 14, OR 21 and added em unit to the contents of the counter 1.

Similar calculations were carried out for 10 seconds for each pulse received at the information input 28 of the device,

A reset signal, coming after the number X at the input 33, through the element

15 OR 19 sets the trigger 5 to one and subtracts the unit from the number K recorded in counter 2. If the value of K K-1 is zero, then the output of the OR 20 element will be at the left 20 and the calculation process is terminated. At the same time in the adder 4 will be the value of X „

In case the value of KK-1 is greater than zero, then at the output of the clamp element, clock input 32, input 33 reset 25 OR 20, a single signal remains.

Sa, control input 34, output 35 of counter 1.

The device works as follows

When erected in a geometrically increasing manner, the degree of the number X defined by a sequence of pulses and arriving at information input 28, must have a single input at input 29, and zero signals at device inputs 30, 31, and 34. At that, counter 1 and adder 4 are free, and counter 2 should contain the number K equal to the binary logarithm of the degree (for example, for degree 2, the number I; for degree 2, the number 2; for degree 2, the number K), resulting in the output of the OR element 20 there is a single signal However, at the input 32 they receive t such as are for pulses of a certain frequency, and the flip-flops 5 and 6 - the zero state

With the arrival of the first pulse, the information input 28 through the AND 15 element adds one to the contents of the adder 4. In addition, the pulse from the output of the element 15 opens a group of elements from the I, through which the contents of counter 1 is transferred to the first group of inputs (in n the least significant bits) of the adder 4 with a shift of one bit to the left, double the value (the contents of counter 1 through 35

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This impulse from the output of the element OR 19 passes through the element 23 of the delay, as a result of which a single signal occurs at the output of the element And 12. This signal through the element OR 22 sets the counter 1 and the shift register 3 to the zero state, and then through the delay element 26 writes the contents of the adder 4 into the shift register 3 and sets a number in the counter 1 in the additional code equal to the number of bits of the shift register n 3 . Further, the signal from the input of the delay element 26 through the delay element 27 sets the adder 4 to the zero state, and three: - ger 6 - to the single state. At the same time on a single output. Trigger 6, a single signal occurs.

If the output of the first (youngest) bit of the 3 shift register is a single signal, then the first clock pulse arriving at input 32; through element I. 13 opens the group

The 50 elements And 7, through which the contents of the register 3 shift, except for the least significant bit, are transmitted to the second group of inputs (in n + 1. most significant bits) of the adder 4 with the shift

55 one bit to the left, i.e. double value. However, one is added to the contents of adder 4 at (2n + 1) -th bit. Then the first tick pulse through the element And 11 and 45

steps on the information inputs of the group of elements AND 8 through the rpyimy of the elements OR 10) "Then the pulse from the output of the element 15 goes through the element 25 of the delay, elements 14 and OR 21 and adds one to the contents of counter 1.

Similar calculations are performed for each pulse arriving at device information input 28,

A reset signal, coming after the number X at the input 33, through the element

OR 19 sets the trigger 5 to one and subtracts one from the number K recorded in counter 2. If the value of K K-1 is zero, then the output of the element OR 20 will have a zero signal and the calculation process will stop. At the same time in the adder 4 will be the value of X „

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This impulse from the output of the element OR 19 passes through the element 23 of the delay, as a result of which a single signal appears at the output of the element And 12. This signal through the element OR 22 sets the counter 1 and the shift register 3 to the zero state, and then through the delay element 26 writes the contents of the adder 4 into the shift register 3 and sets a number in the counter 1 in the additional code equal to the number of bits of the shift register n 3 . Further, the signal from the input of the delay element 26 through the delay element 27 sets the adder 4 to the zero state, and three: - ger 6 - to the single state. At the same time on a single output. Trigger 6, a single signal occurs.

If the output of the first (youngest) bit of the 3 shift register is a single signal, then the first clock pulse arriving at input 32; through element I. 13 opens the group

0 elements And 7, through which the contents of the register 3 shift, except the youngest bit, is transmitted to the second group of inputs (in n + 1. most significant bits) of the adder 4 with a shift

5 one bit to the left, i.e. double value. However, one is added to the contents of adder 4 at (2n + 1) -th bit. Then the first tick pulse through the element 11 and 5

five

the delay element 24 shifts the contents of the adder 4 by two bits to the right and the shift of the contents of the register 3 shifts by one bit to the right

In addition, the pulse from the output of the delay element 24 passes through the OR element 21 and adds one to the contents of the counter 1 o

If the output of the least significant bit is a zero signal, then the first clock pulse through the AND element only and the delay element 24 shifts the content adder 4 by two bits to the right and the shift of the shift register 3 by one bit to the right. In this case, the pulse from the output of the delay element 24 also passes through the element 21 21 and adds one to the contents of counter 1.

Similar calculations are performed for each clock pulse received at input 32. After shifting the number in shift register 3, n pulses go to counter 1, resulting in a single signal at output 35 of this counter, which sets trigger 6 to zero. the Due to this, the arrival of the clock pulses through the elements And 13 and 11 is terminated. However, a single signal from the output 35 of the counter 1 through the elements OR 19 subtracts one from the number K recorded in the counter 2 ..

If K K-1 is greater than zero, then a single signal will remain at the output of the OR 20 element. While a single signal from the output of the element OR 19 passes through the element 23 of the delay, resulting in the output element And 12 there is a single signal.

Next, the device works as described.

If the value of KK-1 is zero, then a zero signal occurs at the output of the OR 20 element and the calculation process is terminated.

As a result, in adder 4, there will be a value x, where K is the initial value recorded in the slice 2 „

Work must be single, and at inputs 29 and 31 there are zero signals. In this case, the shift register 3, the adder 4 and the counter I are free, and the counter 2 records the number K equal to the binary logarithm of the degree, so that the output of the OR 20 element is the 1 st signal. However, the input pulses 32 frequencies, and triggers 5 and 6 are in the zero state

In the first cycle, a single signal is received at the control input 34, which, through the element 17, shifts the contents of the adder 4 and the shift register 3 by two and one bits to the left, respectively. In the second cycle, if there is a unit in the given bit of a serial code arriving at the device information input 28, the unit 15 is added to the contents of the adder 4 In addition, the pulse from the output of the And 15 element opens the group of elements And 8 through which the contents of the register 3 shifts, except for: the first least significant bit, is transmitted to the first group of inputs of the adder 4 with a shift of one bit to the left, i.e. a double value. Then the pulse from the output of the element And 15 passes through the element 25 of the delay, the element And 16 and writes a unit in the register 3 shift.

If there is no unit in this bit n of the sequential code arriving at the device information input 28, the second clock is not executed.

Analogue computing is performed for each bit received at device information input 28.

After the end of the number x specified by the sequential positional code, a reset signal is sent to the input 33. In this case, the subsequent calculations are performed in the device as when a reset signal is received after the number specified by the sequence of pulses. As a result

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in the adder 4 will be the value of x. In the case of raising to the power of

In the case of construction in a geometric, given by a parallel code, the increasing degree of the number x, at the input of the mode setting 31, must be given a serial positional one, and at the inputs 28, 29,

.30, 33 and 34 devices are zero signals. At the same time, in the adder 4 by the record and arriving at the information input 28, on the bus 30 of the task, the number is to be raised to the power 2, and in the counter 2 the number K is equal to the binary logarithm of the degree, as a result of which the output element OR 20 is signal At the same time, the input of 32 receives clock pulses of a certain frequency, and a trigger; 1 5 and 6 - in the zero state.

The first clock pulse arriving at input 32 passes through AND 18 and OR 22o elements. Next, the device works as when a single signal passes from an AND 12 element output through an OR 22 element while raising the power of the number specified by a sequence of pulses. As a result, in the adder 4, the value x will be written.

Claims (1)

Invention Formula A device for raising to a power containing two counters, a register, the first and second triggers, the first group of elements AND, the elements AND, OR, a group of elements OR, characterized in that, in order to expand the class of tasks to be accomplished by providing an additional possibility of a geometrically increasing degree of the numbers specified by a sequential positional code or a sequence of pulses, the second and 1 grid of the group of elements I, the adder and the delay elements are entered into it, and the informational 1st input device is connected with the first input of the first element And, the output of which is directly connected to the first input of the adder and the control inputs of the elements of the first group, and through the first element of the delay to the first inputs of the second and third elements And, the second input of the last and the first input of the fourth element I are connected to the first input of the device mode setting, the second and third inputs of the mode setting of which are connected respectively to the first input of the fifth And element and the second input of the second And element, the outputs of which are connected to the first inputs of the first and second elements OR, respectively, the output of the first of which is connected directly to the installation inputs of the first counter and shift register, and five 0 five 0 five cut the second delay element - with the control inputs of the AND elements of the second group, with the input of the third delay element and the information input of the first counter, the output of which is connected to the installation input O of the first trigger and the first input of the third OR element, the second input of which is connected to the device reset input and the output - with the installation input in 1 of the second trigger, with the counting input of the second counter and the input of the fourth delay element, the output of which is connected to the first input of the sixth element And, the second input of which is connected to the output of the fourth element OR, whose input is connected to the output of the second counter, the inverse output of the second trigger is connected to the second inputs of the first and fourth elements AND, the third input of the last of which is connected to the control input of the device, and the output to the first control inputs of the shift register and an adder, the second control inputs of which and the second input of the second element OR are connected to the output of the fifth delay element, the input of which is connected to the output of the seventh element AND, the first input of which and the first inputs of the fifth and eighth About elements And are connected to the clock input of the device, the second inputs of the seventh and eighth elements And are connected to the direct output of the first trigger, the inverse output of which is connected to the third input of the fifth And, and the input of the installation to 1 40 the output of the third delay element and the input of the installation in About the adder, the outputs of which are connected to the information inputs of the elements And the second group, the outputs of the elements And which are connected to the information inputs the shift register, the third control input of which is connected to the code of the third element AND, the third input of the eighth element AND is connected to the output of the shift register, and the output is connected to the second. the input of the adder and the control inputs of the elements AND of the third group, the informational inputs of the elements of the swarm and the first inputs of the elements of the OR group are connected to the group of outputs the shift register, the second inputs and outputs of the elements OR of the group are connected respectively to the bit outputs of the first count and to the information inputs of the elements AND of the first group 149933810 , py, outputs of the elements AND of which and the inputs of the adder respectively, the output of the elements of the third group and the third input of the first element OR are connected with the first and second groups with the output of the sixth element I.