SU1453408A1 - Apparatus for debugging a microprocessor system - Google Patents

Abstract

The invention relates to an automation technology for developing microprocessor systems and is intended for use in in-circuit emulators. The aim of the invention is to simplify the device and the associated emulator. The device contains a call decoder 9, registers 8 and 20, multiplexer 12, block 13 of code comparison, BAN elements 23 and OR 21, register register block 18, restart code generator 22, three groups of NOT elements and state definition block 7. 1 hp F-ly, 5 Sh1. § (L s

Description

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 1453408

This invention relates to a microprocessor development automation technology and is intended for use in in-circuit emulators replacing a microprocessor-based non-conveyor architecture with an open bus system in an exhaust system.

The purpose of the invention is to simplify the device.

Fig. 1 shows a functional diagram of a device for debugging a microprocessor system; 2 is a functional diagram of the state determination unit in FIG. 3 is a functional block comparison code diagram; FIG. 4 is a functional block diagram of the register memory of FIG. 5 - diagram of the algorithm of the device.

In the diagram of the device (Fig. 1), the following two are shown: input 1, initialization of the device, line 2 of the I / O reading of the control computer system (CID), third line 3 of the BAC ban,

Line 4 records the input of the UVS, ad- 25 are looking for a device (ROM) EVM resna bus 5 UVS, line 6 of reading par-rii1.1ve JBM.

mi UVS, block 7 definitions of the state - the first register 8, decyfrator, 9

five

Code Comparison Unit (holds key 52, 53 code scheme, element OR 54, el

The register memory block contains the registers 56.1 and the lower boundaries of the loan zones 57.1 and 57.2 of the upper loan memory, adders 58.1, 58 59.2, elements OR 60.1, and elements 61.1 and 61.2, electric 62,

As a control system is used

The functional assigned components of the next device initialization on the computer initialization line pour the computer into a state, the system monitor starts its operation with a torus, i.e. initialization processor is delivered to the beginning of the program written in constant

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calls, bus 10 of the system being debugged ,, address bus 11 of the system being debugged, multiplexer 12, block 13 compared and codes, line 14 of the HCS memory record, first output 15 of the block. state determination, the second output 16 of the state definition unit, the line 17 of the sign of the first cycle of the command yBCs block 18 of the register memory - THj the second output 19 of the device, the second register 20, the OR element 21, the shaper 22 of the restart code, the BAN element 23, the first group of 24 elements is NOT, the first is 25, the second is 26 and tertiary is 27 elements are NOT the first group, the third is group 28 elements are NOT ,, first 29 and the second 30 elements are NOT the third group, the second group is 31 elements NOT, the first is 32 and the second is 33 elements Not the second group, the first line 34 of the ban on hydrocarbons, the second line 35 of the ban on hydrocarbons, vy output device 36, the first and second 38 .37 kschie control unit inputs conditions, the tire 39 UCS data.

The state determination unit (Fig. 2) contains the first 40, the second 41 and the Tium 42 And elements, the first 43 and the second 44 transition decoders, the first 45, the second 46, the third 47 and the fourth 48 elements OR, the first 49, the second -50 and third 51 triggers.

Line 2 reading output device (UVV) is active, if the address is set to stabilize UVV, which is read or computed by the computer processor.

The line 3 is blocked by the UVZ act and it is required to prohibit the circulation belonging to the computer, therefore the second 20 registers, block, are UVV, belonging as chosen by its monitor

Line 4 of the UVV asset record on the 5 address bus sets the address of the UVV to which the entry is written or to be written.

Address bus 5 serves as the address of the memorized mouth (RAM) or air-blast on the D2 highway, including to the emulsion control unit emul

The read line 6 is active, the 5 address bus is located the address of the memory cell, which will be read or

The determination unit 7 consists of the main structural structure of the device that discriminates the memorized state of the computer: EXCHANGE, OPERATION.

The first register 8 memorizes in it the debug interrupt monitor, for example break points, coma codes

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5 We are looking for a device (ROM) EVM RI1.1ve JBM.

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The code comparison block (Fig. 3) contains a key 52, a code matching circuit 53, an OR element 54, an AND 55 element.

The register memory block (Fig. 4) contains memory registers 56.1 and 56.2 of the lower boundaries of the loan zones, registers 57.1 and 57.2 of the memory of the upper boundaries of the loan zones, adders 58.1, 58.2, 59.1 and 59.2, the elements OR 60.1 and 60.2, the AND elements 61.1 and 61.2, element OR 62,

A computer is used as a control computer system.

The functional purpose of the structural components is the following. The device initialization line is connected to the device initialization input; it sets the computer to the state when its system monitor debugger starts its operation, i.e. After initialization, the processor of the computer refers to the beginning of the monitor program recorded in the permanent memory 25 looking for a computer device (ROM) 1.1Me JBM.

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Line 2 of the I / O device readout is active if the addresses of the addresses have a stable UVV address that is read or will be read by the computer processor.

The grenade line 3 is UVZ active if it is required to prohibit access to computer-controlled UVV, so the first 8 and second 20 registers, blocks 13 and 18 are computer-owned UVV, as selected by its monitor.

Line 4 of the UVV record is active if the stable address of the UVV is set on the 5 address bus, in which the computer records or will write information.

Address bus 5 serves to transfer the address of the memorizing device (memory) or the air-blast device along the main line of the computer to its D2 blocks, including the emulator and to the control device of the emulator.

The read line 6 is active if on the 5 address bus there is a stable address of the memory cell that is read or will be read by the computer processor.

The state determination unit 7 is the main structural component of the device discriminating and storing the computer state: MONITOR EXCHANGE, OPERATION.

The first register 8 memorizes the debugging interrupt conditions programmed in it by the monitor, for example, addresses of break points, command codes, up to 50

55

the completeness of which you need to know the state of the program or system being debugged, etc. The width of the first register 8 can exceed the width of the ES data bus, so it can be programmed in several stages.

Bus 10 of the data being debugged by the computer processor as the first byte of the command.

Register memory block 18 enters the memory addressable areas that will be occupied by the system being debugged. The output of block 18 may, during a computer cycle, be in the state of a logical unit, provided

We are the data bus of the emulated current address of the memory or the UEV without a microprocessor, or it is connected to the appropriate computer and is resolving to the fifth. it through the buffer. the input of block 18 enters the logical

Bus 11 of the addresses of the system being debugged is a bus of addresses of the emulated microprocessor or is connected to it via a buffer.

Tires 1O and 11, if the system being debugged is physically absent, can be connected to tires 39 and 5 computers. In this case, the operability of the device is fully preserved.

The multiplexer 12 connects to the second information input of the block 13 or the data bus 10, or the bus 11 addresses of the system being debugged.

Unit 13 compares the codes on the second information input and the part of the first information input; the other part of the first information input determines the types of computer cycles in which the codes may coincide. If in the current cycle of a given type a coincidence of codes is detected, then during such a cycle, the output of block 13 receives a logical unit. For example, if a break point is set, then if the address of the break point is set on the address bus 5, the address will be gated in this case by combining the read memory signals and the sign of the first command cycle, then block 13 will work.

The memory write line 14 is active if there is a stable memory cell address on the 5 address bus that is read or will be read by the processor.

The first output 15 of the state definition block is active if the memory cell is available to the monitor, masked either by monitor resources or resources of the system being debugged.

The second output 16 of the state definition unit is active if the computer is running a user program.

The line 17 of the sign of the first cycle of the command is active if on the bus of 5 addresses there is a stable address g of the memory cell, the contents of which will be

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unit.

Device output 19 is active if a user program is being executed. A timer can be connected to the output 19 of the device to directly measure the speed of the user programs. In this case, debugging interrupts will not affect the results of the measures, since if you terminate the debugging, the logical unit from the output 19 of the device will be automatically removed. In addition, the output 19 of the device can be used to control the tracer of the charger, which is included in the emulator or computer, and store the debugging history before it is interrupted using the BLSUK 13.

The second register 20 is an ES control device register. Depending on the state of the first output of the second register 20, either the data bus 10 or the address bus 11 of the debugging system is connected to the second information input of the block 13. By a logical unit coming from the second output of register 20, block 7 can be transferred to the EXCHANGE state with the resource disabled | sov monitor. The logical unit at the third output of the second register 20 is resolved by software through the OR 21 element, triggering the block 18, if this is not permitted via the other two inputs of the OR 21 element from the outputs 15 and 16 of block 7.

The element PfflH 21 collects the signals allowing the register memory 18 to be activated by the fifth resolution input.

The shaper 22 of the restart code i on the data bus 39 is one of the restart codes reserved in the computer for processing program debugging interrupts if the logical unit enters the input of the shaper 22.

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The element BAN 23 prohibits the activity of the first output 36 of the device. abort debugging regardless of the address at which the interrupt occurs.

The first group of 24 elements, HE 25-27, inhibits the resources of the monitor, if at least one of the inputs of the inverters contains a logical unit. The latter is possible if a shuttle call is performed at an address masked by monitor resources, at which the logical unit comes from the first output 15 of block 7 to the input of the NOT element 25, or a user program is executed, at which the logical unit comes from the output 16 of block 7 to the input of the element NOT 26, or a restart code is generated by the formatter 22, the log of which is the log of the unit coming from the output of block 13 to the input of the element HE 27.

Third group of 28 elements NOT for

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prevents UVV ESh, if at least one by shaper 22

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The first output 36 is terminated in a state of logic, if in the current cycle g the processor is turning on the proper debugging

At the first input 37, the logical unit of the activity of the output of 15 current units and the disconnection of the receiver (its ROM and

At the second input, 38 blanks, upon detecting a block of the VIY, a debugging interrupt unit, returning 7 to the initial state.

The data bus comes from the data bus 39, 20 for programming the power of the first 8 and into the gistra, block 18. On the w computer reads from the device of the block 13 and the restart code

There is a logical one among the inputs of the elements HE 29 and 30. The latter is possible if a shuttle call is performed at an address masked by monitor resources, at which the logical unit comes from the first output 15 of block 7 to the input of the element HE 30, or the program is executed. user Logical unit in

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16 block 7 to the input element NOT 29.

The second group of 31 elements, HE 32 and 33, prohibits the RAM of the EL, if at least one of the inputs of the elements 32 and 33 has a logical one. This is possible if the memory block treats the current memory address as not belonging to ET, but the restart code is not generated by shaper 22, and the logical unit from the code of the BAN 23 is input to the input of the HE element 33, or the restart code is generated by the 22 shader code, and a logical unit arrives from the output of block 13 to the input element HE 32.

Line 34 disables monitor resources; Pa in the current cycle of the computer processor if there is an active low potential on line 34.

Line 35 prohibits computer RAM in the current cycle of the computer processor if line 35 has an actual low potential.

The AND 40 element in the loop permits decoding of a de 43 state transition, a 5 ESH, if the preliminary 30 first trigger 49.

Element And 41 in the loop permits decoding the desh transition state of the address of the computer, if previously

Element And 42 resolves the first trigger 49 and the first trigger 50, if the second three

40 The first decoder 43 bats, if the processor is an ice byte of the address of the monitor peer. The address of the transition is generated moni

45 computers at a fixed hell

The second decoder 44 will work if the process is to execute the programs, read the last b of the 50 registers of the operating memory of the monitor's memory.

The element IL 45 is assembled from the output of the first decryption of the gg transitions (the first signal) of the computer initialization (the second reset of the first trigger

Element OR 46 is collected from initialization line 1

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wiuRa and and rest code

5 by shaper 22

The first device output 36 is in the state of a logical unit if in the current cycle of operation of the computer g the processor is accessing the address belonging to the system being debugged.

A logical unit is placed at the first input 37 of block 7 with a working fragment of the ES monitor, which causes the output 15 of block 7 of the state to be active and the monitor's resources (its ROM and working memory) are disconnected.

At the second input 38 of the block of 7 states, when the block 13 detects the condition of the VIA 5 debugging interrupt, a logical unit is placed returning the block 7 to the initial state.

The data bus 39 from the computer in the device receives the data required by 0 for the monitor to program the contents of the first 8 and second 20 registers, block 18. The computer data bus 39 reads from the device the state of block 13 and the restart code generated by the shaper 22

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Element I 40 in the read cycle of the memory device allows decoding by the decoder 43 a state transition of the address bus 5 of the ECH, if the 30 first trigger 49 is previously set.

Element And 41 in the read cycle of the memory device allows decoding by the decoder 44 a state transition of the address bus 5 of the computer, if previously installed

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Element And 42 allows the installation of the first trigger 49 and the reset of the second trigger 50, if the second trigger 50 is previously set.

The first transition decoder 43 is triggered if the processor reads the last byte of the address of the transition to the monitor's ROM. The transition address is pre-generated by the monitor in RAM.

Computer at a fixed address.

The second descrambler of the 44 transition triggers, if the processor goes to the user program execution, read the last byte of the pseudo-register program counter from the monitor's working memory.

The IL 45 element collects signals from the output of the first decoder 43 transitions (the first signal) and from the computer initialization line 1 (the second signal) to reset the first trigger 49.

Element OR 46 collects the signals m of the computer initialization line 1. (the first

7,

signal) and from the second permitting input 38 of block 7 for setting up the second trigger 50 and simultaneously resetting the third trigger 51.

The OR 47 element collects signals from the second transition decoder 44 (first signal) and from the first enable input 37 of block 7 (second signal) to reset the second trigger 50. The second signal to — reset the second trigger 50, provided that the latter is preset, which is provided the third element and 42.

The OR 48 element collects the signals: the ES initialization (the first signal, which also passes through the third element OR 47, coming from line 1), control via the second input 38 of block 7 (the second signal, which also passes through the third element OR 47) , the operation of the first decoder 43 transitions (the third signal). In all these cases, a second trigger 50 is set.

The first trigger 49 is installed programmatically via the first enable input 37 of block 7, if the second trigger 50 is pre-installed. The logical unit coming to the first output 15 of block 7 indicates that the monitor can access the memory cell, address which masked by monitor resources. The flip-flop trigger 49 is automatically performed if the working byte of the monitor reads the last byte of the return address by moving to the desired address of the monitor's ROM. The reset of the first trigger 49 also occurs during the initialization of the computer (but not the system being debugged).

The second trigger 50 is set, if the work fragment of the monitor has finished its work, which will be detected by the operation of the first decoder 43 of the transition, if it arrives. logical unit of the second

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1453408.

generated a working snippet and denying monitor resources. For this purpose, a logical unit is programmatically supplied to the first permitting input 37 of block 7. The second trigger 50 is also reset if the second decryptor of the 44 transition detects a reading from the working memory of the monitor of the last 6afi transition address to the user program.

The third trigger 51 is set if the second decoder of the 44 transition detects a reading from the working memory of the monitor of the last byte of the transition address to the user program. The third trigger 51 is reset, if block 13 detects no longer debugging conditions for the program, for which block 13 supplies a logical unit to the second enable input 38 of block 7.

The key 52, if a log unit is set at the input of the block 13, connects the state of the information output of the coincidence circuit 53 to the drives on the computer data bus 39. This allows you to find out the reason for the coincidence of the codes (matched the low byte, matched about the byte) using only one restart code generated by block 22.

The code matching circuit 53 isolates a pair; l: bitwise bitwise byte-by-byte comparison, for example, by modulating modulo 2 convolutionally. The output of the code matching circuit 53 receives a logical unit if its information inputs have a bit match in one byte. (operand - stop) or in two bytes (address - stop). The match condition (one or two bytes) is programmed in register 8 and is the condition for terminating debugging.

The element 55 excludes the operation of the comparator at the time when the address is unstable, when the current address is not the address of the first byte of the command code and when the user ska program does not work. The exception srabatshani comparator when not 25

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the decisive input 38 of block 7, which is achieved pre-cleverly to the recoverable address when attempting to write to the specified storage zone and is detected by block 13, and if the computer is initialized. The single state of the second flip-flop 50 reflects that the resources of the monitor normally mask the RAM of the ESH, and the user program is not executed. Wto-; the swarm trigger 50 is reset if

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a work fragment was generated and the monitor resources were banned. For this, a logic unit is programmatically supplied to the first permitting input 37 of block 7. The second trigger 50 is also reset if the second transition decoder 44 detects reading from the working memory of the monitor of the last 6afiTa transition address to the user program.

The third trigger 51 is set if the second transition decoder 44 detects reading from the working memory of the monitor of the last byte of the transition address to the user program. The third trigger 51 is reset if block 13 detects interrupted debugging conditions, for which block 13 supplies a logical unit to the second enable input 38 of block 7.

The key 52, if the log unit is set at the read input of the block 13, connects the status of the information output of the code match circuit 53 to the computer data bus 39. This allows one to find out the reason for the coincidence of the codes (the low byte coincided, both bytes coincided) using only one restart code generated by block 22.

The code matching circuit 53 isolates a pair; l: bitwise bitwise byte-by-byte comparison, for example, by modulating modulo 2 convolutionally. The output of the code matching circuit 53 receives a logical unit if its information inputs have a bit match in one byte. (operand - stop) or in two bytes (address - stop). The match condition (one or two bytes) is programmed in register 8 and is the condition for terminating debugging.

The element 55 excludes the operation of the comparator at the time when the address is unstable, when the current address is not the address of the first byte of the command code, and when the user program does not work. The exception srabatshani comparator when not 25

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whose input element AND 55 is the sign of the memory sample formed by the disjunction of signals on the reading lines 6 and writing 14 memory. The exception is interrupted by debugging, when the current address is not the address of the first byte of the command code, it is necessary to exclude the supply of the restart code when 145340810

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A user needs a resolution input of the memory block 18. it

it is necessary to exclude randomly and for the address of the air-blast, but the CGP - “–––––––––––––––––––––––––––––––––––––––––––––––––––––– zoGsG :: ™. , „: G„ l: ™; - - it turns out the high byte of the Hyipi GTAT

Cessor computer. The latter is not owned by the loan. In register 57.1 storage upper - (./, R,

boundaries of the occupied memory zone for,

the high byte of the address is written (or which is not masked by the resource: G.:. i ™ s,.

address generated by the microdigits changes the contents of the block

the computer processor, the latter does not belong to the memory so as to exclude such

reaped In the storage register 57.1, the top hit, then at the third input of the upper boundary of the occupied memory zone of the OR element 21, the monitor sets

The same information is written about the logical unit, which resolves

address, starting at which address, operation of memory block 18 without a fate

generated by a microprocessor computer, unit 7; belong to the last. 65 - change of borders;

The codes of adders 58.1, 59.1, 58.266 - the implementation of the directive, not

and 39.2 are exits of a transparative exchange containing, or containing

and have one bit. On the output of a sum.a-exchange with an unmasked address;

torus b8.1 receives a logical one-67 - a button is pressed to the computer if the bus 5 .Address is set-reset, this activates the lilane memory address, the value of which is equal to 1 initialization of the device trigna or exceeds the lower limit of the trigger 49 and 51 is reset, and the trigger

ema Similarly, the output of the adder 50 is set to one;

59.1 a logical unit arrives, .68 - the monitor is initialized, and the computer is installed on the 5 address bus and clears registers 8 and 20

res memory, the value of which is equal to or device and proceeds to waiting

less than the upper limit of the loan. To direct. In this state, the IPGs of the corresponding 15 and 16 block 7 are zero,

Registers are programmed using the third input of the OR 21, setting the boundaries in the additional codes. A logical zero is found, the investigator Since the outputs of a pair of adders are connected, the operation of memory block 18 is prohibited by the permissive input.

ment And 61.1, the necessary conditionWorking block 13 is prohibited by zero

Lo ™ G ™ - element And 61.1 Vysode 16 of block 7. Memories of memory from such a unit is a populated system impossible;

the current address of the memory cell is inter-69 — the monitor dispatcher controls the programmed boundaries of the console and waits for full input of the equality of one of the boundaries. rektivy. Until the last one is entered,

Element Ш1И 60.1 excludes the case-transition to the .block 70 is impossible;

tea generation of zone borrowing condition 70 — checks whether the input is stored if the ad-directive directive installed on the bus transfers control to the memory unstable or on bus 5 in the user program; The address is UVV. Therefore, at 55 71 - the directive does not transfer the output of the element And 61.1 through the user’s program to the user's program, get the address space borrowed. Zaverts whether the entered diu of the system being debugged contains an exchange, for example, with the cell or UVB72; , the contents of the cell or port must be replaced, it is checked that the address is not masked by the resources of the monitor;

73- the address to which the exchange will be, masked by the monitor resources, therefore, it is necessary to generate a working fragment (RF), check if the portion of the RAM from the RF will be in the loan during the RF execution;

7D - the area where the RF will be generated is in a loan from a debugger. Beforehand, the program counter, which can be any, is loaded into the pseudo register of the program counter in the working RAM of the monitor. Address

living system, it is necessary to exclude this loan, since it is not known that in this section the system being debugged has (and does it even have) good RAM. The memory block 18 is reprogrammed so as to exclude a loan for the RF segment; for this, the upper or lower limit in the memory block 18 is shifted accordingly;

75 is generated by the RF and is transferred to it;

76- performed by the RF. The execution of the RF begins with the filing of a logical unit on line 37 of the device by appropriate programming — a second register 20. A flip-flop 51 is set, and a flip-flop 50 is reset. There is a state of EXCHANGE. The operation of block 13 is prohibited, and the operation of memory block 18 is permitted. When exchanging with a memory cell, enter its address in the loan, memory block 18 is activated. Since the item is banned 23

does not block line 36, then 40 debug interrupts occur, since the exchange is at the address that relates to the element BAN 23. 23. At the same time, the system being debugged. At the same time, instead of the next first byte, at the address relating to the computer, none of the user program commands changes, since it blocks the data bus 39, the block 22 is placed through the element 33 and the restart code is restarted, and at the end of the cycle is an intermediary memory. If the address is not located on line 38, the trigger 50 sets a switch, then on the contrary, the processor of the computer is absent, and the trigger 51 is reset. The process of access not to the memory of the system being debugged, but to the computer's memory. The execution of RF j ends with the reading of the return address to a certain monitor address. The latter is fixed and does not depend on the directive containing the exchange. When reading the last byte of the return address, the decoder 43 of block 7 is triggered, which triggers trigger 49 and sets trigger 50, i.e. the MONITOR status is returned by the time the command code is read from the monitor's ROM;

77- checks whether the memory block 18 has been reprogrammed. If so, the original content is restored and control is transferred to the monitor dispatcher 69;

78- the directive contains the transfer of control to the user program, it is checked whether the conditions of the debug interrupt have been specified in the directive;

79- debug interrupt, conditions are loaded into device register 8;

80 start user prog ramme.

Previously, the program counter in the working RAM of the monitor is loaded into the pseudo register with the start address of the user program, which can be any number. Address

pseudo-register and program counter is constant. When the last byte of this pseudo-register is read, the decoder 44 is fired, the trip er 50 is reset, and the trigger 51 is set. By the time the processor accesses the start address, the RUNNING state is set, a logical unit arrives on line 16, and a logical zero is stored on line 15. This allows piiDoTy of block 13 and block 18 of memory.

In those cycles where the current address does not belong to the computer, but to the system being debugged, the contacts of the emulator connector will be connected to the corresponding computer buses during unauthorized operation of the memory block 18. Such a connection will not occur if block 13 in the current cycle detects the conditions

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Litter will read this restart code and transfer control to the monitor according to it. The implementation of program 81 will cease;

82 - debug terminator handler to which the monitor goes to the restart code. When performing a restart from the microprocessor of the computer, the contents of the restart of the program counter are retrieved and placed in the said pseudo register of the program counter. Next, all registries are retrieved.

general purpose. Debug debug processing is completed: by going to the monitor dispatcher. If the trace tag was set, the chain 69 .., 72 is repeated, the trace with the state of the microprocessor registers is displayed on the console, and the emulator control device supports this process.

Thus, block 76 is in the EXCHANGE state, block 81 is executed in the OPERATION state, the remaining blocks are executed in the URINE state TOR.

The device works as follows; at once.

In order for the current work of the computer to become the cycle of the operation of the system, it is necessary that the cres, the replaced computer, resu; The computers of the computer would have been banned, and on the course of 36 the device would go lo; A physical unit that permits the connection of computer busses to the microprocessor connector; a debug system is litter: At the same time, from the user's point of view, the system — emul - sor can be in the three mentioned states: MONITOR , EXCHANGE OF RA-BOTA.

In the MONITOR state, the processor operates with a PZZ or a monitoring monitor and is accessible to it. nonmaskable rauru-cpi-M mogun ora or otl.zhklzuemoy si-em em user resources MBA ,. The last 11 are AMA RAM. Perakryvayugdee all pr my address: n:, ostranstvo ,. and the number of UVB addresses of thornpoints may vary 5, for example, K-1 switch. In the state. MONITOR mg monitor resources will erase the RAM of the UVM with the help of the system: the computer line is banned from RAM, and the user UVB (but not the UVV of the monitor) prohibits the passiveness of the system line of the ZHLET UVV, User UVV, thus, the address can be shared with the UVB address of the UVV and the UVV, user UVB, thus, can be shared with the addresses of the UVB and UVV In the particular case, user air-blast may be absent, but then, when a system is being debugged, it is necessary to have them. In the MONITOR state, the computer performs service functions, for example, it reads a disk sector in the working memory. the monitor, knocks the console keyboard, displays the snc vol on the display, waits for instructions, and so on. In the MONITOR state, the computer can also exchange at its address

resources that are not masked by monitor resources or are debugged.: system.

g In the EXCHANGE state, a computer accesses an address that is not available in the MONITOR state, for example, this address is masked by the resource 1 1 and the monitor. Access is provided as follows. If the address to which access is necessary is masked by the resources of the monitor, which the monitor determines itself, then in some, computer RAM area, the monitor generates

15 own working fragment. Previously, the initial content zone of the working fragment is copied by the monitor to its working storage device. If the area of the working fragment is occupied by the memory of the system being debugged, the contents of memory block 18 in the monitor are changed in such a way as to exclude a loan from the computer, Dapee control is transmitted to the working fragment, which contains the necessary commands to issue a logical unit 1 to the first input 37 of block 7, since in the MONITOR state the trigger 50 was set,

that

0 logical unit, pass through

element 42, will install the first trigger 49 and reset the second trigger 50 “By executing the necessary exchange, the processor reads from the working fragment ad-. Returns to the monitor ROM, which restores the state of the MONITOR,

In the status EXCHANGE perl trigger: 49 is set, the output 15 of block 7 enters the logging unit, which, through the NOT 25 element, inhibits the monitor's resources by the activity of the monitor-inhibiting line 34. At the same time. the same logical unit resolves, through the element ELI 21 5, the issuance of the decision by block 18,

belongs to no address, which is accessed in the state of EXCHANGE, debugged by the us; those; esl, Esn nrnnad / 1zhit, then through the prohibit 23, the block 18 to the output 36 of the device allows logical access to the socket of the processor of the processor or the remote control system If it does not belong to it, then during the entire operation of the fragment, a logical unit will not arrive at 36 devices, since memory unit 18 is working; the fragment is excluded from the memory zone occupied by the system being debugged.

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In the RUNNING state, the user program is executed. In the OPERATION state, the computer system - the emulator goes from the MONITOR state, when the input element I 41 has a logical unit coming from the output of the second trigger 50. When the processor reads from the working memory of the monitor, the byte of the transition address of the computer prohibits the RAM of the computer but now not through

20

25

In the user's frame, the second transition decoder 44 is triggered, the trigger 50 is reset by a cut-off pulse from its output, and the trigger 51 is set. From this point on, the OPERATION state is active, and all three AND 40-42 elements are prohibited by logical zeros at the second inputs. Therefore, the user program does not affect the state of the state block 7. Before entering the OPERATION state by the monitor, the memory block 18 is programmed according to the data of its working memory. Before entering the OPERATION state, i.e. in the MONITOR state, the operation of the memory block 18 is prohibited by permissive input. When entering the OPERATION state, so. as the third trigger 51 is set, the first output 16 of block 7 begins to receive a logical unit, which is maintained during the OPERATION state, the second through the OR 21 element enables the operation of memory block 18. Therefore, in those cycles when the addresses the user program works with belong to the system being debugged, a logical unit will occur at the output of the memory block 18 and, accordingly, the output of the BAN 23 and the device output 36. The latter periodically connects the system being debugged to the emulator with the simultaneous banning of computer RAM through the HE element 33 via the RAM ban line 35, and the monitor resources banned through the HE element 26 through the line 34. During the entire state of the UVB. The computer is prohibited along the line through the element NOT 30 from the second output 16 of block 7. Custom air-blast, if

the HE element 33, and through the HE element 3 the third trigger 51 is reset, the state of the logical unit at the second output 16 of the block 7 and the output 15 of the device 19 stops, the monitor resources are denied on the line 34 through the HE element 26, and held for of this cycle, the prohibition of monitor resuses through the NOT element 27, the shaper 22 generates a restart code. Obviously, the bus conflict does not occur. The start of the generation of the restart code is the end of the OPERATION state and the return to the - MONITOR state. The restart code is read by the processor and, in subsequent cycles of operation in the MONITOR state, the operator’s information on the status of the debugging process is retrieved from the microprocessor ECH.

These are the features of the states of the ES system — the device is an emulator. Consider the dynamics of device states.

thirty

35

45

50

The initialization of the device is performed by feeding a logical unit to the input 1 of the device initialization simultaneously with the initialization of the computer. When the initialization pulse is applied, the outputs 15 and 16 of the unit 7 assume the zero state, and is simultaneously cleared. the second register is 20; therefore, none of the inputs of the OR element 21 have a logical unit and, therefore, the operation of memory block 18, regardless of its contents, is prohibited. The operation of block 13 is also prohibited by zero on the second output 16 of block 7. Therefore, none of the lines 3, 34 and 35, respectively, prohibits the UVV computer, prohibits monitor resources, prohibits RAM, is not active from the device side, and output 36 va is also passive. Therefore, immediately after initialization, the system being debugged is disconnected from the computer buses and resources. the monitor is normally masked by computer RAM

there are, while allowed. In the absence of user air-blast, the air-blast system of the system being debugged is working, and the air-blast computer is also prohibited. The exit from the OPERATION state is possible when the computer is initialized, as well as when the block 13 detects an interrupt-debug condition, since the operation of block 13 in the OPERATION state is allowed by the fifth input from the second output 16 of block 7.

If block 13 in the current cycle detects a debugging failure, for example, a break point, then during this cycle, the element BANGE 23 prohibits the connection of the buses of the system being debugged to the computer, continues

ban on computer RAM, but now not through

the HE element 33, and through the HE element 32, the third trigger 51 is reset, the state of logical one is stopped at the second output 16 of block 7 and the second output 19 of the device, the prohibition of monitor resources on line 34 through the HE element 26 is stopped, held for this cycle, the prohibition of monitor resources through the element 27, the shaper 22 generates a restart code. Obviously, the bus conflict does not occur. The commencement of the generation of the restart code is the end of the OPERATION state and the return to the - MONITOR state. The restart code is read by the processor and in subsequent cycles of operation in the MONITOR state from the microprocessor ESh, the operator’s information on the state of the debugging process is retrieved programmatically.

These are the features of the states of the ES system — the device is an emulator. Consider the dynamics of device states.

0

five

0

five

The initialization of the device is performed by feeding a logical unit to the input 1 of the device initialization simultaneously with the initialization of the computer. When the initialization pulse is applied, the outputs 15 and 16 of the unit 7 assume the zero state, and is simultaneously cleared. the second register is 20; therefore, none of the inputs of the OR element 21 have a logical unit and, therefore, the operation of memory block 18, regardless of its contents, is prohibited. The operation of block 13 is also prohibited by zero on the second output 16 of block 7. Therefore, none of the lines 3, 34 and 35, respectively, prohibits the ACU of the computer, prohibits monitor resources, prohibits RAM, is not active on the device side, and device output 36 passive. Therefore, immediately after initialization, the system being debugged is disconnected from the computer buses and resources. , monitors normally mask computer RAM.

1 7

The device normally works even when the entire address space of the memory belongs not to the computer, but to the system being debugged. The memory zones belonging to the system being debugged are indicated by the operator by special monitor instructions and recorded in the working memory of the monitor.

Let the operator specify a monitor instruction containing access to an address that is not masked by monitor resources, but does not belong to a computer. Before actions to access such an address, the monitor programs memory block 18 so as to exclude the borrowing of memory zones from the system being debugged that match the addresses to the monitor resources. Immediately before the monitor accesses, a logical unit is programmatically installed at the third output of the second register 20, which, through the RShI 21 element, allows operation of the memory block 18. In the loop access 1453408

and the logical unit from the output 36 of the device, as in the previous case, connects the connector of the emulated .g microprocessor to the computer buses.

f

Thus, the monitor has access to any cell of the memory of both the ES and the system being debugged. Consequently, using the proposed device, the entire address space of the memory of the emulated microprocessor can be investigated.

15 Let the operator set a monitor instruction containing access to the UVE of the system being debugged. In this case, the monitor also frees up space for your work piece in computer RAM,

20 generates a work fragment and transfers control to it. The work fragment in this case contains the necessary input-output commands, and not exchange with the memory. There is a status of OMDE

gt-, kg, -to1-.v-v-. or sawn state

PA memory unit 18 is triggered, on its 25 to output 15, unit 7 starts the post RfilV P TT TT T Tm -ij mTT.-i -....

the output enters a logical unit, which through the BANNER element 23 enters the device output 36, which connects the connector of the emulated microprocessor to the buses while simultaneously blocking access to the computer's RAM through the HE element 33. At the end of the access cycle, the third output of the register 20: is programmed to zero, which Prohibits the operation of memory block 18. During the described actions, block 7 remained in the MONITOR state.

Suppose now that the operator has set the monitor instructions, containing access to the address, the masked resource of the monitor and not the receipt of the computer. • Before generating the working fragment by the monitor, the memory block 18 is programmed so as to exclude the borrowing of the working fragment zone. In contrast to the previous case, the third output of the second register 20 is not programmed to one. After transferring control to the working fragment, as it is described, the EXCHANGE state, a logical unit enters the first output 15 of block 7 and through the first element OR 21 enables the operation of the memory block 18 during the access cycle to the specified address. At the same time, the resources of the monitor are previously prohibited through the element NOT 25 through line 34, the computer RAM is prohibited through the element NOT 33 through line 35,

This is a logical unit that solves the operation of the memory block 18 and, through the element NOT 30, will prohibit the UEV of the computer, regardless of the address of the exchange, and will resolve the user UHV, if any. If there is no user UVB, then memory block 18 is pre-programmed so that any cycle containing I / O causes the memory block 18 to wake up, which connects the emulated microprocessor to the ESH connector. If there is a user UVV in a computer, then memory block 18 is programmed so as to exclude 40 operation of memory block 18 at the address to which the UVV computer is selected. and 45 custom air-blast, if they are installed in the ES.

The user program may contain any restart codes, including the code that matches the code, gQ generated by shaper 22. Indeed, if this restart code is encountered in the program, then in block 13 this address is not specified as the debugging address, The gg 13 block does not work and the state of the UNITOR is not restored. Consequently, under this restart code, the actions determined by the user program, but not the monitor, will be executed.

1453408

and the logical unit from the output 36 of the device, as in the previous case, connects the connector of the emulated microprocessor to the computer buses.

f

Thus, the monitor has access to any cell of the memory of both the ES and the system being debugged. Therefore, using the proposed device, the entire address space of the memory of the emulated microprocessor can be investigated.

Let the operator set a monitor instruction containing access to the UVE of the system being debugged. In this case, the monitor also frees up space for your work piece in computer RAM,

generates a work fragment and passes control to it. The work fragment in this case contains the necessary input-output commands, and not the charger from the charger. There is a state of EXCHANGE,

-.V- V-. or sawn state

on exit 15, block 7 begins fasting

This is a logical unit that will allow operation of the memory block 18 and, through the element NOT 30, will prohibit the UEV of the computer, regardless of the address of the exchange, and will decide the user's UVB, if any. If there is no user UVB, then memory block 18 is pre-programmed so that any cycle containing I / O causes a memory block 18 to trigger, which connects the emulated microprocessor to the ESH connector. If the user has an ACU in the computer, then the memory block 18 is programmed so as to exclude 0 the operation of the memory block 18 at the address to which the computer UVB is selected. Thus, irrespective of the air-blast address, the monitor examines both any air-blast system of the system being debugged and 5 user air-blast systems, if they are installed in the ES.

The user program may contain any restart codes, including the code that matches the code Q generated by the shaper 22. Indeed, if the program finds this restart code, then in block 13 this address is not specified as the debugging address, g 13 does not work and the UNITOR state is not restored. Consequently, under this restart code, the actions determined by the user program, but not the monitor, will be executed.

Claims (2)

1. A device for debugging a microprocessor system comprising a multiplexer, a call decoder, a restart code shaper, a register memory block, first and second registers, first and second groups of NOT elements, and a code comparison unit, the first and second information inputs of the multiplexer are device inputs for connection to the bus, respectively, of the address and data of the microprocessor system being debugged, the information input of the access descrambler is connected to the input of the device for connection to the address bus of the control computer system, the first and second control inputs of the address decoder are connected to the device inputs for connecting to the write and read lines and the I / O of the control computer system respectively, the information input of the first register is connected to the device input-output for connecting to a bi-directional data bus control computer system, the input of the first register entry is connected to the first output of the address decoder, the output of the restart code generator is connected to the input-output of the device for li ne bidirectional data bus to control the computer system, first information input code comparing unit connected to the output of the first register, a second informatsion10 15 20 25 thirty 35 The address decoder house, information and address inputs of the raster memory block are connected to the input of the device for connecting respectively to the bidirectional data bus and to the address control bus of the numbering system, from the first n fourth permitting inputs of the register memory block are connected to devices for connecting to, respectively, readings of the memory of the memory of the memory, reading of the input-output and write-in of the input-output of the control computing system, fourth output,. A call decoder is connected to the second recording input. Record whose reset input is connected to the device initialization interface, the information input of the second register is connected to the input-output device of the connection to the bi-directional data bus of the control computing theme, the output of the first field of the second horn is connected to the control input the multiplexer, the outputs of the elements of the first group are combined according to the installation OR scheme and form the output of the device for connecting to the first ban of the controlling control system, the outputs of the elements are not diggable The sensors are combined according to the OR circuit and form the output of the device for connecting a control computer system to the second line, characterized in that, in order to simplify the device, it contains a state determination unit, an OR element, an element behind input of the block of comparison of connection codes, the third group of elements NOT, With the multiplexer output, the information output of the code comparison unit is connected to the input-output of the device for connection to a bi-directional control data bus to the computer system, the enable input. reading the code comparison block is connected to the second output of the decoder, the comparison block output of the code comparison block is connected to the input of the restart code generator, the first, second and third gating inputs of the code comparison block are connected to the inputs of the device for connecting to lines of reading memory cards record, the memory and the sign of the first cycle of the command of the controlling computing system, the recording input of the register memory block is connected to the third output 50 55 moreover, the initialization input of the state conditioner is connected to the input of the device initialization, the gate input of the state determination unit is connected to the input of the device for connecting to the reading line of the control computing system, the first and the second permitting inputs of the state detection unit are connected correspondingly with the output of the second field of the second register and the output of the code comparison block, the information input of the state definition block is connected to the input of the device for connection to the control bus of the computational numeral threads or output elements coupled to the fifth register in permissive memory block house, the first determining unit output conditions ten 15 0 five 0 five the address decoder house, information and address inputs of the register memory block are connected to the device inputs for connecting respectively to the bidirectional data bus and the address computing bus of the control computing system, first to fourth permitting inputs of the register memory block are connected to the device inputs for connecting to the line m, respectively, of reading the memory, writing the memory, reading the I / O and writing the I / o of the control computing system, the fourth output,. the call decoder is connected to the second register entry input, the reset input of which is connected to the device initialization input, the second register information input is connected to the device input-output for connection to the bi-directional data bus of the control computing system, the output of the first field of the second register is connected to the control input of the multiplexer , the outputs of the elements of the first group are not combined according to the installation OR scheme and form the output of the device for connection to the first line of the control inhibitor The system, the outputs of the NOT elements of the second group are combined according to the mounting OR scheme and form the output of the device for connecting the control computer system to the second line, characterized in that, in order to simplify the device, it contains the state definition unit, the OR element, the element Reta, the third group of elements is NOT, Reta, the third group of elements is NOT, wherein the initialization input of the state definition unit is connected to the device initialization input, the gating input of the state determination unit is connected to the input of the device for connecting to the reading line of the memory of the controlling computing system, the first and second permitting inputs of the state determining unit are connected to the output second floor the second register and the comparison block output of the code comparison block, the information input of the state definition block is connected to the device input for connecting to the bus address of the control computing system, the output of the OR element is connected to the fifth enabling input of the register memory block, the first output of the state block definition co one with the input of the first element NOT of the first group and the first input of the OR element, the second input of which, the input of the second element of the first group, the input of the first element of the third group and the enabling input of the code comparison unit are connected to the second input of the state definition unit connected to the output of the third field of the second register; the output of the comparison of the code comparison unit is connected to the input of the third element NOT of the first group, the input of the first element NOT of the second group, and the inverse input of the prohibition element whose direct input th is connected to the output of the register memory of the second element input is not connected to the third group the first input of the third element AND is the first permitting input g of the block for determining the states, the second input of the first element I is connected to the output of the first trigger, the second to the bottom of the second and third elements I are united with the output of the second trigger 10 outputs of the first and second elements I are connected to the enabling inputs of the first and second d transition encoders, respectively, the information inputs of which are combined and connected 15 with the information input of the state detection unit, the initialization input of which is connected to the first inputs of the first and second OR elements, the second input of the second element AND „,. . element j  . T °. .- 20 is the SECOND permission entry Then, the codes of the NOT elements of the third group are combined according to the installation OR scheme and connected to the third control input of the access decoder and form the output of the device for connecting the control computer system to the third inhibit line, the output of the inhibit element is connected to the input of the second element NOT of the second group the state determining unit, the output of the third AND element is connected to the S input of the first trigger and the first input of the third OR element, the output of the 25th is connected to the R input of the second trigger, the second input of the third OR element is connected to the output of the second transition decoder and S-input of the third of the trigger, outputs of the first and W „„. - - l ttcif 1shli, qi | lieuburo and in Lr. .fl ° l °: devices that connect the OR elements connected to the second output of the device is the second output of the state detection unit. 2. The device according to claim 1, characterized in that the block for determining the state contains a transition decoder, three AND elements, four OR elements and three flip-flops, the first inputs of the first and second AND elements being gated with the R inputs of the first and tr the second one of the flip-flops whose outputs are the first and second outputs of the definition block 2g, the first input of the fourth element OR is connected to the output of the second element OR, the output of the first decoder of the junction is connected to the second inputs of the first element OR and the fourth The 40th OR element whose output is connected to the S input of the second trigger. 7 input of the state definition block, the first input of the third element AND is the first enable input the state determination unit, the second input of the first element I is connected to the output of the first trigger, the second inputs of the second and third elements I are connected to the output of the second trigger, the outputs of the first and second elements And are connected to the enabling inputs of the first and second decoder transitions, respectively, the information inputs of which are combined and connected with the information input of the state definition block, whose initialization input is connected to the first inputs of the first and second OR elements, the second input of the second OR element  . element j is the SECOND permission entry is the SECOND permission entry the state determination unit, the output of the third AND element is connected to the S input of the first trigger and to the first input of the third OR element, the output of which is connected to the R input of the second trigger, the second input of the third OR element is connected to the output of the second transition decoder and S-input of the third trigger, outputs of the first and second - ttcif 1sli, qi | lieuburo and in GOI OR elements are connected by EYE OR elements, respectively, connected to the R inputs of the first and third triggers, the outputs of which are the first and second outputs of the state definition block, respectively, the first input of the fourth OR element, and the output of the first transition decoder with the second inputs of the first OR element and the fourth OR element, the output of which is connected to the S input of the second trigger. "Te / / h J9 2nd entrance Read entry 52 / h / info log in ( 53 five -L S5 38 62 Howl Lucnet sjt 66 (Pu2.S