SU1434497A1 - Device for regenerating dynamic storage - Google Patents

Abstract

The invention relates to computing and can be used to regenerate a dynamic memory of a computer. The aim of the invention is to increase the speed of the memory. The device contains 1, 2 clock pulse generators, triggers 3, 4, bus drivers 5, 6, local control unit 7, counters 8, - 8, decoder 9, encoder 10, register 11, AND 12 element, OR 13 element. In the device the current counter codes determine the permissible storage time for each line of the RAM 15. When the processor 14 accesses the RAM 15 during operation, the counter 8 corresponding to the address code g of the selected row is reset, which eliminates unnecessary regeneration cycles. 3 il. (L

Description

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The invention relates to computing and can be used to regenerate a dynamic memory of a computer.

The purpose of the invention is memory boost-speed.

FIG. -1 shows the functional diagram of the device; in fig. 2 is a functional diagram of a local control unit; in FIG. 3 is a temporary diagram of the operation of the device in the information regeneration mode.

The device contains the first 1 and second 2 clock pulse generators, the first 3 and second 4 triggers, the second 5 and first 6 bus drivers, local control unit 7, counters 8, decoder 9, encoder 10, register 11, element AND 12, element OR 13 FIG. Figure 1 also shows the elements of a computer interacting with the device: the central processor 14 and the operational memory 15. In addition, the JStroy contains the output 16 of the demand for direct | n, access to the memory (PDP) of the processor 14, the input 17 of the ODP, output 18 channel lock (PZ) confirmation, address outputs 19, memory control input-outputs 20, output group 21 and input group 22 of local control unit 7, operation mode input 23 of block 7 local control channel, output 24 of synchronization signal, output

25 output resolution recording signal

26 gating signal, reset signal output 27, synchronous input 28 of local control unit 7.

The local control unit 7 contains the elements OR - NOT 29-33, the element NOT 34, the one-shot 35, the elements AND 36-39, the triggers 40-44, the elements AND-HE 45-47, the element 48, the one-shot 49 and the resistor.

The device works in the following way.

In the initial state, triggers 3 and 4, as well as triggers 40-42, 44 are reset, trigger 43 is cocked. In the higher bits of the counters, codes 11 ... 11, 11.10, ... 00..00 are written, respectively (zeroing and initial setting circuits are not shown). The pulses from the output of the generator 2 through the element And go to the counting inputs of the counters 8.

In the regeneration mode, the signal from the inverse output of the trigger 4 permits the passage of pulses from the output of the generator 2 through the element 12 to the account0

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The counter inputs 8. When one of the counters 8 overflows, the signal from the output of its last bit through the OR element 13 enters the trigger setup input 3. At the same time, the output of the encoder 10 sets the counter code 8 (from O to n) corresponding to the address code of the line memory cells for which the storage time of the information has expired and regeneration is required.

On the leading edge of the pulse of the first generator 1, a trigger 3 is set, and a direct access demand signal is generated at its forward output 16. The central processor 14 pauses the execution of operations, frees the address 1W1 to 19 and enters a response signal to the input 17 of the DSP, which sets the trigger 4, which in turn resets the trigger 3, generates a signal at the output 18 of the PZ, and also opens the bus drivers 5 and 6.

The signal from the inverted output of trigger 4 prohibits the passage of generator 2 pulses through the element OR 12 to the inputs of counters 8. The signal from the direct output of trigger 4 goes to local control unit 7 and enables the installation of trigger 40, which is charged after the current memory access cycle is completed typing and clearing the synchronization signals of the active device (SIL), synchronization of the passive device (sip), arriving at inputs 22, with a positive clock pulse (TI) from generator 1. Regeneration signal (WGN) from the direct output The trigger signal 40 enters through the shaper shaper 6 into the RAM 15 and remains active during the entire regeneration time.

The following clock pulses successively trigger trigger 42, trigger 43 is reset, and trigger 44 is energized. The signals from the inverse output of trigger 43 and the direct output of trigger 44, collected on the OR element 48, form the SIL signal, and the collected signal on the And 38 element form the INPUT signal, Signals The SIL and ENTER enter the RAM 15 via the bus driver 6 together with the code of the row address from the bus driver 5 output. At the same time, the row address CBD is fed to the (11) orhimonny inputs of the register 11.

The recording in register 11 occurs on the leading edge of the signal at the output 24 of the input from block 7. In response, the input memory 15 signal generates a CIP signal that arrives at the information input of the trigger 41, which is set to one in the next TI, allowing the trigger to be set 43 following TI. In this case, the ENTER signal is removed, in response to which the RAM 15 removes the CIP signal.

The trigger 41 is reset by the next TI, and the next dim TI, the trigger 44 is reset and the CHA signal is removed. The one-noisy 35 selects the falling edge and generates a single pulse at the output 26 of the unit 7, which is fed to the control input of the decoder 9, thereby wrapping the counter 8 corresponding to the code stored in the register 11. The single-vibration 49 selects the leading edge and forms impulse of negative polarity, zero trigger 40 and through element 34 and trigger 4, RGN and PZ signals are removed, the regeneration cycle is over.

In this way, the regeneration can be carried out for any line of the operating memory 15. If, during the operation of the device, none of the counters 8 is overflowed, i.e. while the storage of information for one line of RAM is not successful, the operation of the device is as follows.

; In the mode of accessing the RAM 15, the processor 14 sets the address code of the memory cell on the address bus, and on the control pin produces control signals received in the control unit 7 from the inputs 22: channel signal of the passive device (CSIP), channel, signal selection of an external device (HLC). Fallen bits of the address code, which are the address code of the line, by the signal from the output 24 of block 7 with

the presence of an enable signal at its output 25 is recorded from register 11. A signal that prevents writing to register 11 at output 25 of block 7 when the processor-1A is accessed, not to the RAM 15, but to external device registers. At the same time, no signal is generated at the output 26 of the control unit 7.

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Since when accessing the RAM 15, all the memory cells with the specified line address are regenerated, then at the end of the cycle of accessing the RAM 15 by a signal from the output 26 of the block 7 by a signal from the output of the decoder 9, the counter 8 is reset to zero which is the same as the address code of the string. Stored in register 11. A request for the regeneration of RAM cells 15 with a given row address can now come from the output of this counter 8 only after Tp, provided that during this time processor 14 will no longer access cells with this row address.

Thus, the current counter codes determine the permissible storage time of information for each line of RAM 15. When the processor 14 accesses the RAM 15 and the operation process, the counter 8 corresponding to the address code of the selected line is reset, which eliminates unnecessary regeneration cycles.

Claims (1)

Invention Formula A device for regenerating dynamic memory containing the first and second clock generators, the first and second triggers, the first and second bus drivers, an OR element, the output of the first clock generator being connected to the synchronous input of the first trigger, the output of which is device memory access, the direct output of the second trigger is an output Confirming the acquisition of the channel of the device and connected to the reset input of the first trigger and the control inputs of the first and second bus | f The actuators, whose outputs are respectively the memory management outputs and device address outputs j, the second trigger setup input is the device providing direct memory access to the device, characterized in that, in order to improve the memory speed, it contains a group counters, register, decoder, encoder, local control unit and the element And, the output of which is connected to the counted inputs of group counters, I / O inputs are connected to the corresponding output of the decoder, information; the ion inputs are connected to the outputs of the register, information inputs are connected to the outputs of the second bus driver, the information inputs of which are connected to the outputs of the encoder, the inputs of which are connected to the outputs of the ruppe counters and the inputs of the OR element, the output of which is connected to the information input of the first trigger, the output of the second clock generator is connected to the first input of the element I, the second input of which is connected to the inverse output of the second trigger, the outputs of the reset, write down, synchronize, and strobing signals of the local control unit are connected to the reset input of the second trigger, the enable input, the sync input of the register, and the control input of the decoder, the sync input of the local control is connected to the output of the first clock generator, the outputs of the group of memory control signals of the local control unit are connected to the inputs of the first bus driver, the inputs of the group of control signals of the memory of the local control unit are the corresponding inputs of the device, the input of the operation mode of the local control unit is connected to the forward output of the second trigger. inJlJLJlJlJULJlJbTJVl-rL 2f 9u.t. 3