SU1429303A1 - Shaper of stepped pulses - Google Patents

Abstract

The invention relates to pulsed tekinka and can be used in radar for the formation of control voltages. The purpose of the invention is to increase the speed of the device while expanding its functionality. Device sodart generator 1 clock pulses, blocks 2.1. 2.2. keys, matrices 3.1. 3.2, operational amplifier 4. Key blocks 2.3 ... 2.K, resistive matrices 3.3 ... 3.K, register 5 numbers and blocks 7.1 ... 7.K are entered into the device. memory Register 5 records information in binary code. At the output of each resistive matrix Z.1 .. Z.K, a step-varying signal is formed if a unit is recorded in the corresponding register bit 5 of the register 5. The sign bits of register 5 determine the sign of the change in the output voltage. The speed is due to the fact that in the memory blocks 7.1 ... 7.K there are no transients. 1-z.p. f-ly, 3 ill. X., Schtrgtr (L with 4 to from 00 about SAE

Description

The invention relates to a pulse technique and can be used in radiolocation to form control voltages.

The aim of the invention is to increase the speed of the device while expanding its functionality.

Fig. I shows a structural (device diagram; Fig. 2, a block diagram of the memory block; Fig. 3 shows timing diagrams.

The generator contains a generator of 1 clock pulses, from the first to the Kth blocks 2.1 ... 2.K keys, from the first to the Cth resistive matrices 3.1 ... 3.K, operation amplifier 4, register 5 Cycles t bus b of the reference voltage, t of the first through the K th block 7.1 ... 7. To the frame, bus 8 of installation O and exit to Yuy bus 9.

I Bcek reset inputs of blocks 7.1 ... 7.K. They are connected to bus 8, the main inputs are with generator 1 output, the sign inputs are with sign outputs of register 5. The control input of the power block, 1 is connected to the corresponding register output 5, and the output is through the block 2.1 and the resistive matrix 3.1 - G by the corresponding input of the operational amplifier, the output of which is connected to the output bus 9. The inputs of the reference voltage of all the blocks 2.1., 2.K are connected to the bus 6.

Each block 7 (FIG. 2) contains from the First to the Nth elements 10.1 ... 10.N of the memory, from the first to the summing elements AND A.1 ... 11.N, from the first to the N-th subtractive elements And 12.1..12.N, From the first to the Nth elements OR 13.1 ..) 3.N, trigger 14, from the first to the ninth elements And 15-23 and (5 + 1) -th element of ШШ 24.

Direct codes of elements 10.1..IO.N Form bits of the output of block 7 and soybeans except element 10.N, with the first inputs of summing elements of the next digit. Invert the outputs of elements 10.1 ... 1O.N are connected to the summing elements AND 11.1 .. 11 .N toro of the same discharge with their own single input and, except for element 10.1, through the reading element And 12.1 ... 12. N-1 with zero input of the previous element 10.1 ... 10.N-1. The second inputs of elements ШШ 13.1 ... 13.N are combined and form the reset input of block 7. The first output is 10.1 and the inverse output

ten

15

20

25

thirty

.C

five

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0

five

N-ro 10.N elements are connected to the first and second inputs of the first element And 15. The inverse output of the first 10.1 and direct output of the K-th 30.N elements are connected to the first and second inputs of the second element And 16. The outputs of the first 15 and the second 16 elements And are connected to the first inputs of the third 17 and fourth 18 elements And, the second inputs of which are sign inputs of block 7, and the outputs are connected to the single and zero inputs of the trigger 14, the direct and inverse outputs of which are connected to the first inputs 19 and sixth 20 elements And, the second inputs to which are combined and connected to the synchronization inputs of all the elements 10.I .., 10.N memory and the output of the seventh element And 21, the first and second inputs of which are respectively the clock and control inputs of the block 7. The first inputs of the eighth 22 and nine 23 elements And are connected respectively to the direct and inverse outputs of the Nro element, 10.N, the second inputs are combined and connected to the inverse output of the trigger 14, and the outputs are connected to the inputs (N + l) -ro of the element OR 24, the output of which is connected to the first input of the N-ro subtractive element I 12. The output of the nth element TA and 19 is connected to a second input of the first summing element and 11.1 and the third inputs of summing elements rest AND 11.2 ... 11.N. The output of the sixth element And 20 is connected to the second inputs of the reading elements And 12.1 ... 12.N.

Each of K resistive matrices, 3.1 ... 3.K is a set of N resistors. The value of the resistors of the first matrix 3.1, for example, corresponds to R, the value of the resistors of the second matrix is 2R, and so on, or the value of the resistors of the first Matrix 3.1 corresponds to R, and the ratings of the load resistors in other bits differ by a multiple of the base of the selected number system. The number of register bits 5 and the number of memory elements in blocks 7, as well as nominal values. resistors of the resistive matrix 3 are determined by the range of variation of the magnitude of the output signal and the required accuracy of the voltage representation

in analog form (step voltage).

The generator works as follows.

The generator provides operation in the following modes: control and generation. Before starting operation, all the triggers in blocks 7 and register 5 are zeroed. We consider processes using positive logic, when a logical unit corresponds to a higher level. In the initial state, register 5 records information in binary code. In control mode, the Addition or Subtraction command

It is formed according to the signs of the sign bits of register 5, which are transmitted to the second inputs of elements AND 17 and 18. When the Addition command is formed (this corresponds to the sign code of bits 10), a high logic level is applied to the second input element AND 17. All elements 10.1 ... 10.N are in the zero state, therefore a high level is applied to the inputs of the AND 15 element. The output signal of the element 15 (high logic level) affects the first input of the element 17, the output of which also forms a high logic level, which, acting on the single input of the trigger 14, sets the last one to one state, the enabling voltage is applied to the first input to element 19. If a unit is recorded in this iM de register 5 register, then a high level is applied to the second input of the first element 21. The first pulse of generator 1 (Fig. 3a) goes through elements 21 and 19 and the effect It is one of the inputs of AND gates 11.1 ..-. 11.N. This pulse passes only through the AND 11.1 element, the remaining, indicated AND elements are closed low from the direct output of the previous memory element. and sets the first element 10.1 to one. The synchronizing input of elements 10.1 ... 10.N at the same time receives the pulses of generator 1 from the output of element I 21. A high level from the direct output of element 10.1 affects the control input of the corresponding key of block 2, the second input of which is energized from the bus 6. At the same time on the corresponding

five

0

resistor matrix; 3.1 A voltage step is formed. The high level from the direct output of element 1 0. affects one if inputs of element AND 11.2, while the second pulse of generator 1 ensures that only the second element 10.2 switches to a single state, as a result a second step voltage step is formed (Fig. 36). The third pulse of the generator 1 sets the next memory element 10.3 in one state, the Nth pulse of the generator 1 - element 10.N in the state one. Thus, all elements of the math of the block 7.1 under consideration are in a single state. Similarly, the processes in the other blocks 7 occur under the condition that a high level is applied to the anchor block 7 from the register 5. The difference is - The reason is that the amplitude of the steps

5 is formed in the jth resistive matrix in accordance with the resistor values of the matrix (Fig. 3, h, and hj). If a low level is applied to the j-th block 7.J from register 5, then

0 This jth block 7.J does not participate in the operation of the device. The combined outputs of resistors of resistive matrices 3.1 ... 3.K are connected to the inputs of the opamp-amplifier 4, the output of which results in the resulting increasing voltage of the stepped form.

In the control mode, when forming the Subtraction command (this corresponds to the code of the sign bits 01), a high logic level is applied to the second input of the And 18 element. All elements 10.1..10., N are in the 1 state, the high logic level is applied to element 16, the output high level of which acts on the first input of element 18, the high level from whose output sets trigger 14 to the zero state, and the resolution voltage from its inverse output is applied to one of the inputs of elements 20 and 22 and 23. A high level from the direct output of the element 10.N acts through the elements AND 22 and OR 24 on one of the inputs of the element AND 12.N. The pulse of the generator 1 through the elements And 21 and 20 affects the elements And 12.1 ... 12.N and provide5

0

five

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5 14293036

It makes the switch through the elements. The form of the output voltage in AND 12.N and OR 13.N of only one single generation mode differs from the form of the ment 10.N c. zero state. The output voltage in the control mode - Another impulse of the generator of inter-ling by the absence of the upper pedestal - includes the next element 10.N-1. In FIG. 3 it is conditionally depicted only in the zero state and so: - to seven steps. Establishment of a multi- Next, after the N-ro pulse of the generation-binary code into register 5, par 1 switches to the zero state, element 10.1, for example, is output from the output device of the computer or by means of the panel | memory of the block 7.1 are in the zero set of parameters.

B Similarly, on command, You-Known devices perform

Quoting occurs in the process and in the conversion of code to analog. blocks 7.1..7.К in the presence of /, - and the binary code receive

The functions in the corresponding bit de igputem computations in the accumulative elements | ) registrar 5. As a result, the output of one-cops, for example, counters, sum | ) Amplifier amplifier 4 is formed by pax. One of the drawbacks is specified; x

The resulting decreasing voltage of the devices is that the fast one is of the 1-step form (Fig. 36). Duration is limited by transient time.

The iiocTb steps, in this case, are determined by the processes occurring during the calculation, which is followed by the pulse tracing period. In the proposed device in

(JJOB generator 1. Blocks 7 carries from lower bits. Consider the generation mode. In this case, there are no highs to higher ones, thanks to the significant bits in the register where the speed is higher. 5 code is written Peak second input 25

Claims (1)

; I give logical elements I17 and 8 The formula of the invention is applied high logical level. The reset pulse is all element-. The step pulse generator tbi 10.1 ... 10.N in blocks 7.1 ... 7.The forms containing the clock generator are zeroed out, and register pulses are written to register 5, the first and second blocks are defined with a certain binary code. High-voltage, the inputs of the reference voltage x-levels from the inverse outputs of the element are connected to the reference bus on ilO.ll and 10.NJ affect the elements of the voltage, and the outputs, respectively, of J5 and 17, provide for switching the first and second resistive mat Triggers 14 in a single state. The grids are connected to the first and second ones. If there is a unit (high level) the inputs of the operational amplifier, the output bit of the register 5 in the flow of which is connected to the one-way wide block 7.1 each pulse, characterized in that the som generator 1 is both it is baked in something, in order to keep the speed up The next establishment of the elements of the pa ... device while simultaneously expanding into a single state, the beginning of its functionality, from element 10.1. When the Mth element is entered from the third to K th blocks lN NM with a generator 1 key pulse; with the third to the Kth resistive Known into one state,: matrices, from the first to the Kth memory blocks, high levels of direct outputs of the element and number register, each of the signs Tov 10.1 and iO.N through the elements And 16: the output of which is connected to and | 18, the trigger input of the corresponding Hera 14 is switched to the zero state. When i memory block, and the output of each bit - 3iTOM alternately, starting with the element connected to control input 10.N are set under the influence of the corresponding memory block, the output pulses of the generator 1 to the zero pass of every third to K block state all elements 10.I ... 10.N.pam- ples are successively switched on and the processes are repeated; the corresponding block of keys is formed, the increasing voltage, then the resistive matrix is connected to the decreasing step voltage and the corresponding input of the operating voltage, etc. By changing the binary code in the register-amplifier, the outputs of the first and second 5, it is possible to widely change the memory blocks connected to the inputs of the first step size (Fig. Zv, hj and h), second and second key blocks, respectively, that expands the functional , with the inputs of the reference to Const., 0 8 Vsh.5 BYU1 OFF.5 (1 ... K) 9tiZ.2 111111111II11111 | 1 Fig.Z