SU1425790A1 - Storage with error detection - Google Patents

Abstract

The invention relates to computing. It can be used to construct storage devices with increased reliability. The purpose of the invention is to increase the reliability of the operation of the device by monitoring the order of reading information from the device to the order of its recording. The information supplied to memory unit 4 has information and check bits. Information bits are calculated by modulating the two (i-l) ro and i-ro words entering the information input of block 4, by the first block 2 modulo-two adders. The check bits of the information layer entering block 4 are computed by the first block 3 of convolution modulo. When reading, the recovered information word is obtained by summing modulo two (i-l) -ro and i-ro words from the output of block 4 by the second block 6 of modulators of modulators two. The check bits of the reconstructed information word are computed by the second modulus of the convolution 7, which are compared with the check bits from the output of block 4 by the block 8 of the comparison. The device also contains an input register 1, a delay element 9 and an output register 10. 1 sludge. (L

Description

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The invention relates to computing and can be used in the construction of storage devices with increased reliability.

The aim of the invention is to increase the reliability of the operation of the device by monitoring the correspondence of the order of reading information from the IQ device to the order of its recording.

The drawing shows a block diagram of a memory device with error detection.

The device contains an input register 5, register 1, the first block 2 modulo adders, the first block 3 modular convolutions, block 4 memory, a buffer register 5, the second block 6 modulo adders two, the second block 7 convolution modulo, comparison unit 8, delay element 9, output register 10, read input 11, address input 12, write input 13, information input 1 L ,. information output 15, 25 output 16 Information is unreliable. The device works as follows.

At the initial moment of time, the registers are cleared to 1.5 and about 1 o. in the recording mode, the address is entered at the device address input 12, and the first word of the array is entered at the device information input 14. Recording takes place as follows: since the state of input register 1 varies on the falling edge of the pulse at input 13, then the outputs of block 2 receive the information of the previous recording cycle (i-1) words (from the output of input register 1) and i.e. which has not yet been received in the input register 1 and which should be recorded in block 4 in this recording cycle.

Thus, in each cycle of the record, the information input of the block 4 enters - the sum modulo two previous (L-I) - the recorded word and the i-ro word, written in this

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cycle. The first block 3 calculates the check bits for the word a written in this i-th cycle into block 4. In the read mode, the address is entered at the address input 12 of the device. With some delay in relation to the leading edge of the reading signal), at the output of the check bits of block 4, the check bits of the word to be read will appear, and

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information output - the word itself, which goes to one of the inputs of block 6, to the other input of which nod sticks (il) -e word from buffer register 5. The restored information word from the output of block b goes to information input of output register 10, to the input check bits of which receives the information obtained by block 8 comparison. Census comparison unit 8 (comparison of control bits from the output of block 4 with the control bits calculated by the second convolution unit 7 modulo for the recovered information word. In the output register 10, the recovered information word and the result of comparison bits (error signal).

If the sequence of the read information array is not violated (i.e., it corresponds to the order of recording it in block 4) and block 4 works smoothly, the check bits at the inputs of the comparison block 8 will be equal.

In this case, a logical O appears at the output of the comparison unit 8, which is fed to the input of the control bits of the output register 10. When the output of the output register 10 is output, the following information word appears at the output 15 of the device, and the logical information about the output 16 which indicates that the order of reading information from the device corresponds to the order of its / recording in block 4 and the information words are not distorted during storage.

If the sequence of reading information does not correspond to the order of writing in case of trouble-free operation of block 4 or, on the contrary, the sequence of reading information from the device corresponds to the order of writing it into block 4, and in cells of block 4 fails, the control bits at the input of the block 8 comparisons will not be equal. A logical 1 signal appears at the output of the comparison block 8. This signal, having passed through the output register 10 to the output 16, indicates that the order of reading information from the device does not correspond to the order of its writing to the device or occurs

distortion of information in the process of storage in memory block 4.

Claims (1)

Invention Formula An error detecting memory device containing an input register, an input register, a memory block, first and second convolution blocks modulo, and a comparison block, the information input of the input register being the information input of the device, the address input and the inputs of the modulator two adders, the outputs the first block of adders modulo two and the first convolution block modulo are connected respectively to the information and control inputs of the memory block, the information output of which is connected to the information input molecular register and the first input of the second unit of modulo two adders, a second input coupled to an output buffer register, whose receiving input is connected to the input of the read device outputs si and reads of the memory block are 15 second blocks of modulo adders responsibly, the address input and the write and read inputs of the device, characterized in that, in order to increase the reliability of the operation of the device by monitoring the correspondence between the information from the device and the order of its recording, the first and second blocks of modulo two are entered into it, a register and a delay element, the first input of the first block of modulo two adders and the input of the first module of convolution modulo are connected to the information input of the device, the input input of the input register is connected to the record input The device si, the input register output is connected to the second input of the first block and connected to the information bits of the output register and the inputs of the second convolution unit modulo, the output of which is connected to the first input of the comparison unit, the second input of which is connected to the control output of the memory block, output the comparison unit is connected to the input of the test bit of the output register, the reception input of which is connected to the output of the delay element, the input of which is connected to the reading input of the device, the outputs of the information bits and The output bit of the output register is the information output and the output. The device information is unreliable.