SU1385227A1 - Frequency multiplier - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation, telemechanics and measurement technology. The invention improves the noise immunity of the frequency multiplier, which is achieved by blocking the multiplier in the absence of an input signal. For this, an element OR 5 and a null organ 7 are additionally introduced into the device. In addition, the device contains an element 1 of adjustable delay, element 2 of delay, elements AND 3 and 4, trigger 6, counting trigger 8, tunable filter 9. In the case of multiplicity of periods the input and output frequencies of the multiplier pulses at the inputs of the second element I 4 will coincide and at its output pulses with a frequency of the input signal at the output. The multiplicity input and output frequency is controlled by the presence of a signal at the output of the element 4. 4 hp f-ly, 1 ill. with o (L

Description

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The device relates to a pulse technique and can be used in automation, telemechanics and measurement, technology,

The purpose of the invention is to improve the noise immunity of the frequency multiplier by blocking the multiplier in the absence of an input signal, i.e. for fg 0.

The drawing shows a structural electrical cJteMa device.

The device contains an adjustable delay element 1, a delay element 2, the first element AND 3, the second element AND 4, the element OR 5 and the trigger

6, providing a multiplication of the frequency of the pulse signals. The first input of the element OR 5 is connected to the output of the first .I element 3 and the first input of the second element I 4, its second input is connected to the R input of the trigger 6

and the second input of the second element AND 4, the output of which is the control output of the device, and the output with the input of the adjustable delay element 1, the output of which is connected to the input of the delay element 2 and the C input of the trigger 6, which is connected to the second input of the first elec - And 3, the first input of which is connected to the output 2 of the delay.

To multiply the frequency of a sinusoidal signal, the device contains a null-organ 7, whose input is with the input of the device, and the output is connected to the second input of the element OR 5, the counting trigger .8, the R-input of which is connected to the output of the zero-organ

7, the C-input is connected to the first input of the element OR 5, and a tunable filter 9, the input of which is connected to the inverse output of the counting trigger

8, and the output is the output bus of the device.

The device works as follows.

The input sinusoidal signal in the null organ 7 is converted to short positive pulses, the temporal position of which corresponds to the zero value of the sinusoidal signal with a positive derivative.

A pulse from the output of the null organ 7 zeroes trigger 6 and counting trigger 8.

At the same time, this impulse goes to the second input of the element OR 5, then through the element 1 of adjustable

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delays on the C input of the trigger 6, transfers it to state 1 on the output, thereby allowing the impulse delayed by element 2 to pass through the first element 3 AND to the first input of the OR 5 element for its subsequent circulation.

Thus, in the interval between 10 pulses, from the output of the null organ 7, the C-input of the counting trigger 8 receives pulses with a period determined by the delay in the Circuit Loop.

At the output of the counting trigger 8, a square wave is formed, from which the tunable filter 9 selects the first harmonic in the form of a sinusoidal signal, the frequency of which is the frequency of the input sinusoidal signal K times, where K is the multiplication factor, and the required multiplication factor is set by varying the delay value of the adjustable element 1 delays.

In the case of multiplicity of periods of the input and output frequencies of the multiplier, the pulses at the inputs of the second element 4 And will coincide at its output along the t-, from the pulses with the frequency of the input voltage. According to the presence of the signal at the output of the element, they control the multiplicity of the input and output frequencies of the multiplier. I

Form l. and invention

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Claims (2)

1, A frequency multiplier containing an adjustable delay element, a delay element, a first And element, the first input of which is connected by an output of a delay element, a second And 4 element, the output of which is the first output of a frequency multiplier, characterized in that, in order to improve noise immunity, the element OR is entered / whose first input is connected to the output of the first element AND and the first input of the second element AND, the second input to the input bus of the frequency multiplier and to the second input of the second element AND, and the output to the input of the element is adjustable oh delay, and the trigger, the R-input of which is connected to the second input of the OR element, the C-input to the output of the adjustable delay element and the input of the second delay element, and the output is connected to the second input of the first element I. 40 45 55 313852274 2. The multiplier of claim 1, about tl and -ment OR, counting trigger, R-input due to the fact that for the purpose of which it is connected to the output of the zero-frequency frequency of the sinusoidal gene, the C-input is connected to the first input of the signal at the output sinusoidalment OR, and a tunable filter, signal, it introduced a zero-body, the input of which is connected to the inverse The switch is between the input bus of the intelligent output of the counting trigger, and the output of the frequency resident and the second input is the elec- tron with the output bus of the frequency multiplier.