SU1338013A1 - Ternary computing device - Google Patents

Abstract

The invention can be used, for example, to construct modulo three counting circuits and to control electronic keys. The purpose of the invention is to increase the reliability of the device. The counting device contains asynchronous RS-triggers on the elements AND-HE 2-7, two-input elements AND-NOT 8-11, and three-input elements 12 and 13. The proposed function is forbidden states.

Description

The invention relates to computing and impulse technology and can be applied, in particular, to build modulo three counting circuits and to control electronic keys.

The purpose of the invention is to increase the reliability of the device by eliminating prohibited states.

FIG. 1 is a schematic electrical diagram of the proposed ternary counting device; in fig. 2 is a timing diagram of the signals at the outputs of all the elements of the device (the number of the diagram shows the number of the element at the output of which this signal is formed).

A ternary counting device contains an input bus 1, a first asynchronous RS trigger on AND-NOT 2 and 3 elements, a second asynchronous RS trigger on AND-NOT D and 5 elements, a third asynchronous RS-trigger on AND-NOT 6 and 7 elements , four two-input elements AND-NOT 8-11, two three-input elements AND-NOT 12 and 13.

The input bus is connected to the first inputs of the first two-input element.

that AND-NO 8 and the first three-input ele-30 dah elements AND-NO 9 and 3 and at the output of the ment AND-NO 12, the output of which is connected to the first element AND-NOT 6 of the third

an asynchronous short-circuit trigger consisting of AND-NOT elements 6 and 7.

On both inputs of the second element

The first fy input of the second two-input element H-HPL 9 and the first input of the first synchronous RS-flip-flop, the first output of which is connected to 5 5 of the second RS-flip-flop by the second input of the second two-input are high potentials from the outputs of the NAND element 9. The non-primary input of the third two-input element AND-HE 10 is connected to the n episoN input of the second asynchronous elements AND-HE 4 and 9, which determines the formation of a low level at its output.

chronic RS-flip-flop, the second output of which is connected to the first input of the second three-input element AND-NOT 13 and the first output with the second input of the third two-input element AND-NE 10, the output of which is connected to the first input of the third asynchronous RS-flip-flop, the second input which is connected to the input bus, the second output of which is connected to the second input of the first three-input element AND-NOT 12 and to the second input of the first asynchronous RS flip-flop, the first output of which is connected to the second input of the second three-input element AND-NOT 13 and to the second input W cerned asynchronous RS-flip-flop, a first input of which is connected to a first input of the fourth AND-NO element and to the output I1 of the first two-input AND-NO element, and the second

and

a 6

the input of which is connected to the output of the fourth two-input element AND-NOT 1 I, the second input of which is connected to the output of the second three-input element j

This AND-NO 13, the third input of which is connected to the first input of the second two-input element AND-HE 9, the output of which is connected to the third input of the first three-input element AND-NO 12. The device operates as follows.

Let, at the initial moment before sending positive pulses to the input-15 bus 1 of the device, the first asynchronous RS-trigger on the AND-NE 2 and 3 elements is in a state of high voltage level at the output of the IS-NOT element and 20 that AND NOT 3.

A low signal at the output of the NAND 3 element determines the formation of a high level at the outputs of the NAND elements 8, 12 and the output of the first element 25 of the NANDA of the second asynchronous RS trigger, consisting of the elements of the NAND 4 and 5 .

A low signal on the input bus 1 determines the high signals on the output of both inputs of the second element.

E 5 second RS-flip-flop-high potentials from the outputs

 5 second RS flip-flops provide high potentials from the outputs

elements AND-NOT 4 and 9, which determines the formation of a low level at its output.

A low level at the output of the NAND element 5 determines the formation of a high level at the output of the element NAND 10.

Thus, at both inputs

The second element IS-NE 7 of the third asynchronous short-circuit trigger turns out to be high levels, which ensures the formation of a low level at its output.

At both inputs of the element, NAND 13 also there are high levels (from the outputs of the elements NAND 12 and 9), which ensures the formation of a low level at its output.

In this way. All output signals of the ternary counting device at the initial moment are determined.

Consider the time t, the beginning of the first pulse on the input bus 1. When

four

HIGH level output element AND NOT 7.

At both inputs of the element IS 11, there is a high potential, which determines the formation of a low level at its output.

Other changes of signals at the outputs of logic elements at the moment of 10 t do not occur.

At the instant tj of the beginning of the third pulse on the input bus 1, at both inputs of the AND-HE element 6 there is a high level, which leads to the formation of

This forms a low level at the output of the NAND 13 element, which leads to a change in the state of the first RS flip-flop on the AND-NE 2 and 3 elements. At the same time, at the output of the AND-NE 3 element a high level is formed, and at the output of the AND- element NOT 2 - low level

The remaining signals at the outputs of the logic elements at the moment remain unchanged.

At the end of the first pulse (time tJ) on the input bus 1, a low level appears, which leads to a change in the state of the NANDEM element 9, at the 15th low level at the output of which the high element is formed. Formed low

the level confirms a high level at the output of the NAND element 7 and changes the state of the first asynchronous RS-20 trigger, while at the output of the element NAND 2 a high level is formed, and at the output of the element IS-NOT 3 a low level.

The low level at the output of the element AND-NOT 3 confirms the high level of the element AND-NO 12, generates the remaining signals at the outputs, the logical level at the output of the elements of the device's elements remains at the AND-NE 8 and changes the state of the second at the moment tj unchanged. asynchronous RS-flip-flop. Wherein

At the moment tj of the beginning of the second input-30, at the output of the element AND-NOT A forms a level.

The high level at the output of the NAND 13 element ensures the formation of a low level at the outputs of the NAND elements 8 and 12, the first of which confirms the high level of the NAND element 13, and the second ensures the formation of a high level at the output of the IS 11 element.

The first pulse at both inputs of the AND-HE element 8 turns out to be high. In this case, a low level is formed at the output of the NAND element 8, which leads to a change in the state of the second RS flip-flop on the NAND elements 4 and 5, while a high potential is formed at the output of the second one and a low potential at the output of the first one.

The low level of the first element AND-NOT 6 of the second asynchronous RS flip-flop leads to the formation of a high level at the output of the element IS-NOT 12. Other changes in logical signals at time tj does not occur.

At the end of the second pulse (time t), the potential at the input bus 1 is low, which leads to

Other signal changes on you

the formation of a high level at the output of the element AND-HE 9, which is confirmed by 50 logical elements at the moment, gives a high level at the output of the element t AND-NOT 5..

In this case, the elements do not occur at both inputs.

After the termination of the third pulse, 55 output signals coincide with the signals before the first pulse is applied to all the logic elements of the ternary counting device. This means that the simple operation of the device has completely repeated what was described.

That NAND 10 is high, which leads to the formation of a low level at the output of this element.

The low level at the output of the element AND NOT 10 leads to the formation

four

HIGH level output element AND NOT 7.

At both inputs of the element IS 11, there is a high potential, which determines the formation of a low level at its output.

Other changes of signals at the outputs of logic elements at the moment 0 t do not occur.

At the instant tj of the beginning of the third pulse on the input bus 1, at both inputs of the element AND-HE 6 there is a high level, which leads to the formation of a low level at the output of this element. Formed low

with a high level, and the output element AND-NOT 5 - low.

The low level of the element AND-NOT 5, in turn, forms a high level at the output of the element AND-NOT 10.

The remaining signals at the outputs of the logic elements do not change at the time.

At the end of the third pulse (time tJ) on the output bus I there is a low voltage level, which leads to a change in the state of the third asynchronous RS trigger, while the output level of the AND-HE element 6 forms a high level, and at the output of the AND -NON 7 - low level.

Other signal changes at the output

 logic elements at time t

50 logical elements at time t

 not happening.

At the end of the third pulse, 55 output signals coincide with the signals before the first pulse are applied to all the logic elements of the ternary counter. This means that the further operation of the device completely repeats the foregoing.

51338013 and

The proposed ternary counting device cannot get into the forbidden roystvo completely free from the state 101.

Claims (3)

nor prohibited states. Actually, the circuit is realizable, the states of all elements of the proposed ternary counting device are determined by single signals completely eliminated by the hits of three NG-triggers: to its element at any possible prohibition I-NOT 2 and 3, 4 and 5, 6 and 7. If the condition is opted, to determine the state of the trigger by the signal at the output of the element with a smaller formula of the invention, then the analysis of the operation of the Ternary counting device indicates that the triggers are sequential - holding three asynchronous RS-triggers transition from the state of the first, two-input AND-NOT element (single signals at the outputs of the element and two three-input elements AND-NOT, the tone of AND-NOT 2, A, 6) in the state 011, 15 input bus connected to the first Inputs 001, 110 and further again in 111. The first two-input element AND NONE and In principle, there can still be another first three input element of the AND NAME, the four forbidden states: 000, the output of which is connected to the first 010, 100 and 101 Show that. the input of the second two-input element-circuit implementation eliminates any of the 20 AND-NOT and to the first input of the first one. At zero signal-asynchronous RS-flip-flop, the first one is output-) (at the output of the H-tlE 6 element, the current is connected to the second input: ;, ,,: I;. I-; K ii., I n vi-i:,; i r. i ;; c .1; .1, -1 Г1 1); h1 ID bottom :: n - i; ii ::; i. Cement (II fihiTb gdish.I cibiia. i.. .-: i ill ,, iiC pfiiii i c: h (1d iiJcri.iTO two-input i .r., chgptstsinpye |; oh th 00 (1 , / b of the I-NC gate is connected to the first ijlli nos-picikat) cannot. The input of the second asynchronous RS-trigle signal at the input of the element, the second output of which is connected with IS-HE 6 generates high signals with the first input of the second three-input at the outputs of the elements NE-7, 2 and 13. of the element IS-IE, and the first output - with. Thus, at both inputs of the element A second input of the third two-input ment IS-NO 3 there are high Sigle element AND-NOT, the output of which connections: from the outputs of the AND-HE 2 elements and to the first input of the third asynch-13. At the output of the NE-3 element of the long-distance RS flip-flop, the zero sig- nal signal, which forms By the fact that, in order to make a single signal at the output of the elec, the reliability of operation by full AND-NO 4, i.e., the circuit realization of the exclusion of forbidden states, does not allow the appearance of the forbidden bus connected to the second scion state 100.input of the third asynchronous rs-trigpro.gp.pziruem after the chopper, the second output of which oedinen schennoe state 101. The outputs to the second input of the first trehvhodovo- AND-NO elements 2 and 6 ok.chzyvayuts You are a first AND-NO element and to second input signals sokie. However, the output of the first asynchronous RS flip-flop, element IS-HE 6 is applied to one of the first output of which is connected to the inputs of the element IS-NOT 2. Thus, the second input of the second three-input input signal, a high signal at the output of the element g of the AND-NOT element and to the second input of the second AND-NOT 2 can occur in that only the asynchronous R3-TpHrrepa, if at the second input, the elemental input of which is connected to the first and the AND-NOT 2 there is a zero signal. the input of the fourth two-input element. The source of this signal is an AND-NOT element and with the output of the first two-AND 3. However, the output of this element 50 of the input element is NAND, the second input of the ment is connected and to the input of the element of which is connected to the output of the 4th NAND 4, i.e. at the output of the element NAND 4 of that two-input element NAND, there can be only a single signal. the second input of which is connected to the output. Therefore, the assumption about the formation of the second three-input element of the single signals at the output gg is NOT, the third input of which is connected to the elements 2 and 6 makes it impossible for the first input of the second two-input on the NAND element, the output of which is based on the output of the NAND 4 element and therefore is connected to the third input of the first three-lagful ternary counting device — the IN-NE input element. tl tz fy and 5 ts cpu3.2