SU1336252A1 - Parallel binary code-to-serial quasi-ternary code converter - Google Patents

Abstract

This invention relates to an auto. Literature, computing, and technology can be used in autonomous systems for transforming and encoding information. The aim of the invention is to increase the speed of the device. The device converts a parallel binary code of unit weight into a sequence. body ternary code. The device contains an OR 1 element, a pulse former 2, an AND 3 element, a register 4 and selector channels 5,6, each of which is made on the distributor 7 pulses, AND elements 8, 10 and the element OR 9. 2 Il.

Description

The invention relates to automation, computer technology and can be used in autonomous systems P1 for the formation and encoding of information.

The aim of the invention is to increase the speed of the converter.

Fig, 1 shows a functional diagram of the converter; FIG. 2 shows timing diagrams explaining his work.

The converter contains an OR 1 element, a pulse shaper 2, And 3 elements, a register 4 and the first, second selector channels 5 and 6, each of the KoTopbix is configured on a pulse distributor 7, AND 8 elements combined into a group, an OR 9 element and an AND 10 element ,

The Converter operates as follows.

At each step of the transducer, an N-digit parallel binary is fed to the transducer inputs, the one-25 code which will arrive simultaneously through

no weight

If we compare the input signal and its pr, derivative (respectively, plots 1 and 4 in FIG. 2), then the areas of declines ab, dd, ws will correspond to the areas of negative polarity of the derivative, to the areas of rises vg, hedgehog - the areas of positive polarity, and horizontal plots — plots of zero level on plot 4. Thus, the sign function of the input signal derivative is a three-level function, the discretization of which by clock pulses 1 to 29 on plot 1 leads to a sequential threefold code. Since the computer is built from binary elements, the converter must contain 2 channels: a channel for selecting the symbols +1 and O (plot 3) and a channel for the symbols -1 and O (plot 2), it is not difficult to see that information about individual features x of the input signal is preserved, to the summation of symbols on plots 2 and 3 leads to plot 4,

The structure of the converter when mating it with a multichannel output is greatly simplified, since the formation of the three-level signed function of the derivative of the input signal is carried out without prior differentiation and clipping; signal. In order to be convinced of this, it suffices to consider the nature of the transformations on one of the input signal sections, for example,

In this case, with each subsequent measurement cycle, the amplitude, t, e, of the input number of the converter, in which the pulse appears, increases. For example,

0 during the probe of the area vg (plot 1) on the bars 9-16, the numbers of the levels grow from O to (i-2) and t, e. Therefore, it is sufficient to select the sequence of output pulses in the sections

5 rises in one channel, and in areas of recessions - in another channel.

The essence of the transformations, including differentiation, clipping, discretization, is as follows.

Let the measured value of the input signal in the first cycle correspond to the i-th level. In this case, the i-th input has a voltage pulse.

35

open elements AND 3 on the 1-input of the i-th register trigger 4 and on the second inputs of the i-x elements AND, On the first inputs of the latter in this so those are nothing

30 enters, therefore, the voltage at the outputs of the elements And is equal to O, It occurs only in subsequent cycles, when simultaneously with the appearance of a pulse, one of the information inputs of the inputs receive a delayed pulse at the output of the register 4 trigger and through the distributor 7 diode circuits at the first inputs of the corresponding elements And 8,

40 According to plots 1 and 2 in the second clock cycle, a pulse is received at (1-2) input. At the same time, a pulse is outputted at the output of the register 4 trigger, since the same pulse will arrive at its K-input through the element OR 1, the driver 2 and returns the trigger T. of the register 4 to the initial state. The output voltage of this trigger through diode distributors 7 will open the first inputs of the elements And 8 with numbers below the i-ro in the first channel 5 and with numbers above the i-ro in the second channel 6, Consequently, the output pulse turns in channel 5, which selects plots of function dips.

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50

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The output pulses in channel 5 will appear not only until the end of the decay segment ib, but also in

throughout the entire horizontal section bv. This is due to the fact that if the same input signal level is measured in adjacent clocks, then the output voltage is in both channels 5 and 6, such as, for example, at clocks 7-11 and 19-21 (plots 2 and 3 ). Neighboring pulses at the output of each channel 5 and 6 merge into a single pulse, forming a temporary gate for the passage of clock pulses from the output of shaper 2 through elements 10.

Thus, in accordance with the law of alternation of rises, declines, and horizontal sections, a parallel binary code arriving at inputs 1 - N will be converted into a serial ternary code at the outputs of the inverter 5s of the converter. Plot 4 presents summary information about the source function in the ternary code. The symbols -1 appear on the slopes, the symbols O on the horizontal patches, and the symbols +1 on the slopes.

The increase in technical and economic efficiency of the proposed converter as compared to the known one is due to two factors: a reduction in the volume of the equipment due to the combination of a number of functions in one converter and the preservation of the quality characteristics of functioning regardless of the presence of a constant component and the magnitude of its random variation in the message being encoded,

Claims (1)

Invention Formula The parallel parallel code converter into a serial quasi-troism code containing an OR element, AND elements and a register, characterized in that, in order to speed up the transformation of bodies, a pulse driver and first, second selector channels, each of which is implemented on the pulse distributor, are inserted into it , the group of elements AND, the element OR, and the element AND, the outputs of the pulse distributor are connected to the first inputs of the corresponding elements AND groups, the outputs of which are connected to the corresponding inputs of the elements nta OR, the output of which is connected to the first input of the AND element, the inputs of the OR element are combined with the first inputs of the same elements AND, the second inputs of the same elements AND groups of selector channels, and the output of the OR element is connected through the pulse shaper to the second inputs elements AND, the control input of the register and the second inputs of the elements AND the selector channels, the outputs of the elements AND are connected to the corresponding –information inputs of the register, the outputs are register connected to the corresponding t-distribution box inputs teley selector channel pulse elements and outputs the channel selector outputs are preobrazovate.g- l. 0 0 Editor N. Egorova Compiled by M, Nikulenkov Tehred And, Popovich Proofreader S. Shekmar Order 4055/56 Circulation 901 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, ul. Project, 4 ta -V V