SU1322496A1 - Device for generating signal with single phase-difference-shift keying - Google Patents

Abstract

The invention relates to radio engineering and can be used to transmit digital information. The purpose of the invention is to increase the formation rate by reducing the width of the spectrum of the phase-shift keyed signal (SPMS). The device contains a source of 1 digital signals (CA), block 2 bindings, inverters 3, 10, element 4, trigger 5, switch 6, generation & clock torus 7 clock frequency, frequency divider 8. Strobe pulse shaper 9 and matching unit 11. Switch 6 consists of an inverter 12 and element 2I-RSHI-NOT 13. The CA to be transmitted is converted by block 2 into a start-stop CA, attached to, to the clock fronts. The operation of the divider 8 occurs on the negative front of the pulses. This assignment eliminates errors when gating the CA. Element And 4 determines with the help of a signal from shaper 9, the moments of stepwise changes in the phase of the carrier oscillation by 180. When the signals at the inputs of the And 4 element coincide, a sequence of pulses is formed which controls the formation of an AL. In this case, the switch 6 connects to block 11 either a source carrier signal or an inverted source carrier signal, as a result of which a bipolar signal is transmitted to the line. 13 . P. f-l, 1 ill. l with

Description

The invention relates to radio engineering and can be used to transmit digital information over two-wire lines.

The purpose of the invention is to increase the formation rate by decreasing the width of the spectrum of the phase-shifted signal.

The drawing shows a structural electrical circuit of the proposed device.

The device contains a source of 1 digital signals, block 2 bindings, second inverter 3, element 4, trigger 5, switch 6, clock frequency generator 7, frequency divider 8, strobe pulse generator 9, first inverter 10, matching unit P . Switch 6 consists of an inverter 12 and the element 2I-W-NOT 13.

The device works as follows.

A digital signal to be transmitted over a two-wire line is fed to the input of the signal clamping unit 2, which can be, for example, a universal asynchronous transceiver of the KR581 VA-1 type. In this case, digital signals can be either in the form of a parallel code, - then they go directly to the data inputs of the transmitter, - or in the form of a start-stop digital signal (serial code), - then they are. served at the receiver input. The data outputs of the receiver are connected respectively to the inputs of the transmitter, and the inverted data reception signal is connected to the input of the transmitter and reset the readiness of the receiver. The signal from block 2 binds the signal from the output of the transmitter as a start-stop digital signal tied to the positive edges of clock pulses.

For this, the clock generator 7 constantly generates pulses that have a frequency of 2 times higher than the transmission rate of the digital signal. These pulses are sent to the control input of the signal attachment unit 2, at the output of which, after having been received, a digital signal appears, the value of which can change only at times corresponding to positive edges of clock pulses. A feature of the device is such

anchoring so that the beginning of sending the tied digital signal does not coincide with the positive fronts of the original carrier signal formed at the output of the divider 8 after dividing by 2 times the pulse frequency coming from the output of the clock generator 7, which is ensured by the triggering of the divider 8 along the negative clock edges pulses. This option eliminates errors when strobe a digital signal. The coefficient K is chosen so that the frequency of the original sig

carrier was equal to the speed of transmission of digital signals. In accordance with the previously agreed upon simplification,

Signal from the output of the block 2

the signal is inverted by the inverter 3 and is fed to the input of the element 4, which determines the moments of a jump-like change in the phase of the carrier oscillation by 180 °. For this from

the original carrier signal, the strobe pulse shaper 9 generates (when positive fronts 1 arrive, pulses with a duration shorter than the output pulse

oscillator is 7 clock frequency, and feeds them to another input of element 4. If the signals at the inputs of the element 4 coincide, which corresponds to the transfer of logical zeros, at its output

a control pulse sequence appears. These pulses are produced by means of a trigger 5, triggered by a positive differential on the counting input (a D-flip-flop can be used in the counting mode), and a switch 6 generating a phase-controlled signal by connecting to the input of the matching unit 11 or the original carrier signal,

or an inverted source carrier signal, which is provided by the operation of the inverter 12 and element 2-OR-I I3. For operation of the device, the initial state of the trigger 5 is indifferent,

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The switch 6 and the inverter 10 form a circuit that implements the function of inequality (addition modulo two) of the original carrier signal and the signal from the trigger output. The unipolar signal, finally formed at the output of the switch 6, is converted by the matching unit 11 into a bipolar and transmitted to a two-wire line. A signal in a line can be considered as consisting of heterogeneous direct current packages and having a 2: 1 ratio (maximum value) between the times of the presence of different polarity in the line of the parcels.

Claims (2)

1. A device for generating a signal with a relative relative phase shift keying, containing a common frequency, a source of digital signals, an element, whose output is connected to a trigger input, characterized in that with the aim of increasing the formation rate by decreasing the width of the phase-manipulated signal , an anchor block, two inverters, a frequency divider, a gate-pulse shaper, a switch and a matching block are entered, the output of the digital signal source is connected to the first input of the anchor block, the second whose input is connected to the output geRedaktor E.Papp Compiled by N.Lazarev Tehred M. Morgenhal Proofreader A.Zimokosov Order 2879/56 Circulation 638 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 clock clock, also connected via a serially connected frequency divider and the first inverter, is connected to the first input of the switch, the second and third inputs of which are connected respectively to the output of the frequency divider and the trigger output, the output of the coupling unit through the second inverter is connected to the first input of the element And, the second input of which is connected to the output of the frequency divider via a strobe pulse shaper, the output of the switch is connected to the input of the matching unit. 2. The device according to claim 1, characterized in that the switch consists of an inverter and element 2I-OR-NOT, the input of the inverter being combined with the first input of the element 2I-OR-NOT and is the third input of the switch, the second input of the element 2I-OTI -NON is the second input of the switch, the first input and output of which are respectively the third input and the output of element 2I-OR-NOT, the fourth input of which is connected to the output of the inverter.