SU1322265A1 - Multiplying device - Google Patents

Abstract

The invention relates to computing and can be used in the development of high-speed devices for multiplying numbers represented in any positional type. with the number system. Especially effective - but its application when using large integrated circuits. The aim of the invention is to increase the speed of the device by providing the possibility of forming, at the outputs of the computing units, the bit values of the product of the higher and lower digits of their bit products in the multi code. It is achieved due to the fact that the device for multiplying, which contains the multiplier register 1, n blocks for calculating the bit product values, the buffer registers 3 and A of the first and second groups, contains a casting unit 5 consisting of the summation node 6 and the delay register 7. Zil. efO with

Description

The invention relates to computing and can be used in the development of high-speed devices for multiplying numbers represented in any positional number system. Its application is especially effective when using large integrated circuits.

The purpose of the invention is to increase the speed of the device.

FIG. I shows a block diagram of a multiplier; in fig. 2 is an array of terms, for the case of a binary-coded 64-number system (L 2 and k 6), which is summed up by each block of calculation of digit values of the product until its highest and lower digits are obtained at its outputs works in two-fold code; in fig. 3 shows the process of summing the array of items in FIG. 2 in each block of calculating discharge product values.

The multiplying device contains n-bit multiplicative register, n blocks 2 of calculating bit product values, n buffer registers 3 of the first group, n buffer registers 4 of the second group, reduction unit 5, consisting of summation node 6 and delay register 7 , correction input 8 and input 9 of the device multiplier, output 10 of the device, output 11 of the i-ro register register 1 multiplicand, output 12 of the highest bit of block 2, output 13 of the lower bit of block 2, output 14 of the node 6 transfer, output 15 of the sum node 6. The set of i-ro block 2 calculated the bit values of Institution and i-x buffer registers 3 and 4 may be structured as a single module 16.

Each unit 2 for calculating bit values of a product is a combination circuit that performs the following functions

F X-Y + A + B,

where X, Y are the values of the first and second factors of block 2, respectively; L, B - the values of the first and second groups of the terms of block 2, respectively (in general, the number of the terms in the groups may be different).

FIG. 2 for use in the device of a binary-coded 64-number system (i.e., when, 2 64) and in

the assumption that the highest and lowest digits of the bit product of block 2 are formed in a two-row code, an array of terms is given, which is summed by each block 2 of the calculation of the bit values of the product of the device. The first group of terms A of block 2 is depicted with a sign +, the second group of terms of B is shown with signs X, and the array of partial products formed in block 2 as a result of multiplying the factors X, Y is depicted as a matrix of points.

FIG. 3 illustrates the summation process in block 2 of the addend array shown in FIG. 2. Summation is carried out according to the so-called economical algorithm for folding a multi-source code to a two-row one using single-bit binary adders. Those binary bits of the array items that are processed by the same one-bit binary adder are outlined by an oval line. As can be seen from FIG. 3, the conversion of the original nine-way code to the resulting two-way code is carried out in four steps I-IV. As a result, at the outputs 12 and 13 of block 2 and the highest 64-bit, and the younger 64-bit, the digits of its bit product are formed in a two-bit code.

Block 5 is designed to bring to the single-sided code of the multi-result code generated in the process of multiplication in the first buffer register 4 of the second group. I

The multiplier operates as follows.

In the initial state, the delay register 7 and the buffer registers 3 and 4 of all modules 16 are reset to zero, and the multiplier 1 register holds the unsigned 2-digit multiplicand code (n-k-multiplicand binary code) without a sign. Here it is assumed that the multiplicand and the multiplier are represented in the binary-coded 2 -personal number system, i.e. X1, each bit of both multiplier and multiplier, is a set of k binary digits.

In each of the first n cycles of operation of the device, its input 9 enters parallel to the k binary bits of the multiplier, starting with the lower bits. , At the same time, in the i-oM block 2 of calculating the bit values of the product of the production of PCT, the cumulative k binary bits of the multiplicator arriving at its input are the first factor from the output 11 of the i-ro 2 -batch register of the multiplicand 1, by the k binary bits of the multipliers entering the second multiplier from the input 9 of the device multiplier, and adding to the k younger binary bits of the resulting 2-k-multiplication of the terms, riocTynaronix from the output of the i-ro buffer register 3 to the input of the sub-components of the i-ro block 2, and the terms coming from the output (i + l) -ro buffer register 4 to the input components of the i-ro block 2.

After that, the higher binary bits of the result of the i-block of block 2 from its output 12, generated in a multi-bit code (in a special case in two-sided), are written into i, the buffer registers 3, and the low-order binary bits of the result, also generated in multi-bit code (in the particular case in two-wave), from its output 13 are written in the i-th buffer register A. Simultaneously with the work of the blocks 2 for calculating discharge product values, the block 5, which carries out the conversion to the single-code of the multi-channel code generated in the process of multiplying In the first buffer register 4.

After completing the first five cycles of operation of the device, zero information arrives at its input 9 of the multiplier and then additional n cycles continue, during which information is output from the device with the corresponding conversion, xp animation in the delay register 7 of block 5 and in the buffer registers 3 and 4 all modules 16. The output of a 2-n-bit product in the device is performed via its output 10 in a parallel-sequential code (k bits each per clock).

In the considered case, the zero correction information was supplied to the device correction input 8 in all its 2n cycles. In the same cases when a rounded n-bit product is required to be obtained, it is necessary to submit a k-bit binary code to the correction input input 8 in the first tact of the device. ,100.. . 000. This allows rounding without additional

time costs.

Using input 8 in a certain way, it is possible to simultaneously perform in it an operation of multiplying two n-bit numbers with summing up to n most-significant bits of the product of some n-bit term or group of terms. Input B can also be effectively used to introduce corrections into the product when multiplying numbers in the additional code.

Multiplication of n-bit numbers in the device can be performed in () cycles, if after the execution of the n-th cycle the contents of the buffer registers 3 and A of modules I6 are submitted for final summation to the corresponding inputs of the high-speed multi-input summation block (summation block and corresponding z are shown in dashed lines).

Claims (1)

Invention Formula A device for multiplying, containing the multiplicable register, n blocks for calculating the bit values of the product (n is the number of multiplicand bits), n buffer registers of the first group, n buffer registers of the second group, the output of the i-ro bit of the multiplier register is connected to the input of the first factor The i-ro block for calculating the bit values of the product (i 1,2, ..., p) the input of the second factor is connected to the input of the device multiplier, the output i-ro of the buffer register of the first group is connected to the input of the first term of the i-ro block for calculating the bit bottom values The second product, the input of the second addend of which is connected to the input (i + l) -ro of the buffer register of the second group, the input of the second addendum of the i-ro block for calculating discharge values of the product is connected to the correction input of the device, the inputs of the buffer registers of the first and second groups are connected with the high and low bits of the corresponding blocks for calculating the bit values of the product, characterized in that, in order to increase the speed, the values of the low and high bits of the block for calculating the bit values These products are formed in a multi-code, a casting block is entered into it, which includes a summation node and a delay register, while you the progress of the first buffer register by the second output of the delay register, the input of which group is connected to the input of the first one, is connected to the transfer output of the nodal summing node, the input of the second summation, the output of the sum of which the addend is connected to . I i-h-f-f-lf-f-f-b-f-b X XXXXX X X X X X X t /. Have Thebes. 2 Compiled by N. Markelova Editor P. Gereshi Tehred L. Oliynyk Proofreader, A. Ilyin ., J ...- TT ---..-.-... - - Order 2865/45 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 ////////// l 12 f / J FIG. 3