SU1317446A1 - Information input device - Google Patents

Abstract

The invention relates to computing and can be used dp selection of information channels in multi-channel systems for collecting, recording and processing information. The purpose of the invention is to simplify the device by optimizing the operation algorithm. The device contains two registers, a block of delay elements, an element NAND, a multiplexer. two memory blocks, three AND elements, an NOT element, an OR element, an OR-NOT element, a pulse shaper. Before starting work, the memory blocks are reset. Then, in the first memory block, by a signal, the information is entered on the numbers of the input channels to be processed. Thereafter, the measurement and calibration cycles alternate. In the measurement cycle, the information supplied to the device is sorted based on the attributes recorded in the first memory block. In the second memory block, information about the rates of the channels actually processed in the measurement cycle is entered. In the calibration mode, the information from the second memory block is transferred to the computer, after which the second memory block is nullified. After the calibration is completed, the device goes into a measurement cycle or, if necessary, into the zeroing and setting mode. 3 il. i (Л С со 4 О5

Description

eleven

The invention relates to computing and can be used as a device for selecting information channels in multichannel data acquisition, register and information processing systems.

The aim of the invention is to simplify the device by optimizing the operation algorithm.

Figure 1 shows the structural scheme of the device; Fig. 2 illustrates an example implementation of a memory block; FIG. 3 shows an example of implementation of a block of delay elements.

In the diagram (Fig. 1), the first 1 and second 2 registers are formed, the block 3 of the elements of the program, the AND-NO element 4, the multiplexer 5, the first 6 and the second 7 memory blocks, the first 8, the second 9 and the third 10 And elements, the element NOT 11, element OR 12, element OR-NOT 13, shaper 14 pulses, information inputs 15 and outputs 16 of the device, input 17 of the signal Measurement of the device, input 18 of the signal Calibration of the device, first 19, second 20 and third 21 synchronization input of the device, output 22 signal Device setting, input 23 sig nal / Reset device, address inputs-24 devices, output 2 5 signal Ready device. In Fig. 2, an element 26 and 26, an address counter 27, a driver 28 and a memory element 29 are indicated; in fig. 3 - elements 30-32 delay and the element is NOT 33

The device works as follows.

Before starting work, all memory cells of memory blocks 6 and 7 are reset. In this case, clock pulses are supplied to the synchronous input 21, and signal 1 is input to input 23. Clock pulses from the output of the NAND element 4 arrive at the input of the AND 26 element, the information input of the memory element 29 and the counting input of the counter 27 of the address of the memory block 6. The signal O at the output of the element AND-HE 4 provides the writing of the zero bit to the memory element 29 at the address stored on the address counter 27. According to the positive signal differential at the output of the NAND 4 element, the content of the counter 27 of the address is increased by one unit. Writing the zero bits at other addresses of the memory element 29 is performed similarly. Clock pulses from the output

174462

The element AND-NO 4- passes through the element NOT 11 and the element OR-NOT 13 to the second input of the recording of the memory block 7 and also embraces its cells. Duration T of signal 1 at input 23

must be sufficient to write zero bits to all addresses of memory blocks 6 and 7.

The device operates in two modes: max: the mode of the initial loading of memory block 6 and the mode of sampling data of measuring channels for processing. In the boot mode, an entry is made to the block 6 of the memory 5 of the allocation program. At the same time, a signal 1 is applied to the installation input 22, which provides the connection of the address inputs 24 through a multiplexer

5k information inputs of the counter 20 27 addresses of the memory block 6. The address INPUT 24, accompanied by clock pulses at input 20, receives the address codes of memory block element 29

6 lines for recording single data bits. A signal at input 20, passing through the AND 8 element, is fed to the input of the recording of the address of memory block 6 and provides the recording of the address code from address inputs 24 to the address counter 27. The sync pulses from input 20 also arrive at the input of shaper 28. On the positive edge of the signal pulse, shaper 28 generates a pulse signal of some level that passes through element 26 to input of the operation code of memory element 29 and writes to it a single bit at the address stored Schemus, in the counter -27 addresses. Similarly, single bits are recorded at other addresses arriving at address inputs 24 accompanied by clock pulses at input 20. Writing a single bit at the k-th address into memory block 6 means selecting the data of the measuring channel with the k-th address sign in the sampling mode channels for processing. At the end

25

thirty

40

50

the initial load at input 22 sets the signal o.

In the mode of sampling data for processing, the device alternates measurement and calibration cycles. After re- The data input to the device of measurement channels from sensors of monitored parameters in a measurement cycle follows a calibration cycle, which serves to assess the operability of the entire information transmission path. In the calibration cycle, control signals are sent to the input of the device through all information channels. The operation of the device in data sampling mode is controlled by the signals at inputs 17 and 18. Signals 1 are fed alternately to inputs 17 and 18 and set the measurement mode and calibration mode, respectively.

In the measurement mode, input 1 has a signal 1, and input 18 has a signal o. With the arrival of the information parcel at the inputs 15 accompanied by a pulse at the input 19 on the leading edge of the tracking pulse, the data from the inputs 15 are written to register 1. After the recording is finished, the address part of the message goes to the address inputs of the memory unit 7 and through multiplexer 5 - to the address inputs of the memory block 6. The impulse from input 19 is delayed by element 30 and through element NO 33 comes from the first output of block 3 to the input of the recording of the address of the memory block 7 and through the element 8 to the input of the recording of the address of the memory block 6, recorded the address part of the message 27 addresses. In block 6 of the memory, information is read at the address of the address. If a single bit is read at the output of memory element 29 of block 6, then the information parcel stored in register 1 is to be allocated. The output signal of memory block 6 is fed to the first input of the AND 9 element, the third input of which contains signal 1 from input 19, and the second input comes a strobe pulse from the second output of block 3, which is a pulse from input 19, delayed by elements 30 and 32. In the case of the selection of the information parcel, the output of element 9 is a pulse that passes through element OR 12 to the input of the register entry 2, the second input of the unit 3 of the delay elements, and the first input of the block 7 of memory. From register 1 to register 2, the data entering the information outputs 16 of the device are copied. The signal from the output of the element OR 12 is delayed by the element 31 of block 3 and is fed to the output 25 of the device, indicating that data is available at the information outputs 16. The signal from the output of the element AND 9 in the memory block 7 records the single bit at the address stored in the counter 27 addresses and coinciding with the address part of the highlighted information package. The processing of subsequent information parcels by the device in the measurement mode is similar. Thus, at the end of the measurement mode, in the memory block 7, the unit bits are written to the addresses uniquely corresponding to the address portions of the data feeds that were selected for processing in the measurement mode.

In the mode of entering the inputs 15 of the device of the calibration signals to the inputs 17 and 18, the signals O and 1 are given, respectively. Element 9 operation is blocked. With the arrival at the inputs 15 of the information package, on the leading edge of the tracking pulse, data is recorded in register 1. At the end of the recording, the address part of the message arrives at the address inputs of memory block 7. By the signal from the first output of the block of 3 delay elements, the address is entered into the counter 27 of the address of the memory block 7. Then, information is read from memory block 7 at the recorded address. When the calibration signal address coincides with one of the measurement channel addresses that were selected for processing in the previous measurement cycle, a signal 1 is generated at the output of the memory block 7, arriving at the second input of the element 10, the third input of which contains a signal 1 s input 18 control. With the arrival of the first input element AND Yu of the strobe signal from the second output of the block 3 delay elements, an impulse is formed at the input of the element OR 12 and the input of the driver 14. The pulse from the output: - The element OR 12 rewrites the calibration burst from the register 1 in register 2 and the formation of a ready signal at the output 25 of the device. A shaper 14, at the trailing edge of the input signal, generates a pulse arriving through the OR-NO 13 element at the second input of the recording of the memory block 7 and recording the zero bit at the address stored in the address counter 27. So

Thus, in the calibration mode, the device will only process the value of the calibration signals of those measurement channels that were present in the previous measurement cycle. At the end of the calibration mode, zero bits will be recorded at the seven addresses of memory block 7, thus block 7 will be prepared for operation in the next measurement cycle, i.e. Optimization of the agglomerate of the device operation in the calibration mode allowed simplifying the technical solution.

Claims (1)

Invention Formula A device for inputting information containing two registers, a block of delay elements, a multiplexer, two memory blocks, three AND elements, an OR element, a NOT element, and an NAND element, the first and second inputs of which are, respectively, the input signal of the device Reset and the third input device synchronization, the output of the element AND-NOT is connected to the second recording input of the first memory block, the output of which is connected to the first input of the second element AND, the third input of which is the input signal of the device Measurement, the output of the second element AND connected to OR input element OR whose output is connected to the input of the second register and the second input of the block of delay elements, the second output of which is connected to the second input of the second element AND and the third input of the third element AND, the first input of which is the signal input Calibrating the device, the first input of the element block the delays are combined with the recording input of the first register and is the first synchronization input of the device; the information inputs of the first register are the information inputs of the device; the outputs of the higher bits ervogo register connected to data inputs the upper bits of the second register, whose inputs are the information outputs of the device, the outputs of the lower bits of the first register are connected to the information inputs of the lower bits of the second register, the address inputs of the second memory block and the information inputs of the first multiplexer group, the outputs of which are connected to the address inputs of the first memory unit, the first recording input of which is combined with the second input of the first element AND and is the second synchronization input of the device, the address input of the multiplexer is device input, the information inputs of the second multiplexer group are device inputs, the first output of the block of delay elements is connected to the first input of the first And element, the output of which is connected to the input of the gate of the address of the first memory block, the output of the second memory block is connected to the second input of the third element AND, the output of which is connected to the first input of the element OR, the third output of the block of the delay elements is the output of the device Ready signal, characterized in that, in order to simplify oystva operation by an optimization algorithm, the device comprises a generator of pulses and momentum 5 IGSH-NO element whose output is connected to a second input of the second recording unit memory, the input of which is combined strobiro- Vani address. with the first input of the first element AND, the output of the element AND-NOT is connected to the input of the element NOT, the output of which is connected to the second input of the element AND-NOT, the first input of the element OR is combined with the input of the pulse former, the output of which is connected to the first input of the element OR NOT, the second input of the element OR is combined with the first input of the recording of the second memory block. 0 five 0 0 five . Editor A. Makowska Compiled by V. Fayzrakmanov Tehred- V. Kadar . Order 2425/44 Circulation 672 Subscription VNSHPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4 figs Corrector S.Cherni