SU1314341A1 - Microprogram control device - Google Patents

Abstract

The invention is intended to be used in universal and speck5 76, P and Om6j. ka5 cializirovannyh computers. The invention allows to increase the speed by reducing the number of generated micro-instructions and shortening the operation cycle of the device by combining in time the process of forming the address of micro-instructions. The device contains the address 1 counter, block 2 of memory of micro-instructions, register 3 of micro-instructions, first 4, second 5, third 6, fourth 9 decoders, return register 7, address 8 register, first 10, second 11, third 12 triggers, OR- NOT 13, element NOT 14, element AND-NOT 15, key 16 of the return register, key 17 of a constant. 2 Il. Catch (L CO 4 / Apple (rig.1

Description

113

The invention relates to computing and can be used in universal and specialized computers.

The aim of the invention is to increase speed.

Figure 1 presents the scheme of the proposed device; figure 2 - diagram of the device.

The microprogram control unit contains the address 1 counter, the microinstructions memory block 2, the microinstruction register 3, the first decoder 4, the second decoder 5, the third decoder 6, the return register 7, the address register 8, the fourth decoder 9, the first 10, the second 11, the third 12 triggers, the element OR NOT 13, the element NOT 14, AND-NOT 15, the key 16 of the return register and the key 17 of the constant.

The device works in the following way.

The device operates with two series of sync pulses: the main sync pulses of SI 1 (Fig. 2a) and the auxiliary SI 2 (Fig. 25), which are shifted by half a period relative to the main sync pulses.

With sequential execution of the microprogram, the formation of the address of the microcommand A begins on the positive front of each main clock pulse SI 1, arriving at the counting input of the counter 1 of the address, which was in the state Af,., (Fig. 2B). On the positive front of the next main sync pulse SI 1, arriving at the first input of the register 8 of the address, the contents of the counter 1 of the address A are rewritten into the register 8 of the address (Fig. 2-2) and at the same time the address of the following microcommand A n is formed in the counter 1 of the address (Fig. 2 &). At address Af, from block 2 of memory, micro-command A is sampled, which is recorded at the first input into register 3 of micro-commands when a positive front of the main sync pulse SI 1 is received at its second input (Fig. 2). Thus, on every positive front. SI 1 in the sequential execution of the firmware occurs simultaneously: one is added to the address counter 1, the previous content of counter 1 is rewritten into the address register 8, selected from the memory block 2 of the microinstruction 12

is written to the register of 3 microinstructions.

Assume that microcommand A (fig. 2d) is microcommand

unconditional transition to the return microcommand. The address of the transition is in the external device, the address of the external device is contained in the microcommand and goes to the first input.

data of the first decoder 4. On

the second output of register 3 micro-instructions sets the potential of a logical zero, is determined by A, a micro-command, i.e. operation is allowed on the second control input of the first decoder 4, and there is no signal at the output of the constant key 17. The external device gets the resolved 1st potential from the output of the first decoder 4 and adds

address. go to the data bus

(fig, 2k), the code of the unconditional branch instruction is received from the first data output of the register of 3 micro-instructions to the first data input of the second decoder 5, at the first output of which the potential of the logical zero is formed (Fig. 2), incoming to the first input of the decoder 6 defining the micro-command unconditional transition. The latter generates simultaneously two control pulses of different polarity. At the first output, a positive polarity pulse is formed, at the second, an inverse polarity (Fig. 2f). These

the pulses are equal in duration to the pulses of the auxiliary series of mi 2 supplied to the fifth control input of the decoder 6 and are formed simultaneously with the first mi pulse 2

auxiliary series, incoming

for the pulse of the main series of SI 1, on the positive front of which the microcommand A of an unconditional transition without return was received on the hist 3 microcommands (fig.2b,, j,; k) The pulse from the first output of the decoder 6 enters the first input of the element OR NOT 13 and from its output a pulse of inverse polarity (Fig.2i) arrives at the second load input of the counter 1 microcommand addresses and the potential of a logical zero records information from the data bus A, into this counter (fig.2i, k and 6). Thereby in this

55

the counter will record the address of the microinstruction, To which the firmware will go. On the potential of logical zero at the second output of the decoder 6, per313

The BOM output of the first trigger 10 and the output of the second trigger 11 are set to state 1, and the potential of the logical unit is confirmed at the output of the NAND element 15 (FIG. 2, A, m and n).

On the positive edge of the pulse generated at the second output of the decoder 6, arriving at the C input of the third trigger 12, the latter is set to state O. Then, at its output, a potential O is formed, which goes to the second control input of the return register 7 (Fig. 2o). This potential will record in register 7 return information from register 8 addresses. Thus, in the specified register, the address of the microinstruction following the microcommand of the transition is remembered (Fig.2-g, O. un).

At the end of the positive edge of the pulse formed at the second output of the decoder 6, which arrived at the first input of the AND-NE element 15, the potential of the logical zero will be established at the output of the last (Fig. 2i, LA, H). This potential arrives at the first input of the decoder 9 and the input of the element NO 14. The potential 1 from the output of the element NO 14 arrives at the third control input of the first decoder 4 and the second input of the second decoder 5. This potential 1 disables the operation of the first 4 and second 5 decoders and sets on their outputs 1. Thus it is forbidden for all devices to output information to the data bus and receive information from the data bus (FIG. 2g, k, n).

On the negative pulse front of the main synerium, SI 1, arriving at the S input of the third trigger 12 and following the pulse of the main synchronization series SI I, according to which microcommand A was received in register 3 microcommands, the third trigger 12 is set to one. At its output, a unit potential appears at the second input of the return register 7, and thus ends the recording from the output of the register 8 of the micro-command addresses to the first data input of the return register 7 (Fig. 2a, o).

On the positive front of the same pulse, which arrives at the C input of the first trigger 10, it is set to the zero state (Fig. 2a, l). The

14

the most on the second output of the first trigger 10 6bLa is formed an inverse pulse, which prohibited writing to the register 3 of micro-commands on the controlling third input of micro-command А „,. Thereby, the sequential sampling of micro-instructions from memory block 2 is violated. Micro-command A will not be recorded in the register of 3 micro-instructions, and micro-command A will be stored in this register for the second period of the main synchronization series SI 1 (Fig. 2). On the same front of the pulse of the main synchronization series SI I, arriving at the second input

the address register 8 and the first input of the address counter 1 is added to the contents of the counter, i.e. it forms the address A ,, and the old contents of the specified counter A

rewritten to address register 8 (Fig. 2a, & g).

On the positive edge of the pulse of the main series of the SI 1, following the second pulse, according to which micro-command A was received into register 3 of micro-instructions received at the C input of the second trigger 11, it is set to zero (Fig. 2A), and in the counter 1 addresses are generated

Add address. In this case, the address A is written to the address register 8, and the microinstruction A dd of Fig. 2a, E) -g is recorded in the register of 3 micro-commands. ° The potential of the logical zero from the output of the second trigger 11 is fed to the first input of the element NE 15, the output of which forms the potential of the logical unit (FIG. 2m, n), which forms the potential of the logical zero at the output

element HE 14 and is fed to the third input of the first decoder 4 and to the second input of the second decoder 5, thereby permitting their operation.

Suppose that microinstruction A .. is a microinstruction of unconditional

the transition to a microcommand with a return, the address of the transition is contained in the microcommand itself.

In between the first impulse

the main series of SI 1, according to which the microinstruction-Hell was taken into register 3 of microcom-1, and the second pulse of this series elements of the device work in the same way as in the execution of microcommand A except for the first decoder 4, the key 16 of the return register, the key 17 of the constant and a decoder 9. After entering the positive 5 3

the main front of the pulse of the main synchronization series SI 1 (FIG. 2) to the third input of the register of 3 micro-commands, according to which the micro-command A "is recorded in mode

the gist 3 microinstructions and at its second output the potential of the logical unit is established, which serves as a sign that the microcommand contains information transmitted to the data bus. The potential of a logical unit from the second output of the register of 3 micro-instructions comes to the second input of the first decoder 4 and prohibits its operation, i.e. all external devices are relatively described and connected to the data bus receive from the output of the first decoder 4 potentials that prohibit the issuance of information on the data bus.

The potential of the logical unit from the second output of the register 3 microinstructions enters the second input of the key 17 of the constant and allows the transfer of information from its output to the data bus (figure 2k). Information from the data bus to the micro-command address counter 1 is recorded in the same way as when micro-command A was executed (Fig. 2,,, K, l, M in). The return register 7 will write the address of the microcommand A;,., In accordance with the time diagram (Fig. 2a, 5,0 and u). In order to ensure that the executed firmware returns to the micro-command stored in memory block 2 at address A, it is necessary to ensure that the return register 7 is transferred via the data bus to the return address counter t during the second execution cycle of firmware A, i.e. during the time between the first impulse following the impulse of the basic synchronization series SI 1, according to which microinstrument A ;, and the second impulse of the basic synchronization series SI 1 were received on register 3 micro-commands (Fig. 2 sk- and a). Control signals for the operator

No return forms the decoder 9. After that, at the third output of the register of 3 micro-commands, the potential of the logical unit is used, which indicates that the micro-command of the transition is returned. With the appearance of the potential of a logical zero at the output of the NAND 15 element at the second output of the decoder 9, a potential of a logical zero is generated (FIG. 2p), which will prohibit the transmission of information from

6

the first output of the register 3 microcommands through the key 17 of the constant to the data bus. At the same time, this potential arrives at the second input of the key 16 of the return register and permits the transfer of information to the data bus (FIG. 2 k and p).

On the first output of the return decoder 9, a positive

a pulse equal in duration to the impulse of the additional synchronization series SI 2, which is fed to the third input of the return decoder 9 (FIG. 2c, a, S, and a). Impulse from the second exit

the inverse polarity decoder enters the first input of the I address counter and ensures that information is entered from the data bus (Fig. 2e, and to &), i.e. the contents of register 7 will be returned to the data bus.

25

On the positive front of the second pulse of the basic synchronization series SI 1, arriving at the second input of the counter

1 address, to the second input of the register 8 addresses and the third input of the register 3 microinstructions, add one to the contents of counter 1 of the address and its contents will be equal to A. The old contents of the specified counter will be overwritten into the register 8 of the address, the contents of which will be equal to A.,, and micro-35 command A is written to the register of 3 microinstructions, (Fig. 2a, g, d and a).

In accordance with the principle of operation of the proposed device, the next microinstruction in register 3 microinstructions will be the microinstruction.

40 A (Fig. 2-1). Thus, there is no need to put after the microcommand AJ, the microcommand of returning to the microcommand A ,,.

45 formula, inventions

A microprogrammed control unit containing an address counter, a memory block M1 of crooks, a mic50 rocomand register, first to fourth decoders, a return register, first and second triggers, the output of the microinstruction memory block connected to the information input of the micro55 command register, characterized in that in order to increase speed, the address register, the third trigger, the NAND element, ele713 are entered into it

ment.NE, the element OR NOT, the key of the return register, the key of the constant, and the input of the device command code is connected to the information input of the address counter, the output of which is connected to the information input of the address register, the output of which is connected to information, the input of the return register and the address input the microinstructions memory block, the microoperations register microoperations field output is connected to the device’s first microoperations output, the microomand register information source field output is connected to the information input of the first decrypt ra, the output of which is connected to the second output of microoperations of the device; the output of the field of receiver code information of the micro-register is connected to the information input of the second decoder, the first output of which is connected to the third output of the micro-operations of the device; the output of the field of the micro-command type register is connected to the first gate of the first decoder and the first Yush; by the input of the constant key, the output of the constant field of the micro-register register is connected to the information input of the constant key, the output of which is dinene output device constant, the input conditions of the device connected to the first information input of the third decoder, the first output of which is connected to the first input of the element OR NOT, the output of which is connected to the synchronization input of the address counter, the output field of the return code of the microcommand register the decoder, the first output of which is connected to the second input of the element OR NOT, the second output of the second decoder is connected to the second information input of the third decoder, the third output second decoder 18

The third output of the second decoder is connected to the fourth information input of the third decoder, the fifth output of the second decoder is connected to the fifth information input of the third decoder, the second output of which is connected to the installation input of the first.

trigger, the direct output of which is connected to the information input of the second trigger, the output of which is connected to the first input of the NAND element, the output of which is connected to the second information input of the fourth decoder, the second output of which is connected to the second control input of the constant key and to the control input return register key whose output

connected to the output of the device return address, the first synchronization input of the device is connected to the counting input of the address counter, to the synchronization inputs of the address register, microinstructions register, first and second triggers, and to the installation output in the third trigger I, the output of which is connected to the synchronization input of the return register, the output of which is connected to the information input of the return register key, the second synchronization input of the device is connected to the gate inputs of the fourth and third decoders, the second output

which is connected to the installation input in 1 of the second trigger, to the synchronization input of the third trigger and to the second input of the NAND element, the output of which is connected to the input of the element

.NON, the output of which is connected to the building input of the second decoder and to the second gate input of the first decoder, the inverse output of the first trigger is connected to the input

permission to write the microinstructions register.

Order, 2214/49

Circulation 673 Subscription

VNIIGTI State Committee of S.SSR

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. D. 4/5

Production and printing company, g.) Genus, ul. Project, 4

Claims (1)

Claim A firmware control device comprising an address counter, a micro-command memory block, a micro-command register, first to fourth decoders, a return register, first and second triggers, the micro-command memory block output being connected to the micro-command register information input, characterized in that, in order to improve performance , address register, third trigger, AND-NOT element, ele 7 1314341 ment. NOT, element OR NOT, return register key, constant key, and the input of the device command code is connected to the information input of the address counter, the output of which is connected to the information input of the address register, the output of which is connected to the information. the input of the return register and with the address input of the micro-command memory block, the micro-operation register output of the micro-command register 10 is connected to the first micro-operation output of the device, the micro-command register information source field of the micro-command is connected to the information input of the first decryptor 15, the output of which is connected to the second micro-operation output devices, the output of the code field of the receiver of information from the register of microcommands is connected to the information input of the second decryptor-20 of the torus, the first output of which is connected to the third output of the microoperations of the device properties, the output of the attribute field of the type of micro-command of the micro-register register is connected to the first gate input of the first decoder and the first control input of the constant key, the output of the constant field of the micro-register register is connected to the information input of the constant key, the output of which 50 is connected to the output of the device constant, the device conditions input connected to the first information input of the third decoder, the first output of which is connected to the first input 35 of the OR-NOT element, the output of which is connected to the synchronization input of the address counter, the microcode register return code field output is connected to the first information input of the fourth 40 decoder, the first output of which is connected to the second input of the OR-NOT element, the second output of the second decoder is connected to the second information input of the third decoder, the third-45th output of the second decoder is connected to the third information input of the third decoder, the fourth output of the second decoder is connected to the fourth information input of the third decoder, the fifth output of the second decoder is connected to the fifth information the input of the third decoder, the second output of which is connected to the installation in 1 of the first trigger, the direct output of which is connected to the information input of the second trigger, the output of which is connected to the first input of the NAND element, the output of which is connected to the second information input of the fourth decoder, the second output which is connected to the second control input of the constant key and to the control input of the return register key, the output of which is connected to the output of the device return address, the first synchronization input of the device is connected with the counting input of the address counter, with the synchronization inputs of the address register, micro-command register, the first and second triggers, and with the installation output in 1 of the third trigger, the output of which is connected to the synchronization input of the return register, the output of which is connected to the information input of the return register key, the second input device synchronization is connected to the gate inputs of the fourth and third decoders, the second output of which is connected to the installation input in 1 of the second trigger, with the synchronization input of the third trigger and with the second the input of the AND gate, the output of which is connected to the input of the NOT gate, the output of which is connected to the gate input of the second decoder and to the second gate input of the first decoder, the inverse output of the first trigger is connected to the micro-command register enable input. X sj “r k, 'g” * g 4; V, '> 7H 5 rq * S ¹ D Xi £ •5· is X X X '’B Ϊ5 h § Sq 4 ^ 3 S3 g Vi X Th V t Ϊ '