SU1303998A1 - Device for monitoring parameters - Google Patents

Abstract

The invention relates to computing and can be used to monitor discrete sensors. The purpose of the invention is to enhance the functionality by generating a service request signal. A device for monitoring parameters contains sensors 1 parameters, a block 2 interface, the first element OR 3, a register 4, a bus 5 clock pulses, a block 6 interface, a driver 7 pulses, the first element AND 8, a counter 9 pulses, the first trigger 10, the second element OR 11, second register 12, adder 13 modulo two, third element AND 14, second trigger 15, second element AND 16, block 17 elements AND, first control output 18, control input 19 of the device, information outputs 20 of the device . In this device, it is possible to convert a parallel code carrying information about the state of monitored sensors into a serial code with subsequent processing, as well as forming a request signal for the service of the received information. 3 il. with S (Л с: -imtb со о со со СО. 00

Description

The invention relates to computing and can be used for ontrol discrete sensors.

The purpose of the invention is to expand the functional capabilities by generating a service request signal.

Figure 1 shows the functional diagram of the device; in FIG. 2 and 3 - time diagrams of the device.

The device contains sensors 1 parameters, the first block 2 of the conjugation, which includes the first element OR 3 and the first register 4, the bus 5 clock pulses, the second block 6 of conjugation, as well as the driver 7 pulses, the first element And 8, the counter 9 pulses, the first trigger 10, the second element OR 11, the second register 12, the adder 13 modulo two, the third element AND 14, the second trigger 15, the second element AND 16, the block 17 elements And, the control output 18 of the device, control input 19 devices, information outputs 20 devices.

The device works as follows.

The device periodically polls and monitors the status of discrete sensors. Since monitored sensors are usually located in peripheral devices, it is necessary to convert the parallel code from these sensors into a serial code (to reduce the number of connections). This conversion is performed by the first interface unit 2 located in the Peripheral equipment. Information is recorded into the first interface unit 2 and the CE extracts this information from it using control signals generated by the second interface unit. When receiving a sequential code, the latter analyzes the changes in the incoming signals and, if there are any changes in them, at the end of the reception of the information parcel, generates a request signal for its service. After that, the received information packet on the receipt of the service enablement signal from the computer is read in the form of a parallel code at the outputs of the device. The second block 6 of the interface is located in the input blocks of the computer.

Let us consider in more detail the operation of this device. The processing of incoming information is performed during one cycle. The operation cycle of the device is set by the counter 9, which is set to a number of clock pulses, which is equal to the number of monitored sensors. When the device is turned on, all the memory elements are reset, and in register 4 a parallel code is written that enters its information inputs from the sensor outputs 1. For simplicity, the initial setting circuit is not shown in it.

To pass the clock pulses through the element And 8 at its inverse input there must be zero potential, which is formed at the output of the element I 1 6 as a result of zeroing of the trigger 15 on the initial setting signal during power-up or on arrival at its R input from the control input 19 single impulse during servicing of this device. In this case, the clock pulses pass through the AND 8 element, which allows the device to process information received from the monitored sensors. When receiving new information, the trigger 15 triggers, as a result of which the trigger 10 triggers at the output of the AND 16 element on the unit. This single signal blocks the passage of clock pulses through element 8. At this time, the device is in standby mode, i.e. at that time it does not rewrite the next information from register 4 to register 12. Only after a single impulse arrives at the control input 19, when the trigger 15 clears, and the output of the AND 16 element changes the single signal to zero, the clock pulses start again, pass through AND 8, which allows the device to proceed to the next information processing cycle (see FIGS. 2 and 3). 2, the initial setup signal is shown dotted. Information can be recorded at the initial moment of time also without using the signal of the initial setup, and with the help of a single pulse generated by the trigger 10. The latter produces the specified single pulse by means of two control pulses, which are formed in the pauses of clock pulses at the output of the pulse former 7. In this case, the start of recording information in register 4 is delayed by the time that counter 9 is working (.: M. FIG. 3). Clock pulses formed at the output of the element And

10, the single signal changes to zero, with the result that register 4 is prepared for the mode of next retrieving information from it. At the same time, at the output of the OR 11 element, a single signal is retained due to the presence of a single signal at its second input. After that, the device is in the standby mode of its service, 8 the pulse counter 9 is filled and passes to the control input of the first register 4. As a result, information is read in the form of a sequential code from the first Q register of the van. Upon the arrival of a single pulse 4 and recording it in the second register 12. A signal permitting to produce This information also goes to the maintenance of this device, the first input of the adder 13 modulo the control input 19 is read- two, to the second input of which the input the received information from the second information from the last output of the re-jj register 12 through the block, 17 elements

gistra 12 shift. Thus, using the modulo-two adder 13, the received (current) information is compared with the previously issued information stored in register 20 12. If at least one of the bits of these information is unequal, the output signal of the adder 13 is a single signal, which (if there is a delayed clock pulse at the second 25 input of the element And 14), having passed the element And 14, will switch the trigger 15 into one state. A single signal is output at the output of this trigger, as a result of which a blockage is removed from the first input of the element 16. After the completion of testing the counter 9, a single signal is generated at its output, and then when a pulse delay delay pulse appears at the output of the driver 7, At the output of this trigger, the zero signal changes to a single one, which zeroes the counter 9 and the input 35

And in the form of a parallel code. Each position of this code carries information about the state of the monitored object.

Simultaneously with the acquisition of information, the trigger 15 is reset to the zero state by means of the specified control signal. As a result, at the output of the AND 16 element, the single signal changes to zero, which leads to a change of the single signal to zero at the output of the OR 11 element and to unblock the inverse input of the first And 8 element. After that, the clock pulses begin to pass through this element. This means that the device has started the next information processing cycle.

If during the next cycle of recording information from the sensors in the first register 4 their state has not changed, then the information in this register will be identical to that previously issued and stored in the second register 12. In this case, during the next processing cycle

em on the first control input of the first

register 4, and through the element OR 3 - to the second control input of this register for recording information signals from sensors 1 into it. In addition, a single signal from the output of trigger 1 through the element OR 11 is fed to the input of element AND 16, as a result the latter is triggered and a single service request signal is generated at its output. This signal is fed to the control output 18 of the device, to the input of the element OR 11, and to the inverse input of the first element AND 8, as a result of which the passage of clock pulses through this element is prohibited. The next clock pulse, having passed the pulse shaper 7, resets the trigger 10 to the zero state. At the output of this trigger

3998

four

10, the single signal changes to zero, with the result that register 4 is prepared for the mode of next retrieving information from it. At the same time, at the output of the OR 11 element, a single signal is retained due to the presence of a single signal at its second input. After that, the device is in standby mode to serve Q vani. Upon the arrival of a single pulse signal that permits servicing of this device, control input 19 is used to read the received information from the second jj register 12 through the block, 17 elements

0 5 o

five

And in the form of a parallel code. Each position of this code carries information about the state of the monitored object.

Simultaneously with the acquisition of information, the trigger 15 is reset to the zero state by means of the specified control signal. As a result, at the output of the AND 16 element, the single signal changes to zero, which leads to a change of the single signal to zero at the output of the OR 11 element and to unblock the inverse input of the first And 8 element. After that, the clock pulses begin to pass through this element. This means that the device has started the next information processing cycle.

If during the next cycle of recording information from the sensors in the first register 4 their state has not changed, then the information in this register will be identical to that previously issued and stored in the second register 12. In this case, during the next processing cycle

this

information on both inputs of the adder 13 there will be identical signals, therefore the adder 13 will not operate and the device will not generate a single request signal for its service at its control output 18, i.e. no information will be provided to the outputs 20 of this device. After testing the counter 9 pulses at the output of the trigger 10, a single pulse signal is again generated, which is fed to the first interface unit 2 for the next recording in its register 4 IR: formations from the sensors 1 parameters. Thus, the information is processed during one cycle, and At the end of the cycle, the states of the parameter sensors are polled, i.e. entering information from them into the register 4. Eat

513

This information can only begin if the device is not in standby mode.

Form

ula invention

A device for controlling parameters containing the first And element, the And element block, the pulse counter, the first and second triggers, the output of the second trigger is connected to the first input of the second element And, the third And element, the modulo two, the first input of which is connected to the output of the first

register, the second input - with the first you - f5 input of the first element And, with the output

The second element And with the first output of the device for controlling parameters, the second outputs of which are connected to the outputs of the block of elements And, the third input of which is connected to the R-input of the second trigger and the second input of the device for controlling parameters, the output of the second element OR is connected to the second input The second element And, the output of the second register and the first input of the block of elements And, the second inputs of which are connected to the second outputs of the second register, the inputs of the first register are connected to the outputs of the sensors of 20 parameters, different in that , in order to expand the functionality by forming a service request signal, two OR elements are entered and the first register for the first register is connected to the pulse inizer, the input of which is connected to the forward input of the first AND element and to the first input of the device for controlling parameters, and output is njajTTLrxruTruTruxnjTJTJ

7 .JVUSHUUULLLJShJShShlIUSShJIfUULnOflL

the keys to the C input of the first trigger and to the first input of the third element I, the second input of which is connected to the output of the modulo two adder, the output of the first element I connected to the first input of the first element OR, to the control input of the second register and C input of the counter pulses, the R-input of which is connected to the second input of the first OR element, to the first control input of the first register, to the output of the first trigger and to the first input of the second OR element, the second input of which is connected to the inverse

formation input of the second register, and the second control input of the first register is connected to the output of the first OR element.

lLLJJ J J JJ ° lJPLGLLJ -g

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5 JTruijajn njiJiJiJiJi

7 "JlOiUlflJinjinJULJlllJlJ

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Editor M.Petrova Order 1310/48.

Compiled by I.Shvets Tehred I.Popovich

Corrector C

Circulation 864 Subscription

VNISHI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

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Fig.Z

Proofreader S. Shekmar

Claims (6)

The claims 5 A device for monitoring parameters, containing the first element And, the block of elements And, the pulse counter, the first and second triggers, the output of the second 10 trigger is connected to the first input of the second element And, the third element And, the adder modulo two, the first input of which is connected to the output of the first register, the second input - with the first output of the second register and with the first input of the block of elements And, the second inputs of which are connected to the second outputs of the second register, the inputs of the first register are connected to the outputs of the sensors 20 parameters, characterized in that, with In order to expand functionality due to the formation of a service request signal, two OR elements and a pulse shaper were introduced, the input of which is connected to the direct input of the first AND element and to the first input of the device for parameter control, and the output is blowing 6 keys to the C-input the first trigger and the first input of the third AND element, the second input of which is connected to the output of the adder modulo two, the output of the first AND element is connected to the first input of the first OR element, with the control input of the second register and Gate. pulse pulse ^ R-input of which is connected to the second input of the first element And $ And, to the first control input of the first register, to the output of the first trigger and to the first input of the second element OR, the second input of which is connected to the inverse input of the first element And, with the output of the second element And and with the first output of the device for monitoring parameters, the second outputs of which are connected to the outputs of the block of elements And, the third input of which is connected to the R-input of the second trigger and with the second input of the device for monitoring parameters, the output of the second element OR connected to the second input of the second AND element, the output of the first register is connected to the information input of the second register, and the second control input of the first register is connected to the output of the first OR element. 3 ^ TJTJTJTJT ^ _nj ^^ nJTJTJT-Tl_r 4 --------------------------- L ._____________ h ------------------ ------- ¹ . '-------- j — gpll__gghgipluggggit-p - g' h p I — I _____ L __________ 'h-gt ______ gt g — I ________ ___ GT ______ GT ___ I --- 1 --- FIG. 2 5 -shtgi-bang ^^ 7_JlOJUUUinJlTL ^ f ₇ J --------— Ί -------------- $ ._ JbTlJnLJ ^ __Г Vf 12 ₂ w ______ ΓΊ __________ _________ Γ “Ί ________ ____ ΓΊ _____ P _____ 2___TL__ _____________ P —_____________.____ FI.3