SU1300466A1 - Device for extracting square root - Google Patents

Abstract

The invention relates to computing and can be applied in process control systems, in specialized computers. The aim of the invention is to increase the speed due to the decomposition of the calculation algorithm into stages with large and small steps. The device contains the first register 1, the first adder 2 elements And 3 groups, the first switch 4, the second switch 5, the second adder 6, the comparison circuit 7, the first counter 8, the second register 9, the third register 10, the first trigger 11, the first element ШИИ 12 , the second trigger 13, the generator 14 clock pulses, the first element And 15, the second element And 16 the second counter 17, the fourth register 18, the second element OR 19, the third element And 20, the first 21, the second 22, the third 23 delay elements clock input 24. 1 Il. (L -J-; CLE 22 U bo

Description

The invention relates to computing technology and can be used in control systems for flexible automated productions, technological processes in the following specialists:.

The aim of the invention is to increase speed by decomposing

positions of the calculation algorithm into stages with large and small steps.

(ti.a)

F (t,)

+ 2

The drawing shows the functional diagram of the device.

The device for extracting kva, the main root contains the first register 1, the first adder 2, the elements of the AND 3 groups, the first switch 4, the second switch 5, the second adder 6, the comparison circuit 7, the first counter 8, the second register 9, third register 10, first trigger 1, first element 20 OR 12, second trigger 13, generator

clock pulses 14, the first element And 15, the second element And 16, the second

counter 17, fourth register 18, the second formation of the function at

swarm element OR 19, third element

And 20, first 21, second 22, third

23 delay elements, clock

input 24,

The device operates as follows.

An analysis on the bit level of continuous monotone functions, in particular, the function F (t) and 4G, showed that the meander of the i-bit position of the function F (t) consists of the segments of the argument called the intervals of (b - (j)) i -ro bit on which the i-th bit takes a constant value - only where t- is an unequal node

 .

; с о, 1,2,. ,, which is L -Calculation of (j + l) -ro and constants based on the J-M interval and, moreover, the value of the function

l

quantum 2 junior bit to implement deployment

the current argument argument t ends

thirty

where t

h + g

i t

e

- the node is uniform

GH (t "4

--o lt -

 0, l, 2, .., i h 2 0,1,2 ,,., The swarm is realized.

It is advisable to close both large and small

step

case conversion from two stages. On the first

to 1 or only o, Between the intervals of the function F (t) and the finite differences of the inverse function φ (t) (F (t) 1 / φ (Ь)) there is a one-to-one correspondence

Li (j) Vj, (1)

where L; (j) is the j-th interval of the constancy of the i-th bit of the function F (t); H j is finite difference

the first order of the inverse function Ф (t), considered on the grid (A) C) {t n

 - - i «« i hq. 2-,

Difference u ° S; (j) L; (j + l) - - L; (j) intervals of constant nazgde and

Vana right j-th trend trend of discharge

and

u ° S; (j)

 nd (;,

(2)

where and

H | - j is the difference of the second order of the function (t). Over the interval of the i-ro discharge constant, the function F (t) is changed by quantum 2, i.e.

(ti.a)

F (t,)

+ 2

education function at

KS

where t- is a node of irregular grid

 .

 z:

; с о, 1,2,. ,,, whose step is L - L; (c) Vc. Calculating the (j + l) -ro interval of a constant based on information about the J-M interval and changing the value of the function F (t) by

l

the low-order 2 quantum allows realizing decompression transform for the current value tj of the argument t, when

0

where t

h + g

i t

e

(3)

- node of uniform grid

GH (t "4

--o L-t - b oP

 0, l, 2, .., i h ,, 2-, j, 2 0,1,2 ,,., On which the transformation is realized.

In order to achieve a faster conversion rate, it is advisable to sweep large and small

in steps. In that

In this case, the transformation consists of two stages. At the first stage

dets sweep big step in some average

q-M de bit

(), After the condition tg is fulfilled, the transition to the lower L -th digit is performed and the second stage of conversion is realized,

In general, the scan of the function F (t) and -Tt is written as follows:

50

Stage 1

55

Stage 2

2Z L, (m) - BO

L

where CP +, is a constant,

As initial values, the values of the interval of constancy and the local trend are given, corresponding to the node t of the grid cOj,,

In the transition from the first stage to the second t ,, tj ,,, FCt} ,,) F (t5 ,,)

The conversion for the current value of the argument ends when condition (3) is met. The second stage realizes, within the interval of a constant LO (P + I) of the function F (t) and 4G, its interpolation by a linear function. with derivative Vl r.,

 (p + l).

In the device diagram, the local trend value ° 5 (p) is stored in the first register 1, the interval of the constant Lo (p + l) is calculated in the first adder 2, the argument values

 PII "IlLgCn) and t :.

п о т-0

second summator 6, tp comparison, or. tj. with tj implemented in the scheme

Comparison 7, the value of the argument tg is calculated in the first counter 8, and the value of the function F (t) a -jt is formed in the second counter 17 and stored in the second register 9, count-, j. Input (input) pulses with a weight of 2 (0, 1.2, ..) are fed to the input of 24 devices,

In the initial state, register 9, triggers 11 and 13 are reset. The first counting pulse of the clock input 24 of the device is fed to the synchronization input of the second register 9, to which the value of the function F (t |) is written, and to the input of the first counter 8, increasing its content by 2. Passing through the first delay element 21, the counting pulse resets to O the minor (Lq) bits of the counter 17, In addition, a second trigger 13 is switched on the falling edge of the counting and pulse, the unit from the forward output of which goes to the second inputs of the elements And 15 and 16, Element And 16 is open at the first input by a signal log, 1 from the inverse output of the first trigger 11. Clock pulses from the generator 14 clock pulses through the open element And 16 arrive at the input

five

O

five

e j

bit with a weight of 2 second counter 17 and increase its content

-H,

on quantum 2,

In addition, the clock pulses arrive at the clock input of the first adder 2, in which its contents are added with the code in the first register 1,

Thus, in the adder 2, the current constant value interval Lo (p + l) is calculated. Log, 1 from the inverse trigger output 1 1 opens a group of elements And 3,

The signal from the direct input of this trigger goes to the control inputs of switches 4 and 5. As a result, one of the inputs of the second adder 6 receives the code from the third register 10, the other input is the binary code of the interval La (p + l). adder 6 an argument code appears. which is compared in the comparison circuit 7 with the code from the first counter 8.

D1 If, t, then the output of the circuit of Comparison 7 remains a log, O, In this case, the fourth register 18 records the code from the outputs of the bits of the second adder 6, When performing the sweep with a large pinch, t, e. at intervals of q-ro discharge, in the third register 10, the code from the output of the second adder 6 is recorded regardless of the result of the comparison operation.

When the output of the comparison circuit of 7 units appears, the first trigger II switches to 1 and the log, O from its inverse output closes the AND 20 element and in the fourth register J8 remains the same value of the sum

E

ZlL (, (n) intervals of the constant q-ro

bit

At zero on the inverse output of the first trigger 11, the transition to the sweep is performed with a small pin. The clock pulses from the generator 14 are fed to the input of the younger digit 2 of the second counter 17 and increase its content to quantum 2. The code from the fourth register 18 is fed to one group of inputs of the second adder 6, and the code La (p + 1 ), At the output of the second adder 6, the code tj, .2 appears, which

is compared in comparison circuit 7 with the code of the first counter 8 and is written into the fourth register 18.

Sweep in small steps, i.e. intervals of the L – th bit of the interpolation direct are performed until the output of the comparison circuit 7 is equal to one, In this case, the first flip-flop 11 switches to O and switches the second flip-flop 13 to O, which locks elements And 15 and 16.

B

That is where the calculation of the function F (t.) And Tit ends. When the next counting pulse arrives at the device clock input 24, the described computational process repeats.

Claims (1)

Invention Formula A device for extracting a square root containing two counters, two adders, a comparison circuit, three registers, two triggers, a group of elements AND, the first element OR, two elements AND, two delay elements and a generator of clock pulses, the clock input of the device connected to the first input of the first the OR element, the outputs of the first register and the first counter are connected respectively to the information input of the first adder and to the first information input of the comparison circuit; the output of the clock generator is connected to the first input The first element And, the second and third inputs of which are connected to the outputs of the first and second triggers, respectively, the counting input of the second trigger connected to the output of the first element OR, the output of the second counter is connected to the 45 register and to the first input of the third the formational input of the second register, the synchronization input of which is connected to the clock input of the device, characterized in that, in order to increase speed, a fourth register, two switches, a third delay element, a second OR element and a third AND element, and the older q bits of the first adder (q is the bit number of the change in the calculation step) are connected to the first five 0 the inputs of the AND elements of the group, the second inputs of which are connected to the inverse output of the first trigger, the direct output of which is connected to the control inputs of the first and second switches. The first group of information inputs of the first switch is connected to the outputs q of the higher bits of the first adder, (A - q) whose lower bits (A is the width of the argument) are connected to the second group of information inputs of the first switch, the outputs of the AND group and the first the switch is connected to the inputs of the first term of the second adder, the inputs of the second term of which are connected to the outputs of the second switch, the first and second groups of information inputs of which are connected to the outputs of the third and fourth re respectively, the output of the second adder is connected to the informational inputs of the third and fourth registers and the second informational input of the comparison circuit, the sign output which is less connected to the counting input of the first trigger, the direct output of which is connected to the second input of the first OR element, the clock input of the device is connected with the counting input of the first counter and through the first delay element with the reset input to zero the younger (- q) bits of the second counter, the conversion inputs with weights 2 and which are connected to the outputs of the co respectively first and second AND gates, the output of the first AND element is connected via a second delay element with a first input of a second OR gate, the output of the second AND element is connected to the synchronization input of the first adder and via the third delay element with the synchronizing input of the third 0 0 element And, the second input of which is connected to the inverse output of the first trigger, the output of the third element And is connected to the second input of the second element OR, the output of which is connected to the synchronizing input of the fourth register, the first, second and third inputs of the second element AND to the inverse output of the first trigger 55 pa, with the direct output of the second trigger and the output of the generator of clock pulses, respectively.