SU1298804A1 - Shift register - Google Patents

Abstract

The invention relates to a computational technique and can be used in matrix ycTpoiiCToax information shifts. The aim of the invention is to improve the speed of the register and to enable it to operate in two-stroke (normal) and notact (accelerated) shift modes. To achieve this goal, in each cell of us a matrix of storage, consisting of two tripleters, six AND elements and two IDN elements, are introduced by two Element1GY AND elements and one IDN element, allowing to provide for the not active input and shift of information. 2 Il. ts5; about 00 00

Description

The invention relates to computing and can be used in matrix devices for shifting information.

The purpose of the invention is to improve the speed and to enable operation in two-stroke (normal) and tact (accelerated) shift modes.

FIG. 1 is a diagram of the shift register; in fig. 2 is a cell diagram.

The shift register (Fig. 1) contains memory cells 1, each of which has four information inputs for receiving information on the left 2, on the top 3, on the right 4 and on the bottom 5 and exit 6.

Shift control inputs to the right 7, down 8, left 9 and up 10, the first 11 and the second 12 clock inputs, the resolution inputs of the push-pull 13 and the actual 14 shift modes (Fig. 1) are also shown. The memory cell (Fig. 2) contains eight elements AND 15-22, three elements OR 23-25 and two D-flip-flops 26 and 27.

The shift register works as follows.

The mode of operation is push-pull. Let us assume for definiteness that binary information will be advanced from left to right.

Before entering, the triggers of all memory cells (PL) are set to the state "O" (the circuit of the preliminary installation of the PL switches in Fig. 2 is not shown). Input 7 is supplied with a potential signal permitting information to be moved through the register to the right: elements AND 15 memory cells are prepared to skip the information to the right. Bus 13 is supplied with a potential signal permitting the operation of the PL in a push-pull mode, while serially connecting the first and second PL triggers with each other. P1INY 11 and 12 receive impulses of both clock sequences.

According to the T1 clock, the input information is fed to the inputs of the 2 left PLs, which form the first column of the matrix. This information, the passage through the elements AND 15, OR 23 are memorized by the triggers of the 26 memory cells of the first column of the matrix register.

According to the T2 cycle, the information on the inputs 2 is not received. From the outputs of the flip-flops 26, the information passes through the elements AND 19, .OR 24, and is memorized by the triggers of 27 memory cells of the first column of the matrix.

By the next clock cycle T 1 (second on the account), the new information is fed to the inputs 2 of the left PLs and is memorized by the triggers of 26 memory cells of the first column of the matrix. In addition, the clock pulse T1 permits the census of information from the triggers of the 27 memory cells of the first column of the matrix to the triggers of 26 memory cells of the second column of the matrix.

For the next T2 cycle (second in a row), information is not received at inputs 2. The T2 clock pulse permits the census of information from triggers of 26 cells

memory of the first and second columns. matrices in triggers 27 memory cells of these columns of the matrix.

Further recording and promotion of information occurs in a similar way. After recording the information in the register

the shift from input 7 is removed.

Mode of operation is tactile. Before entering, the triggers of all PLs are set to the state "O. Input 7 is supplied with a potential signal that allows information to move to the right. A potential signal is applied to input 14 permitting the operation of the PL in the continuous mode; this signal is fed to the control inputs of the AND 20 and 21 elements, providing the first and second triggers in all the PLs in parallel with each other. The inputs 11 and 12 receive the pulses of both clock sequences.

According to the T1 clock, the input information is fed to the inputs of the 2 left PLs. Passing through the elements AND 15, OR 23, it is remembered by the triggers 26 cells of the first column of the matrix.

By T2 cycle, the second bits of input information are received at the inputs of the 2 left PLs. Passing through elements AND 20, OR 24, these bits are remembered by the triggers of 27 memory cells of the first column of the matrix. In addition, information stored on triggers 23 of the first PL, pass through the AND 21 elements, OR 25 memory cells of the first column of the matrix, goes through the AND 15, OR 23 elements to write to the triggers 26 cells of the first and second cells of the matrix .

According to the next T1 cycle (second in succession), the next (third) bits of the input information arrive at the inputs of the left PL. Passing through the elements AND 15, OR 23, they are memorized by the triggers of 26 memory cells of the first column of the matrix. In addition, the first bits of the input information through the open elements AND 22, OR 25 from the outputs of the triggers 27 memory cells of the second column of the matrix are written to the triggers 26 of the third column of the matrix, and the second bits from the outputs of the triggers 27 of the first column of the matrix to write to the triggers 26 of the second column of the matrix. Thus, the three clock cycles (two clock cycles T1 and one clock cycle T2) of the three bits of the information are placed in the matrix register. With push-pull shift control, such a record requires 6 clocks (three beats of T1 and three beats of T2). When the recording of information into the shift register from input 7 is completed, a signal is removed.

Claims (1)

Invention Formula A shift register containing a matrix of memory cells, each of which consists of the first and second D-flip-flops, six AND elements and two OR elements, with the outputs of the first, second, third and fourth AND elements connected to the inputs of the first OR element, the output of which is the D input of the first D-flip-flop, the outputs of the fifth and sixth And elements are connected to the inputs of the second OR element, the output of which is connected to the D-input of the second D-flip-flop, the C-inputs of the first and second D-flip-flops are respectively the first and the second clock inputs reg the shift stratum, the first inputs of the first, third, second, and fourth elements AND of each memory cell are the right, left, down, and upward shift control inputs, respectively, the second inputs of the first, third, second, and fourth elements of the first and last memory cells These in each row and in each column of the matrix are the information inputs for shifting right, left, down and up respectively, and the data outputs of the cells are respectively the information outputs of the register when shifting left, right, up and down in Doi matrix row of the second input of the first element of each memory cell other than the first, with a yield of previous oedinen chey0 memory, and the second input of the third element AND each memory cell, except the last, - with the output of the subsequent memory cell, and in each matrix column the second input of the second element AND each memory cell, except the first, is connected to the output of the previous memory cell and the second input of the fourth element AND of each memory cell, except the last, with the output of the subsequent memory cell, characterized in that, in order to increase speed and enable operation in two-stroke and continuous modes, each cell is inserted seventh and eighth uh elements and the third 5 element OR, the first input of the fifth element AND being the resolution input of the push-pull mode, and the first inputs of the sixth and seventh elements AND - the resolution inputs of the cycle mode, the second inputs of the fifth and seventh elements AND are connected to the output of the first D-flip-flop, D -input of which is connected to the second input of the signal element I, and C input to the first input of the eighth element I, the second input of which is connected to the output of the second D flip-flop, C input of which is connected to the third input of the seventh element I, output of the eighth element I connected to the first stroke third OR gate, a second input coupled to an output of the seventh AND gate, and the output is the output of the memory cell. Compiled by A. Deriugin Editor A. SaboTechred I. VeresKorrektor O. Lugova Order 751/54 Circulation 590 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4